1 /* 2 * Copyright (c) 2022-2023, Arm Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef CORTEX_A510_H 8 #define CORTEX_A510_H 9 10 #define CORTEX_A510_MIDR U(0x410FD460) 11 12 /******************************************************************************* 13 * CPU Extended Control register specific definitions 14 ******************************************************************************/ 15 #define CORTEX_A510_CPUECTLR_EL1 S3_0_C15_C1_4 16 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_SHIFT U(19) 17 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_WIDTH U(1) 18 #define CORTEX_A510_CPUECTLR_EL1_READPREFERUNIQUE_DISABLE U(1) 19 #define CORTEX_A510_CPUECTLR_EL1_RSCTL_SHIFT U(23) 20 #define CORTEX_A510_CPUECTLR_EL1_NTCTL_SHIFT U(46) 21 #define CORTEX_A510_CPUECTLR_EL1_ATOM_EXECALLINSTRNEAR U(2) 22 #define CORTEX_A510_CPUECTLR_EL1_ATOM_SHIFT U(38) 23 #define CORTEX_A510_CPUECTLR_EL1_ATOM_WIDTH U(3) 24 25 /******************************************************************************* 26 * CPU Power Control register specific definitions 27 ******************************************************************************/ 28 #define CORTEX_A510_CPUPWRCTLR_EL1 S3_0_C15_C2_7 29 #define CORTEX_A510_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) 30 31 /******************************************************************************* 32 * Complex auxiliary control register specific definitions 33 ******************************************************************************/ 34 #define CORTEX_A510_CMPXACTLR_EL1 S3_0_C15_C1_3 35 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 36 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(25) 37 #define CORTEX_A510_CMPXACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 38 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_DISABLE U(3) 39 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_SHIFT U(10) 40 #define CORTEX_A510_CMPXACTLR_EL1_SNPPREFERUNIQUE_WIDTH U(2) 41 42 /******************************************************************************* 43 * Auxiliary control register specific definitions 44 ******************************************************************************/ 45 #define CORTEX_A510_CPUACTLR_EL1 S3_0_C15_C1_0 46 #define CORTEX_A510_CPUACTLR_EL1_BIT_17 (ULL(1) << 17) 47 #define CORTEX_A510_CPUACTLR_EL1_BIT_38 (ULL(1) << 38) 48 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_DISABLE U(1) 49 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_SHIFT U(18) 50 #define CORTEX_A510_CPUACTLR_EL1_ALIAS_LOADSTORE_WIDTH U(1) 51 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_DISABLE U(1) 52 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_SHIFT U(18) 53 #define CORTEX_A510_CPUACTLR_EL1_DATA_CORRUPT_WIDTH U(1) 54 55 #endif /* CORTEX_A510_H */ 56
