1 /*
2  * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef CORTEX_A35_H
8 #define CORTEX_A35_H
9 
10 #include <lib/utils_def.h>
11 
12 /* Cortex-A35 Main ID register for revision 0 */
13 #define CORTEX_A35_MIDR				U(0x410FD040)
14 
15 /*******************************************************************************
16  * CPU Extended Control register specific definitions.
17  * CPUECTLR_EL1 is an implementation-specific register.
18  ******************************************************************************/
19 #define CORTEX_A35_CPUECTLR_EL1			S3_1_C15_C2_1
20 #define CORTEX_A35_CPUECTLR_SMPEN_BIT		(ULL(1) << 6)
21 
22 /*******************************************************************************
23  * CPU Auxiliary Control register specific definitions.
24  ******************************************************************************/
25 #define CORTEX_A35_CPUACTLR_EL1			S3_1_C15_C2_0
26 
27 #define CORTEX_A35_CPUACTLR_EL1_ENDCCASCI	(ULL(1) << 44)
28 
29 #endif /* CORTEX_A35_H */
30