1 /* 2 * Copyright (c) 2017-2021 Arm Limited. All rights reserved. 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 /* 18 * This file is derivative of CMSIS V5.01: 19 * Device\_Template_Vendor\Vendor\Device\Include\Device.h 20 */ 21 22 #ifndef __PLATFORM_BASE_ADDRESS_H__ 23 #define __PLATFORM_BASE_ADDRESS_H__ 24 25 /* Secure Enclave Peripheral base addresses */ 26 #define CORSTONE1000_ROM_BASE (0x00000000U) /* SE ROM Region */ 27 #define CORSTONE1000_CRYPTO_ACCELERATOR_BASE (0x2F000000U) /* Crypto Accelerator */ 28 #define CORSTONE1000_SRAM_BASE (0x30000000U) /* SE RAM Region */ 29 #define CORSTONE1000_PERIPHERAL_BASE (0x50000000U) /* SE Peripheral Region */ 30 #define CORSTONE1000_CMSDK_TIMER_0_BASE (0x50000000U) /* CMSDK Timer 0 */ 31 #define CORSTONE1000_CMSDK_TIMER_1_BASE (0x50001000U) /* CMSDK Timer 1 */ 32 #define CORSTONE1000_SEH_0_SENDER_BASE (0x50003000U) /* SEH0 Sender */ 33 #define CORSTONE1000_HSE_0_RECEIVER_BASE (0x50004000U) /* HSE1 Receiver */ 34 #define CORSTONE1000_SEH_1_SENDER_BASE (0x50005000U) /* SEH1 Sender */ 35 #define CORSTONE1000_HSE_1_RECEIVER_BASE (0x50006000U) /* HSE1 Receiver */ 36 /* Not all of the SEESx/ESxSE peripherals will be applicable, depending on the 37 * number of external systems present */ 38 #define CORSTONE1000_SEES0_0_SENDER_BASE (0x50010000U) /* SEES0 0 Sender */ 39 #define CORSTONE1000_ES0SE_0_RECEIVER_BASE (0x50011000U) /* ES0SE 0 Receiver */ 40 #define CORSTONE1000_SEES0_1_SENDER_BASE (0x50012000U) /* SEES0 1 Sender */ 41 #define CORSTONE1000_ES0SE_1_RECEIVER_BASE (0x50013000U) /* ES0SE 1 Receiver */ 42 #define CORSTONE1000_SEES1_0_SENDER_BASE (0x50014000U) /* SEES1 0 Sender */ 43 #define CORSTONE1000_ES1SE_0_RECEIVER_BASE (0x50015000U) /* ES1SE 0 Receiver */ 44 #define CORSTONE1000_SEES1_1_SENDER_BASE (0x50016000U) /* SEES1 1 Sender */ 45 #define CORSTONE1000_ES1SE_1_RECEIVER_BASE (0x50017000U) /* ES1SE 1 Receiver */ 46 #define CORSTONE1000_SEES2_0_SENDER_BASE (0x50018000U) /* SEES2 0 Sender */ 47 #define CORSTONE1000_ES2SE_0_RECEIVER_BASE (0x50019000U) /* ES2SE 0 Receiver */ 48 #define CORSTONE1000_SEES2_1_SENDER_BASE (0x5001A000U) /* SEES2 1 Sender */ 49 #define CORSTONE1000_ES2SE_1_RECEIVER_BASE (0x5001B000U) /* ES2SE 1 Receiver */ 50 #define CORSTONE1000_SEES3_0_SENDER_BASE (0x5001C000U) /* SEES3 0 Sender */ 51 #define CORSTONE1000_ES3SE_0_RECEIVER_BASE (0x5001D000U) /* ES3SE 0 Receiver */ 52 #define CORSTONE1000_SEES3_1_SENDER_BASE (0x5001E000U) /* SEES3 1 Sender */ 53 #define CORSTONE1000_ES3SE_1_RECEIVER_BASE (0x5001F000U) /* ES3SE 1 Receiver */ 54 #define CORSTONE1000_SCR_BASE (0x50080000U) /* System Control Register */ 55 #define CORSTONE1000_WATCHDOG_TIMER_BASE (0x50081000U) /* Watchdog Timer */ 56 #define CORSTONE1000_SECENCTOP_PPU_BASE (0x5008D000U) /* SECENCTOP PPU */ 57 #define CORSTONE1000_BASE_SCR_BASE (0x5008E000U) /* SE Base System Control Register */ 58 #define CORSTONE1000_SOC_WATCHDOG_BASE (0x5008F000U) /* SoC Watchdog */ 59 #define CORSTONE1000_UART_BASE (0x50090000U) /* UART */ 60 #define CORSTONE1000_SE_FIREWALL_BASE (0x50200000U) /* SE Firewall */ 61 #define CORSTONE1000_HOST_ACCESS_REGION_BASE (0x60000000U) /* Host Access Region */ 62 #define CORSTONE1000_PPB_BASE (0xE0000000U) /* Private Peripheral Bus (PPB) */ 63 #define CORSTONE1000_CS_ROM_BASE (0xF0000000U) /* SE CS ROM */ 64 #define CORSTONE1000_CTI_BASE (0xF0001000U) /* SE CTI */ 65 66 /* Host base addresses from the SE perspective - partial list, only the ones 67 * required by the SE are defined here */ 68 #define CORSTONE1000_HOST_ADDRESS_SPACE_BASE (0x60000000U) /* Host Address Space */ 69 #define CORSTONE1000_HOST_BIR_BASE (0x60000000U) /* Boot Instruction Register */ 70 #define CORSTONE1000_HOST_SHARED_RAM_BASE (0x62000000U) /* Shared RAM */ 71 #define CORSTONE1000_HOST_XNVM_BASE (0x68000000U) /* XNVM */ 72 #define CORSTONE1000_HOST_BASE_SYSTEM_CONTROL_BASE (0x7A010000U) /* Host SCB */ 73 #define CORSTONE1000_EXT_SYS_RESET_REG (0x7A010310U) /* external system (cortex-M3) */ 74 #define CORSTONE1000_HOST_FIREWALL_BASE (0x7A800000U) /* Host Firewall */ 75 #define CORSTONE1000_HOST_INT_APBCOM_BASE (0x7B900000U) /* Internal APBCOM */ 76 #define CORSTONE1000_HOST_FPGA_SCC_REGISTERS (0x80000000U) /* FPGA SCC Registers */ 77 #define CORSTONE1000_HOST_SE_SECURE_FLASH_BASE_FVP (0x80010000U) /* SE Flash */ 78 #define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE (0x80050000U) /* AXI QSPI Controller */ 79 #define CORSTONE1000_HOST_AXI_QSPI_CTRL_REG_BASE_SE_SECURE_FLASH (0x90010000U) /* AXI QSPI Controller for SE FLash */ 80 #define CORSTONE1000_HOST_DRAM_UEFI_CAPSULE (0xA0000000U) /* 1.5 GB DDR */ 81 82 /* Map Component definitions to Corstone definitions */ 83 #define CC3XX_BASE_S CORSTONE1000_CRYPTO_ACCELERATOR_BASE 84 85 #endif /* __PLATFORM_BASE_ADDRESS_H__ */ 86
