1 /***************************************************************************//** 2 * \file cyip_mxcordic_1_0.h 3 * 4 * \brief 5 * MXCORDIC_1_0 IP definitions 6 * 7 ******************************************************************************** 8 * \copyright 9 * (c) (2016-2024), Cypress Semiconductor Corporation (an Infineon company) or 10 * an affiliate of Cypress Semiconductor Corporation. 11 * 12 * SPDX-License-Identifier: Apache-2.0 13 * 14 * Licensed under the Apache License, Version 2.0 (the "License"); 15 * you may not use this file except in compliance with the License. 16 * You may obtain a copy of the License at 17 * 18 * http://www.apache.org/licenses/LICENSE-2.0 19 * 20 * Unless required by applicable law or agreed to in writing, software 21 * distributed under the License is distributed on an "AS IS" BASIS, 22 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 23 * See the License for the specific language governing permissions and 24 * limitations under the License. 25 *******************************************************************************/ 26 27 #ifndef _CYIP_MXCORDIC_1_0_H_ 28 #define _CYIP_MXCORDIC_1_0_H_ 29 30 #include "cyip_headers.h" 31 32 /******************************************************************************* 33 * MXCORDIC_1_0 34 *******************************************************************************/ 35 36 #define MXCORDIC_1_0_SECTION_SIZE 0x00010000UL 37 38 /** 39 * \brief N/A (MXCORDIC_1_0) 40 */ 41 typedef struct { 42 __IOM uint32_t CTL; /*!< 0x00000000 N/A */ 43 __IM uint32_t RESERVED; 44 __IM uint32_t ID; /*!< 0x00000008 Module Identification Register */ 45 __IM uint32_t RESERVED1; 46 __IOM uint32_t INTR; /*!< 0x00000010 Interrupt Cause Register */ 47 __IOM uint32_t INTR_SET; /*!< 0x00000014 Interrupt Set Register */ 48 __IOM uint32_t INTR_MASK; /*!< 0x00000018 Interrupt Mask Register */ 49 __IM uint32_t INTR_MASKED; /*!< 0x0000001C Interrupt Masked Register */ 50 __IM uint32_t RESERVED2[8]; 51 __IOM uint32_t KEEP; /*!< 0x00000040 CORDIC Keep Register */ 52 __IOM uint32_t CON; /*!< 0x00000044 CORDIC Control Register */ 53 __IOM uint32_t CORDX; /*!< 0x00000048 CORDIC X Data Register */ 54 __IOM uint32_t CORDY; /*!< 0x0000004C CORDIC Y Data Register */ 55 __IOM uint32_t CORDZ; /*!< 0x00000050 CORDIC Z Data Register */ 56 __IM uint32_t CORRX; /*!< 0x00000054 CORDIC X Result Register */ 57 __IM uint32_t CORRY; /*!< 0x00000058 CORDIC Y Result Register */ 58 __IM uint32_t CORRZ; /*!< 0x0000005C CORDIC Z Result Register */ 59 __IM uint32_t STAT; /*!< 0x00000060 CORDIC Status Register */ 60 __IOM uint32_t START_CMD; /*!< 0x00000064 CORDIC Start Command Register */ 61 } MXCORDIC_1_0_Type; /*!< Size = 104 (0x68) */ 62 63 64 /* MXCORDIC_1_0.CTL */ 65 #define MXCORDIC_1_0_CTL_ENABLED_Pos 31UL 66 #define MXCORDIC_1_0_CTL_ENABLED_Msk 0x80000000UL 67 /* MXCORDIC_1_0.ID */ 68 #define MXCORDIC_1_0_ID_MOD_REV_Pos 0UL 69 #define MXCORDIC_1_0_ID_MOD_REV_Msk 0xFFUL 70 #define MXCORDIC_1_0_ID_MOD_TYPE_Pos 8UL 71 #define MXCORDIC_1_0_ID_MOD_TYPE_Msk 0xFF00UL 72 #define MXCORDIC_1_0_ID_MOD_NUMBER_Pos 16UL 73 #define MXCORDIC_1_0_ID_MOD_NUMBER_Msk 0xFFFF0000UL 74 /* MXCORDIC_1_0.INTR */ 75 #define MXCORDIC_1_0_INTR_CDEOC_Pos 2UL 76 #define MXCORDIC_1_0_INTR_CDEOC_Msk 0x4UL 77 #define MXCORDIC_1_0_INTR_CDERR_Pos 3UL 78 #define MXCORDIC_1_0_INTR_CDERR_Msk 0x8UL 79 /* MXCORDIC_1_0.INTR_SET */ 80 #define MXCORDIC_1_0_INTR_SET_CDEOC_Pos 2UL 81 #define MXCORDIC_1_0_INTR_SET_CDEOC_Msk 0x4UL 82 #define MXCORDIC_1_0_INTR_SET_CDERR_Pos 3UL 83 #define MXCORDIC_1_0_INTR_SET_CDERR_Msk 0x8UL 84 /* MXCORDIC_1_0.INTR_MASK */ 85 #define MXCORDIC_1_0_INTR_MASK_CDEOC_Pos 2UL 86 #define MXCORDIC_1_0_INTR_MASK_CDEOC_Msk 0x4UL 87 #define MXCORDIC_1_0_INTR_MASK_CDERR_Pos 3UL 88 #define MXCORDIC_1_0_INTR_MASK_CDERR_Msk 0x8UL 89 /* MXCORDIC_1_0.INTR_MASKED */ 90 #define MXCORDIC_1_0_INTR_MASKED_CDEOC_Pos 2UL 91 #define MXCORDIC_1_0_INTR_MASKED_CDEOC_Msk 0x4UL 92 #define MXCORDIC_1_0_INTR_MASKED_CDERR_Pos 3UL 93 #define MXCORDIC_1_0_INTR_MASKED_CDERR_Msk 0x8UL 94 /* MXCORDIC_1_0.KEEP */ 95 #define MXCORDIC_1_0_KEEP_KEEPX_Pos 5UL 96 #define MXCORDIC_1_0_KEEP_KEEPX_Msk 0x20UL 97 #define MXCORDIC_1_0_KEEP_KEEPY_Pos 6UL 98 #define MXCORDIC_1_0_KEEP_KEEPY_Msk 0x40UL 99 #define MXCORDIC_1_0_KEEP_KEEPZ_Pos 7UL 100 #define MXCORDIC_1_0_KEEP_KEEPZ_Msk 0x80UL 101 /* MXCORDIC_1_0.CON */ 102 #define MXCORDIC_1_0_CON_MODE_Pos 1UL 103 #define MXCORDIC_1_0_CON_MODE_Msk 0x6UL 104 #define MXCORDIC_1_0_CON_ROTVEC_Pos 3UL 105 #define MXCORDIC_1_0_CON_ROTVEC_Msk 0x8UL 106 #define MXCORDIC_1_0_CON_ST_MODE_Pos 4UL 107 #define MXCORDIC_1_0_CON_ST_MODE_Msk 0x10UL 108 #define MXCORDIC_1_0_CON_X_USIGN_Pos 5UL 109 #define MXCORDIC_1_0_CON_X_USIGN_Msk 0x20UL 110 #define MXCORDIC_1_0_CON_MPS_Pos 6UL 111 #define MXCORDIC_1_0_CON_MPS_Msk 0xC0UL 112 #define MXCORDIC_1_0_CON_N_ITER_Pos 8UL 113 #define MXCORDIC_1_0_CON_N_ITER_Msk 0x700UL 114 /* MXCORDIC_1_0.CORDX */ 115 #define MXCORDIC_1_0_CORDX_DATA_Pos 8UL 116 #define MXCORDIC_1_0_CORDX_DATA_Msk 0xFFFFFF00UL 117 /* MXCORDIC_1_0.CORDY */ 118 #define MXCORDIC_1_0_CORDY_DATA_Pos 8UL 119 #define MXCORDIC_1_0_CORDY_DATA_Msk 0xFFFFFF00UL 120 /* MXCORDIC_1_0.CORDZ */ 121 #define MXCORDIC_1_0_CORDZ_DATA_Pos 8UL 122 #define MXCORDIC_1_0_CORDZ_DATA_Msk 0xFFFFFF00UL 123 /* MXCORDIC_1_0.CORRX */ 124 #define MXCORDIC_1_0_CORRX_RESULT_Pos 8UL 125 #define MXCORDIC_1_0_CORRX_RESULT_Msk 0xFFFFFF00UL 126 /* MXCORDIC_1_0.CORRY */ 127 #define MXCORDIC_1_0_CORRY_RESULT_Pos 8UL 128 #define MXCORDIC_1_0_CORRY_RESULT_Msk 0xFFFFFF00UL 129 /* MXCORDIC_1_0.CORRZ */ 130 #define MXCORDIC_1_0_CORRZ_RESULT_Pos 8UL 131 #define MXCORDIC_1_0_CORRZ_RESULT_Msk 0xFFFFFF00UL 132 /* MXCORDIC_1_0.STAT */ 133 #define MXCORDIC_1_0_STAT_BSY_Pos 0UL 134 #define MXCORDIC_1_0_STAT_BSY_Msk 0x1UL 135 /* MXCORDIC_1_0.START_CMD */ 136 #define MXCORDIC_1_0_START_CMD_ST_Pos 0UL 137 #define MXCORDIC_1_0_START_CMD_ST_Msk 0x1UL 138 139 140 #endif /* _CYIP_MXCORDIC_1_0_H_ */ 141 142 143 /* [] END OF FILE */ 144
