1 /* Auto-generated config file peripheral_clk_config.h */ 2 #ifndef PERIPHERAL_CLK_CONFIG_H 3 #define PERIPHERAL_CLK_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 // <y> EIC Clock Source 8 // <id> eic_gclk_selection 9 10 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 11 12 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 13 14 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 15 16 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 17 18 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 19 20 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 21 22 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 23 24 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 25 26 // <i> Select the clock source for EIC. 27 #ifndef CONF_GCLK_EIC_SRC 28 #define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 29 #endif 30 31 /** 32 * \def CONF_GCLK_EIC_FREQUENCY 33 * \brief EIC's Clock frequency 34 */ 35 #ifndef CONF_GCLK_EIC_FREQUENCY 36 #define CONF_GCLK_EIC_FREQUENCY 16000000 37 #endif 38 39 /** 40 * \def CONF_CPU_FREQUENCY 41 * \brief CPU's Clock frequency 42 */ 43 #ifndef CONF_CPU_FREQUENCY 44 #define CONF_CPU_FREQUENCY 16000000 45 #endif 46 47 // <y> RTC Clock Source 48 // <id> rtc_clk_selection 49 // <RTC_CLOCK_SOURCE"> RTC source 50 // <i> Select the clock source for RTC. 51 #ifndef CONF_GCLK_RTC_SRC 52 #define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE 53 #endif 54 55 /** 56 * \def CONF_GCLK_RTC_FREQUENCY 57 * \brief RTC's Clock frequency 58 */ 59 #ifndef CONF_GCLK_RTC_FREQUENCY 60 #define CONF_GCLK_RTC_FREQUENCY 1024 61 #endif 62 63 // <y> Core Clock Source 64 // <id> core_gclk_selection 65 66 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 67 68 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 69 70 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 71 72 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 73 74 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 75 76 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 77 78 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 79 80 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 81 82 // <i> Select the clock source for CORE. 83 #ifndef CONF_GCLK_SERCOM0_CORE_SRC 84 #define CONF_GCLK_SERCOM0_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 85 #endif 86 87 // <y> Slow Clock Source 88 // <id> slow_gclk_selection 89 90 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 91 92 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 93 94 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 95 96 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 97 98 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 99 100 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 101 102 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 103 104 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 105 106 // <i> Select the slow clock source. 107 #ifndef CONF_GCLK_SERCOM0_SLOW_SRC 108 #define CONF_GCLK_SERCOM0_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 109 #endif 110 111 /** 112 * \def CONF_GCLK_SERCOM0_CORE_FREQUENCY 113 * \brief SERCOM0's Core Clock frequency 114 */ 115 #ifndef CONF_GCLK_SERCOM0_CORE_FREQUENCY 116 #define CONF_GCLK_SERCOM0_CORE_FREQUENCY 16000000 117 #endif 118 119 /** 120 * \def CONF_GCLK_SERCOM0_SLOW_FREQUENCY 121 * \brief SERCOM0's Slow Clock frequency 122 */ 123 #ifndef CONF_GCLK_SERCOM0_SLOW_FREQUENCY 124 #define CONF_GCLK_SERCOM0_SLOW_FREQUENCY 16000000 125 #endif 126 127 // <y> Core Clock Source 128 // <id> core_gclk_selection 129 130 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 131 132 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 133 134 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 135 136 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 137 138 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 139 140 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 141 142 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 143 144 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 145 146 // <i> Select the clock source for CORE. 147 #ifndef CONF_GCLK_SERCOM1_CORE_SRC 148 #define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 149 #endif 150 151 // <y> Slow Clock Source 152 // <id> slow_gclk_selection 153 154 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 155 156 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 157 158 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 159 160 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 161 162 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 163 164 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 165 166 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 167 168 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 169 170 // <i> Select the slow clock source. 171 #ifndef CONF_GCLK_SERCOM1_SLOW_SRC 172 #define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 173 #endif 174 175 /** 176 * \def CONF_GCLK_SERCOM1_CORE_FREQUENCY 177 * \brief SERCOM1's Core Clock frequency 178 */ 179 #ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY 180 #define CONF_GCLK_SERCOM1_CORE_FREQUENCY 16000000 181 #endif 182 183 /** 184 * \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY 185 * \brief SERCOM1's Slow Clock frequency 186 */ 187 #ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY 188 #define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 16000000 189 #endif 190 191 // <y> Core Clock Source 192 // <id> core_gclk_selection 193 194 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 195 196 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 197 198 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 199 200 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 201 202 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 203 204 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 205 206 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 207 208 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 209 210 // <i> Select theRADIO_RESET clock source for CORE. 211 #ifndef CONF_GCLK_SERCOM4_CORE_SRC 212 #define CONF_GCLK_SERCOM4_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 213 #endif 214 215 // <y> Slow Clock Source 216 // <id> slow_gclk_selection 217 218 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 219 220 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 221 222 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 223 224 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 225 226 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 227 228 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 229 230 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 231 232 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 233 234 // <i> Select the slow clock source. 235 #ifndef CONF_GCLK_SERCOM4_SLOW_SRC 236 #define CONF_GCLK_SERCOM4_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK0_Val 237 #endif 238 239 /** 240 * \def CONF_GCLK_SERCOM4_CORE_FREQUENCY 241 * \brief SERCOM4's Core Clock frequency 242 */ 243 #ifndef CONF_GCLK_SERCOM4_CORE_FREQUENCY 244 #define CONF_GCLK_SERCOM4_CORE_FREQUENCY 16000000 245 #endif 246 247 /** 248 * \def CONF_GCLK_SERCOM4_SLOW_FREQUENCY 249 * \brief SERCOM4's Slow Clock frequency 250 */ 251 #ifndef CONF_GCLK_SERCOM4_SLOW_FREQUENCY 252 #define CONF_GCLK_SERCOM4_SLOW_FREQUENCY 16000000 253 #endif 254 255 // <<< end of configuration section >>> 256 257 #endif // PERIPHERAL_CLK_CONFIG_H 258
