1 /* Auto-generated config file hpl_gclk_config.h */ 2 #ifndef HPL_GCLK_CONFIG_H 3 #define HPL_GCLK_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 // <e> Generic clock generator 0 configuration 8 // <i> Indicates whether generic clock 0 configuration is enabled or not 9 // <id> enable_gclk_gen_0 10 #ifndef CONF_GCLK_GENERATOR_0_CONFIG 11 #define CONF_GCLK_GENERATOR_0_CONFIG 1 12 #endif 13 14 // <h> Generic Clock Generator Control 15 // <y> Generic clock generator 0 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 16 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 17 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 18 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 19 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 20 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 21 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 22 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 23 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 24 // <i> This defines the clock source for generic clock generator 0 25 // <id> gclk_gen_0_oscillator 26 #ifndef CONF_GCLK_GEN_0_SOURCE 27 #define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M 28 #endif 29 30 // <q> Run in Standby 31 // <i> Indicates whether Run in Standby is enabled or not 32 // <id> gclk_arch_gen_0_runstdby 33 #ifndef CONF_GCLK_GEN_0_RUNSTDBY 34 #define CONF_GCLK_GEN_0_RUNSTDBY 0 35 #endif 36 37 // <q> Divide Selection 38 // <i> Indicates whether Divide Selection is enabled or not 39 //<id> gclk_gen_0_div_sel 40 #ifndef CONF_GCLK_GEN_0_DIVSEL 41 #define CONF_GCLK_GEN_0_DIVSEL 0 42 #endif 43 44 // <q> Output Enable 45 // <i> Indicates whether Output Enable is enabled or not 46 // <id> gclk_arch_gen_0_oe 47 #ifndef CONF_GCLK_GEN_0_OE 48 #define CONF_GCLK_GEN_0_OE 0 49 #endif 50 51 // <q> Output Off Value 52 // <i> Indicates whether Output Off Value is enabled or not 53 // <id> gclk_arch_gen_0_oov 54 #ifndef CONF_GCLK_GEN_0_OOV 55 #define CONF_GCLK_GEN_0_OOV 0 56 #endif 57 58 // <q> Improve Duty Cycle 59 // <i> Indicates whether Improve Duty Cycle is enabled or not 60 // <id> gclk_arch_gen_0_idc 61 #ifndef CONF_GCLK_GEN_0_IDC 62 #define CONF_GCLK_GEN_0_IDC 0 63 #endif 64 65 // <q> Generic Clock Generator Enable 66 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 67 // <id> gclk_arch_gen_0_enable 68 #ifndef CONF_GCLK_GEN_0_GENEN 69 #define CONF_GCLK_GEN_0_GENEN 1 70 #endif 71 // </h> 72 73 //<h> Generic Clock Generator Division 74 //<o> Generic clock generator 0 division <0x0000-0xFFFF> 75 // <id> gclk_gen_0_div 76 #ifndef CONF_GCLK_GEN_0_DIV 77 #define CONF_GCLK_GEN_0_DIV 1 78 #endif 79 // </h> 80 // </e> 81 82 // <e> Generic clock generator 1 configuration 83 // <i> Indicates whether generic clock 1 configuration is enabled or not 84 // <id> enable_gclk_gen_1 85 #ifndef CONF_GCLK_GENERATOR_1_CONFIG 86 #define CONF_GCLK_GENERATOR_1_CONFIG 0 87 #endif 88 89 // <h> Generic Clock Generator Control 90 // <y> Generic clock generator 1 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 91 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 92 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 93 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 94 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 95 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 96 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 97 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 98 // <i> This defines the clock source for generic clock generator 1 99 // <id> gclk_gen_1_oscillator 100 #ifndef CONF_GCLK_GEN_1_SOURCE 101 #define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_OSC16M 102 #endif 103 104 // <q> Run in Standby 105 // <i> Indicates whether Run in Standby is enabled or not 106 // <id> gclk_arch_gen_1_runstdby 107 #ifndef CONF_GCLK_GEN_1_RUNSTDBY 108 #define CONF_GCLK_GEN_1_RUNSTDBY 0 109 #endif 110 111 // <q> Divide Selection 112 // <i> Indicates whether Divide Selection is enabled or not 113 //<id> gclk_gen_1_div_sel 114 #ifndef CONF_GCLK_GEN_1_DIVSEL 115 #define CONF_GCLK_GEN_1_DIVSEL 0 116 #endif 117 118 // <q> Output Enable 119 // <i> Indicates whether Output Enable is enabled or not 120 // <id> gclk_arch_gen_1_oe 121 #ifndef CONF_GCLK_GEN_1_OE 122 #define CONF_GCLK_GEN_1_OE 0 123 #endif 124 125 // <q> Output Off Value 126 // <i> Indicates whether Output Off Value is enabled or not 127 // <id> gclk_arch_gen_1_oov 128 #ifndef CONF_GCLK_GEN_1_OOV 129 #define CONF_GCLK_GEN_1_OOV 0 130 #endif 131 132 // <q> Improve Duty Cycle 133 // <i> Indicates whether Improve Duty Cycle is enabled or not 134 // <id> gclk_arch_gen_1_idc 135 #ifndef CONF_GCLK_GEN_1_IDC 136 #define CONF_GCLK_GEN_1_IDC 0 137 #endif 138 139 // <q> Generic Clock Generator Enable 140 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 141 // <id> gclk_arch_gen_1_enable 142 #ifndef CONF_GCLK_GEN_1_GENEN 143 #define CONF_GCLK_GEN_1_GENEN 1 144 #endif 145 // </h> 146 147 //<h> Generic Clock Generator Division 148 //<o> Generic clock generator 1 division <0x0000-0xFFFF> 149 // <id> gclk_gen_1_div 150 #ifndef CONF_GCLK_GEN_1_DIV 151 #define CONF_GCLK_GEN_1_DIV 1 152 #endif 153 // </h> 154 // </e> 155 156 // <e> Generic clock generator 2 configuration 157 // <i> Indicates whether generic clock 2 configuration is enabled or not 158 // <id> enable_gclk_gen_2 159 #ifndef CONF_GCLK_GENERATOR_2_CONFIG 160 #define CONF_GCLK_GENERATOR_2_CONFIG 0 161 #endif 162 163 // <h> Generic Clock Generator Control 164 // <y> Generic clock generator 2 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 165 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 166 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 167 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 168 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 169 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 170 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 171 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 172 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 173 // <i> This defines the clock source for generic clock generator 2 174 // <id> gclk_gen_2_oscillator 175 #ifndef CONF_GCLK_GEN_2_SOURCE 176 #define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_OSC16M 177 #endif 178 179 // <q> Run in Standby 180 // <i> Indicates whether Run in Standby is enabled or not 181 // <id> gclk_arch_gen_2_runstdby 182 #ifndef CONF_GCLK_GEN_2_RUNSTDBY 183 #define CONF_GCLK_GEN_2_RUNSTDBY 0 184 #endif 185 186 // <q> Divide Selection 187 // <i> Indicates whether Divide Selection is enabled or not 188 //<id> gclk_gen_2_div_sel 189 #ifndef CONF_GCLK_GEN_2_DIVSEL 190 #define CONF_GCLK_GEN_2_DIVSEL 1 191 #endif 192 193 // <q> Output Enable 194 // <i> Indicates whether Output Enable is enabled or not 195 // <id> gclk_arch_gen_2_oe 196 #ifndef CONF_GCLK_GEN_2_OE 197 #define CONF_GCLK_GEN_2_OE 0 198 #endif 199 200 // <q> Output Off Value 201 // <i> Indicates whether Output Off Value is enabled or not 202 // <id> gclk_arch_gen_2_oov 203 #ifndef CONF_GCLK_GEN_2_OOV 204 #define CONF_GCLK_GEN_2_OOV 0 205 #endif 206 207 // <q> Improve Duty Cycle 208 // <i> Indicates whether Improve Duty Cycle is enabled or not 209 // <id> gclk_arch_gen_2_idc 210 #ifndef CONF_GCLK_GEN_2_IDC 211 #define CONF_GCLK_GEN_2_IDC 0 212 #endif 213 214 // <q> Generic Clock Generator Enable 215 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 216 // <id> gclk_arch_gen_2_enable 217 #ifndef CONF_GCLK_GEN_2_GENEN 218 #define CONF_GCLK_GEN_2_GENEN 1 219 #endif 220 // </h> 221 222 //<h> Generic Clock Generator Division 223 //<o> Generic clock generator 2 division <0x0000-0xFFFF> 224 // <id> gclk_gen_2_div 225 #ifndef CONF_GCLK_GEN_2_DIV 226 #define CONF_GCLK_GEN_2_DIV 1 227 #endif 228 // </h> 229 // </e> 230 231 // <e> Generic clock generator 3 configuration 232 // <i> Indicates whether generic clock 3 configuration is enabled or not 233 // <id> enable_gclk_gen_3 234 #ifndef CONF_GCLK_GENERATOR_3_CONFIG 235 #define CONF_GCLK_GENERATOR_3_CONFIG 0 236 #endif 237 238 // <h> Generic Clock Generator Control 239 // <y> Generic clock generator 3 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 240 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 241 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 242 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 243 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 244 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 245 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 246 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 247 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 248 // <i> This defines the clock source for generic clock generator 3 249 // <id> gclk_gen_3_oscillator 250 #ifndef CONF_GCLK_GEN_3_SOURCE 251 #define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K 252 #endif 253 254 // <q> Run in Standby 255 // <i> Indicates whether Run in Standby is enabled or not 256 // <id> gclk_arch_gen_3_runstdby 257 #ifndef CONF_GCLK_GEN_3_RUNSTDBY 258 #define CONF_GCLK_GEN_3_RUNSTDBY 0 259 #endif 260 261 // <q> Divide Selection 262 // <i> Indicates whether Divide Selection is enabled or not 263 //<id> gclk_gen_3_div_sel 264 #ifndef CONF_GCLK_GEN_3_DIVSEL 265 #define CONF_GCLK_GEN_3_DIVSEL 0 266 #endif 267 268 // <q> Output Enable 269 // <i> Indicates whether Output Enable is enabled or not 270 // <id> gclk_arch_gen_3_oe 271 #ifndef CONF_GCLK_GEN_3_OE 272 #define CONF_GCLK_GEN_3_OE 0 273 #endif 274 275 // <q> Output Off Value 276 // <i> Indicates whether Output Off Value is enabled or not 277 // <id> gclk_arch_gen_3_oov 278 #ifndef CONF_GCLK_GEN_3_OOV 279 #define CONF_GCLK_GEN_3_OOV 0 280 #endif 281 282 // <q> Improve Duty Cycle 283 // <i> Indicates whether Improve Duty Cycle is enabled or not 284 // <id> gclk_arch_gen_3_idc 285 #ifndef CONF_GCLK_GEN_3_IDC 286 #define CONF_GCLK_GEN_3_IDC 0 287 #endif 288 289 // <q> Generic Clock Generator Enable 290 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 291 // <id> gclk_arch_gen_3_enable 292 #ifndef CONF_GCLK_GEN_3_GENEN 293 #define CONF_GCLK_GEN_3_GENEN 1 294 #endif 295 // </h> 296 297 //<h> Generic Clock Generator Division 298 //<o> Generic clock generator 3 division <0x0000-0xFFFF> 299 // <id> gclk_gen_3_div 300 #ifndef CONF_GCLK_GEN_3_DIV 301 #define CONF_GCLK_GEN_3_DIV 1 302 #endif 303 // </h> 304 // </e> 305 306 // <e> Generic clock generator 4 configuration 307 // <i> Indicates whether generic clock 4 configuration is enabled or not 308 // <id> enable_gclk_gen_4 309 #ifndef CONF_GCLK_GENERATOR_4_CONFIG 310 #define CONF_GCLK_GENERATOR_4_CONFIG 0 311 #endif 312 313 // <h> Generic Clock Generator Control 314 // <y> Generic clock generator 4 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 315 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 316 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 317 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 318 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 319 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 320 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 321 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 322 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 323 // <i> This defines the clock source for generic clock generator 4 324 // <id> gclk_gen_4_oscillator 325 #ifndef CONF_GCLK_GEN_4_SOURCE 326 #define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_OSC16M 327 #endif 328 329 // <q> Run in Standby 330 // <i> Indicates whether Run in Standby is enabled or not 331 // <id> gclk_arch_gen_4_runstdby 332 #ifndef CONF_GCLK_GEN_4_RUNSTDBY 333 #define CONF_GCLK_GEN_4_RUNSTDBY 0 334 #endif 335 336 // <q> Divide Selection 337 // <i> Indicates whether Divide Selection is enabled or not 338 //<id> gclk_gen_4_div_sel 339 #ifndef CONF_GCLK_GEN_4_DIVSEL 340 #define CONF_GCLK_GEN_4_DIVSEL 0 341 #endif 342 343 // <q> Output Enable 344 // <i> Indicates whether Output Enable is enabled or not 345 // <id> gclk_arch_gen_4_oe 346 #ifndef CONF_GCLK_GEN_4_OE 347 #define CONF_GCLK_GEN_4_OE 0 348 #endif 349 350 // <q> Output Off Value 351 // <i> Indicates whether Output Off Value is enabled or not 352 // <id> gclk_arch_gen_4_oov 353 #ifndef CONF_GCLK_GEN_4_OOV 354 #define CONF_GCLK_GEN_4_OOV 0 355 #endif 356 357 // <q> Improve Duty Cycle 358 // <i> Indicates whether Improve Duty Cycle is enabled or not 359 // <id> gclk_arch_gen_4_idc 360 #ifndef CONF_GCLK_GEN_4_IDC 361 #define CONF_GCLK_GEN_4_IDC 0 362 #endif 363 364 // <q> Generic Clock Generator Enable 365 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 366 // <id> gclk_arch_gen_4_enable 367 #ifndef CONF_GCLK_GEN_4_GENEN 368 #define CONF_GCLK_GEN_4_GENEN 1 369 #endif 370 // </h> 371 372 //<h> Generic Clock Generator Division 373 //<o> Generic clock generator 4 division <0x0000-0xFFFF> 374 // <id> gclk_gen_4_div 375 #ifndef CONF_GCLK_GEN_4_DIV 376 #define CONF_GCLK_GEN_4_DIV 1 377 #endif 378 // </h> 379 // </e> 380 381 // <e> Generic clock generator 5 configuration 382 // <i> Indicates whether generic clock 5 configuration is enabled or not 383 // <id> enable_gclk_gen_5 384 #ifndef CONF_GCLK_GENERATOR_5_CONFIG 385 #define CONF_GCLK_GENERATOR_5_CONFIG 0 386 #endif 387 388 // <h> Generic Clock Generator Control 389 // <y> Generic clock generator 5 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 390 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 391 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 392 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 393 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 394 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 395 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 396 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 397 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 398 // <i> This defines the clock source for generic clock generator 5 399 // <id> gclk_gen_5_oscillator 400 #ifndef CONF_GCLK_GEN_5_SOURCE 401 #define CONF_GCLK_GEN_5_SOURCE GCLK_GENCTRL_SRC_OSC16M 402 #endif 403 404 // <q> Run in Standby 405 // <i> Indicates whether Run in Standby is enabled or not 406 // <id> gclk_arch_gen_5_runstdby 407 #ifndef CONF_GCLK_GEN_5_RUNSTDBY 408 #define CONF_GCLK_GEN_5_RUNSTDBY 0 409 #endif 410 411 // <q> Divide Selection 412 // <i> Indicates whether Divide Selection is enabled or not 413 //<id> gclk_gen_5_div_sel 414 #ifndef CONF_GCLK_GEN_5_DIVSEL 415 #define CONF_GCLK_GEN_5_DIVSEL 0 416 #endif 417 418 // <q> Output Enable 419 // <i> Indicates whether Output Enable is enabled or not 420 // <id> gclk_arch_gen_5_oe 421 #ifndef CONF_GCLK_GEN_5_OE 422 #define CONF_GCLK_GEN_5_OE 0 423 #endif 424 425 // <q> Output Off Value 426 // <i> Indicates whether Output Off Value is enabled or not 427 // <id> gclk_arch_gen_5_oov 428 #ifndef CONF_GCLK_GEN_5_OOV 429 #define CONF_GCLK_GEN_5_OOV 0 430 #endif 431 432 // <q> Improve Duty Cycle 433 // <i> Indicates whether Improve Duty Cycle is enabled or not 434 // <id> gclk_arch_gen_5_idc 435 #ifndef CONF_GCLK_GEN_5_IDC 436 #define CONF_GCLK_GEN_5_IDC 0 437 #endif 438 439 // <q> Generic Clock Generator Enable 440 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 441 // <id> gclk_arch_gen_5_enable 442 #ifndef CONF_GCLK_GEN_5_GENEN 443 #define CONF_GCLK_GEN_5_GENEN 1 444 #endif 445 // </h> 446 447 //<h> Generic Clock Generator Division 448 //<o> Generic clock generator 5 division <0x0000-0xFFFF> 449 // <id> gclk_gen_5_div 450 #ifndef CONF_GCLK_GEN_5_DIV 451 #define CONF_GCLK_GEN_5_DIV 1 452 #endif 453 // </h> 454 // </e> 455 456 // <e> Generic clock generator 6 configuration 457 // <i> Indicates whether generic clock 6 configuration is enabled or not 458 // <id> enable_gclk_gen_6 459 #ifndef CONF_GCLK_GENERATOR_6_CONFIG 460 #define CONF_GCLK_GENERATOR_6_CONFIG 0 461 #endif 462 463 // <h> Generic Clock Generator Control 464 // <y> Generic clock generator 6 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 465 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 466 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 467 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 468 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 469 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 470 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 471 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 472 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 473 // <i> This defines the clock source for generic clock generator 6 474 // <id> gclk_gen_6_oscillator 475 #ifndef CONF_GCLK_GEN_6_SOURCE 476 #define CONF_GCLK_GEN_6_SOURCE GCLK_GENCTRL_SRC_OSC16M 477 #endif 478 479 // <q> Run in Standby 480 // <i> Indicates whether Run in Standby is enabled or not 481 // <id> gclk_arch_gen_6_runstdby 482 #ifndef CONF_GCLK_GEN_6_RUNSTDBY 483 #define CONF_GCLK_GEN_6_RUNSTDBY 0 484 #endif 485 486 // <q> Divide Selection 487 // <i> Indicates whether Divide Selection is enabled or not 488 //<id> gclk_gen_6_div_sel 489 #ifndef CONF_GCLK_GEN_6_DIVSEL 490 #define CONF_GCLK_GEN_6_DIVSEL 0 491 #endif 492 493 // <q> Output Enable 494 // <i> Indicates whether Output Enable is enabled or not 495 // <id> gclk_arch_gen_6_oe 496 #ifndef CONF_GCLK_GEN_6_OE 497 #define CONF_GCLK_GEN_6_OE 0 498 #endif 499 500 // <q> Output Off Value 501 // <i> Indicates whether Output Off Value is enabled or not 502 // <id> gclk_arch_gen_6_oov 503 #ifndef CONF_GCLK_GEN_6_OOV 504 #define CONF_GCLK_GEN_6_OOV 0 505 #endif 506 507 // <q> Improve Duty Cycle 508 // <i> Indicates whether Improve Duty Cycle is enabled or not 509 // <id> gclk_arch_gen_6_idc 510 #ifndef CONF_GCLK_GEN_6_IDC 511 #define CONF_GCLK_GEN_6_IDC 0 512 #endif 513 514 // <q> Generic Clock Generator Enable 515 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 516 // <id> gclk_arch_gen_6_enable 517 #ifndef CONF_GCLK_GEN_6_GENEN 518 #define CONF_GCLK_GEN_6_GENEN 1 519 #endif 520 // </h> 521 522 //<h> Generic Clock Generator Division 523 //<o> Generic clock generator 6 division <0x0000-0xFFFF> 524 // <id> gclk_gen_6_div 525 #ifndef CONF_GCLK_GEN_6_DIV 526 #define CONF_GCLK_GEN_6_DIV 1 527 #endif 528 // </h> 529 // </e> 530 531 // <e> Generic clock generator 7 configuration 532 // <i> Indicates whether generic clock 7 configuration is enabled or not 533 // <id> enable_gclk_gen_7 534 #ifndef CONF_GCLK_GENERATOR_7_CONFIG 535 #define CONF_GCLK_GENERATOR_7_CONFIG 0 536 #endif 537 538 // <h> Generic Clock Generator Control 539 // <y> Generic clock generator 7 source// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 540 // <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad 541 // <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1 542 // <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) 543 // <GCLK_GENCTRL_SRC_OSC32K"> 32kHz High Accuracy Internal Oscillator (OSC32K) 544 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 545 // <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M) 546 // <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M) 547 // <GCLK_GENCTRL_SRC_DPLL96M"> Digital Phase Locked Loop (DPLL96M) 548 // <i> This defines the clock source for generic clock generator 7 549 // <id> gclk_gen_7_oscillator 550 #ifndef CONF_GCLK_GEN_7_SOURCE 551 #define CONF_GCLK_GEN_7_SOURCE GCLK_GENCTRL_SRC_OSC16M 552 #endif 553 554 // <q> Run in Standby 555 // <i> Indicates whether Run in Standby is enabled or not 556 // <id> gclk_arch_gen_7_runstdby 557 #ifndef CONF_GCLK_GEN_7_RUNSTDBY 558 #define CONF_GCLK_GEN_7_RUNSTDBY 0 559 #endif 560 561 // <q> Divide Selection 562 // <i> Indicates whether Divide Selection is enabled or not 563 //<id> gclk_gen_7_div_sel 564 #ifndef CONF_GCLK_GEN_7_DIVSEL 565 #define CONF_GCLK_GEN_7_DIVSEL 0 566 #endif 567 568 // <q> Output Enable 569 // <i> Indicates whether Output Enable is enabled or not 570 // <id> gclk_arch_gen_7_oe 571 #ifndef CONF_GCLK_GEN_7_OE 572 #define CONF_GCLK_GEN_7_OE 0 573 #endif 574 575 // <q> Output Off Value 576 // <i> Indicates whether Output Off Value is enabled or not 577 // <id> gclk_arch_gen_7_oov 578 #ifndef CONF_GCLK_GEN_7_OOV 579 #define CONF_GCLK_GEN_7_OOV 0 580 #endif 581 582 // <q> Improve Duty Cycle 583 // <i> Indicates whether Improve Duty Cycle is enabled or not 584 // <id> gclk_arch_gen_7_idc 585 #ifndef CONF_GCLK_GEN_7_IDC 586 #define CONF_GCLK_GEN_7_IDC 0 587 #endif 588 589 // <q> Generic Clock Generator Enable 590 // <i> Indicates whether Generic Clock Generator Enable is enabled or not 591 // <id> gclk_arch_gen_7_enable 592 #ifndef CONF_GCLK_GEN_7_GENEN 593 #define CONF_GCLK_GEN_7_GENEN 1 594 #endif 595 // </h> 596 597 //<h> Generic Clock Generator Division 598 //<o> Generic clock generator 7 division <0x0000-0xFFFF> 599 // <id> gclk_gen_7_div 600 #ifndef CONF_GCLK_GEN_7_DIV 601 #define CONF_GCLK_GEN_7_DIV 1 602 #endif 603 // </h> 604 // </e> 605 606 // <<< end of configuration section >>> 607 608 #endif // HPL_GCLK_CONFIG_H 609
