1 /* Auto-generated config file hpl_dmac_config.h */ 2 #ifndef HPL_DMAC_CONFIG_H 3 #define HPL_DMAC_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 // <e> DMAC enable 8 // <i> Indicates whether dmac is enabled or not 9 // <id> dmac_enable 10 #ifndef CONF_DMAC_ENABLE 11 #define CONF_DMAC_ENABLE 0 12 #endif 13 14 // <q> Priority Level 0 15 // <i> Indicates whether Priority Level 0 is enabled or not 16 // <id> dmac_lvlen0 17 #ifndef CONF_DMAC_LVLEN0 18 #define CONF_DMAC_LVLEN0 0 19 #endif 20 21 // <o> Level 0 Round-Robin Arbitration 22 // <0=> Static arbitration scheme for channel with priority 0 23 // <1=> Round-robin arbitration scheme for channel with priority 0 24 // <i> Defines Level 0 Arbitration for DMA channels 25 // <id> dmac_rrlvlen0 26 #ifndef CONF_DMAC_RRLVLEN0 27 #define CONF_DMAC_RRLVLEN0 0 28 #endif 29 30 // <o> Level 0 Channel Priority Number <0x00-0xFF> 31 // <id> dmac_lvlpri0 32 #ifndef CONF_DMAC_LVLPRI0 33 #define CONF_DMAC_LVLPRI0 0 34 #endif 35 36 // <q> Priority Level 1 37 // <i> Indicates whether Priority Level 1 is enabled or not 38 // <id> dmac_lvlen1 39 #ifndef CONF_DMAC_LVLEN1 40 #define CONF_DMAC_LVLEN1 0 41 #endif 42 43 // <o> Level 1 Round-Robin Arbitration 44 // <0=> Static arbitration scheme for channel with priority 1 45 // <1=> Round-robin arbitration scheme for channel with priority 1 46 // <i> Defines Level 1 Arbitration for DMA channels 47 // <id> dmac_rrlvlen1 48 #ifndef CONF_DMAC_RRLVLEN1 49 #define CONF_DMAC_RRLVLEN1 0 50 #endif 51 52 // <o> Level 1 Channel Priority Number <0x00-0xFF> 53 // <id> dmac_lvlpri1 54 #ifndef CONF_DMAC_LVLPRI1 55 #define CONF_DMAC_LVLPRI1 0 56 #endif 57 58 // <q> Priority Level 2 59 // <i> Indicates whether Priority Level 2 is enabled or not 60 // <id> dmac_lvlen2 61 #ifndef CONF_DMAC_LVLEN2 62 #define CONF_DMAC_LVLEN2 0 63 #endif 64 65 // <o> Level 2 Round-Robin Arbitration 66 // <0=> Static arbitration scheme for channel with priority 2 67 // <1=> Round-robin arbitration scheme for channel with priority 2 68 // <i> Defines Level 2 Arbitration for DMA channels 69 // <id> dmac_rrlvlen2 70 #ifndef CONF_DMAC_RRLVLEN2 71 #define CONF_DMAC_RRLVLEN2 0 72 #endif 73 74 // <o> Level 2 Channel Priority Number <0x00-0xFF> 75 // <id> dmac_lvlpri2 76 #ifndef CONF_DMAC_LVLPRI2 77 #define CONF_DMAC_LVLPRI2 0 78 #endif 79 80 // <q> Priority Level 3 81 // <i> Indicates whether Priority Level 3 is enabled or not 82 // <id> dmac_lvlen3 83 #ifndef CONF_DMAC_LVLEN3 84 #define CONF_DMAC_LVLEN3 0 85 #endif 86 87 // <o> Level 3 Round-Robin Arbitration 88 // <0=> Static arbitration scheme for channel with priority 3 89 // <1=> Round-robin arbitration scheme for channel with priority 3 90 // <i> Defines Level 3 Arbitration for DMA channels 91 // <id> dmac_rrlvlen3 92 #ifndef CONF_DMAC_RRLVLEN3 93 #define CONF_DMAC_RRLVLEN3 0 94 #endif 95 96 // <o> Level 3 Channel Priority Number <0x00-0xFF> 97 // <id> dmac_lvlpri3 98 #ifndef CONF_DMAC_LVLPRI3 99 #define CONF_DMAC_LVLPRI3 0 100 #endif 101 102 // <o> Data Transfer Quality of Service 103 // <0=> Background (no sensitive operation) 104 // <1=> Sensitive bandwidth 105 // <2=> Sensitive latency 106 // <3=> Critical latency 107 // <i> Defines the memory priority access during the data transfer operation 108 // <id> dmac_dqos 109 #ifndef CONF_DMAC_DQOS 110 #define CONF_DMAC_DQOS 0 111 #endif 112 113 // <o> Fetch Quality of Service 114 // <0=> Background (no sensitive operation) 115 // <1=> Sensitive bandwidth 116 // <2=> Sensitive latency 117 // <3=> Critical latency 118 // <i> Defines the memory priority access during the fetch operation 119 // <id> dmac_fqos 120 #ifndef CONF_DMAC_FQOS 121 #define CONF_DMAC_FQOS 0 122 #endif 123 124 // <o> Write-Back Quality of Service 125 // <0=> Background (no sensitive operation) 126 // <1=> Sensitive bandwidth 127 // <2=> Sensitive latency 128 // <3=> Critical latency 129 // <i> Defines the memory priority access during the write-back operation 130 // <id> dmac_wrbqos 131 #ifndef CONF_DMAC_WRBQOS 132 #define CONF_DMAC_WRBQOS 0 133 #endif 134 135 // <q> Debug Run 136 // <i> Indicates whether Debug Run is enabled or not 137 // <id> dmac_dbgrun 138 #ifndef CONF_DMAC_DBGRUN 139 #define CONF_DMAC_DBGRUN 0 140 #endif 141 142 // <e> Channel 0 settings 143 // <id> dmac_channel_0_settings 144 #ifndef CONF_DMAC_CHANNEL_0_SETTINGS 145 #define CONF_DMAC_CHANNEL_0_SETTINGS 0 146 #endif 147 148 // <q> Channel Enable 149 // <i> Indicates whether channel 0 is enabled or not 150 // <id> dmac_enable_0 151 #ifndef CONF_DMAC_ENABLE_0 152 #define CONF_DMAC_ENABLE_0 0 153 #endif 154 155 // <q> Channel Run in Standby 156 // <i> Indicates whether channel 0 is running in standby mode or not 157 // <id> dmac_runstdby_0 158 #ifndef CONF_DMAC_RUNSTDBY_0 159 #define CONF_DMAC_RUNSTDBY_0 0 160 #endif 161 162 // <o> Trigger action 163 // <0=> One trigger required for each block transfer 164 // <2=> One trigger required for each beat transfer 165 // <3=> One trigger required for each transaction 166 // <i> Defines the trigger action used for a transfer 167 // <id> dmac_trigact_0 168 #ifndef CONF_DMAC_TRIGACT_0 169 #define CONF_DMAC_TRIGACT_0 0 170 #endif 171 172 // <o> Trigger source 173 // <0x00=> Only software/event triggers 174 // <0x01=> SERCOM0 RX Trigger 175 // <0x02=> SERCOM0 TX Trigger 176 // <0x03=> SERCOM1 RX Trigger 177 // <0x04=> SERCOM1 TX Trigger 178 // <0x05=> SERCOM2 RX Trigger 179 // <0x06=> SERCOM2 TX Trigger 180 // <0x07=> SERCOM3 RX Trigger 181 // <0x08=> SERCOM3 TX Trigger 182 // <0x09=> SERCOM4 RX Trigger 183 // <0x0A=> SERCOM4 TX Trigger 184 // <0x0B=> TCC0 Overflow Trigger 185 // <0x0C=> TCC0 Match/Compare 0 Trigger 186 // <0x0D=> TCC0 Match/Compare 1 Trigger 187 // <0x0E=> TCC0 Match/Compare 2 Trigger 188 // <0x0F=> TCC0 Match/Compare 3 Trigger 189 // <0x10=> TCC1 Overflow Trigger 190 // <0x11=> TCC1 Match/Compare 0 Trigger 191 // <0x12=> TCC1 Match/Compare 1 Trigger 192 // <0x13=> TCC2 Overflow Trigger 193 // <0x14=> TCC2 Match/Compare 0 Trigger 194 // <0x15=> TCC2 Match/Compare 1 Trigger 195 // <0x16=> TC0 Overflow Trigger 196 // <0x17=> TC0 Match/Compare 0 Trigger 197 // <0x18=> TC0 Match/Compare 1 Trigger 198 // <0x19=> TC1 Overflow Trigger 199 // <0x1A=> TC1 Match/Compare 0 Trigger 200 // <0x1B=> TC1 Match/Compare 1 Trigger 201 // <0x1C=> TC2 Overflow Trigger 202 // <0x1D=> TC2 Match/Compare 0 Trigger 203 // <0x1E=> TC2 Match/Compare 1 Trigger 204 // <0x1F=> TC3 Overflow Trigger 205 // <0x20=> TC3 Match/Compare 0 Trigger 206 // <0x21=> TC3 Match/Compare 1 Trigger 207 // <0x22=> TC4 Overflow Trigger 208 // <0x23=> TC4 Match/Compare 0 Trigger 209 // <0x24=> TC4 Match/Compare 1 Trigger 210 // <0x25=> ADC Result Ready Trigger 211 // <0x26=> DAC0 Empty Trigger 212 // <0x27=> DAC1 Empty Trigger 213 // <0x2C=> AES Write Trigger 214 // <0x2D=> AES Read Trigger 215 // <i> Defines the peripheral trigger which is source of the transfer 216 // <id> dmac_trifsrc_0 217 #ifndef CONF_DMAC_TRIGSRC_0 218 #define CONF_DMAC_TRIGSRC_0 0 219 #endif 220 221 // <o> Channel Arbitration Level 222 // <0=> Channel priority 0 223 // <1=> Channel priority 1 224 // <2=> Channel priority 2 225 // <3=> Channel priority 3 226 // <i> Defines the arbitration level for this channel 227 // <id> dmac_lvl_0 228 #ifndef CONF_DMAC_LVL_0 229 #define CONF_DMAC_LVL_0 0 230 #endif 231 232 // <q> Channel Event Output 233 // <i> Indicates whether channel event generation is enabled or not 234 // <id> dmac_evoe_0 235 #ifndef CONF_DMAC_EVOE_0 236 #define CONF_DMAC_EVOE_0 0 237 #endif 238 239 // <q> Channel Event Input 240 // <i> Indicates whether channel event reception is enabled or not 241 // <id> dmac_evie_0 242 #ifndef CONF_DMAC_EVIE_0 243 #define CONF_DMAC_EVIE_0 0 244 #endif 245 246 // <o> Event Input Action 247 // <0=> No action 248 // <1=> Normal transfer and conditional transfer on strobe trigger 249 // <2=> Conditional transfer trigger 250 // <3=> Conditional block transfer 251 // <4=> Channel suspend operation 252 // <5=> Channel resume operation 253 // <6=> Skip next block suspend action 254 // <i> Defines the event input action 255 // <id> dmac_evact_0 256 #ifndef CONF_DMAC_EVACT_0 257 #define CONF_DMAC_EVACT_0 0 258 #endif 259 260 // <o> Address Increment Step Size 261 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 262 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 263 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 264 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 265 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 266 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 267 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 268 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 269 // <i> Defines the address increment step size, applies to source or destination address 270 // <id> dmac_stepsize_0 271 #ifndef CONF_DMAC_STEPSIZE_0 272 #define CONF_DMAC_STEPSIZE_0 0 273 #endif 274 275 // <o> Step Selection 276 // <0=> Step size settings apply to the destination address 277 // <1=> Step size settings apply to the source address 278 // <i> Defines whether source or destination addresses are using the step size settings 279 // <id> dmac_stepsel_0 280 #ifndef CONF_DMAC_STEPSEL_0 281 #define CONF_DMAC_STEPSEL_0 0 282 #endif 283 284 // <q> Source Address Increment 285 // <i> Indicates whether the source address incrementation is enabled or not 286 // <id> dmac_srcinc_0 287 #ifndef CONF_DMAC_SRCINC_0 288 #define CONF_DMAC_SRCINC_0 0 289 #endif 290 291 // <q> Destination Address Increment 292 // <i> Indicates whether the destination address incrementation is enabled or not 293 // <id> dmac_dstinc_0 294 #ifndef CONF_DMAC_DSTINC_0 295 #define CONF_DMAC_DSTINC_0 0 296 #endif 297 298 // <o> Beat Size 299 // <0=> 8-bit bus transfer 300 // <1=> 16-bit bus transfer 301 // <2=> 32-bit bus transfer 302 // <i> Defines the size of one beat 303 // <id> dmac_beatsize_0 304 #ifndef CONF_DMAC_BEATSIZE_0 305 #define CONF_DMAC_BEATSIZE_0 0 306 #endif 307 308 // <o> Block Action 309 // <0=> Channel will be disabled if it is the last block transfer in the transaction 310 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 311 // <2=> Channel suspend operation is complete 312 // <3=> Both channel suspend operation and block interrupt 313 // <i> Defines the the DMAC should take after a block transfer has completed 314 // <id> dmac_blockact_0 315 #ifndef CONF_DMAC_BLOCKACT_0 316 #define CONF_DMAC_BLOCKACT_0 0 317 #endif 318 319 // <o> Event Output Selection 320 // <0=> Event generation disabled 321 // <1=> Event strobe when block transfer complete 322 // <3=> Event strobe when beat transfer complete 323 // <i> Defines the event output selection 324 // <id> dmac_evosel_0 325 #ifndef CONF_DMAC_EVOSEL_0 326 #define CONF_DMAC_EVOSEL_0 0 327 #endif 328 // </e> 329 330 // <e> Channel 1 settings 331 // <id> dmac_channel_1_settings 332 #ifndef CONF_DMAC_CHANNEL_1_SETTINGS 333 #define CONF_DMAC_CHANNEL_1_SETTINGS 0 334 #endif 335 336 // <q> Channel Enable 337 // <i> Indicates whether channel 1 is enabled or not 338 // <id> dmac_enable_1 339 #ifndef CONF_DMAC_ENABLE_1 340 #define CONF_DMAC_ENABLE_1 0 341 #endif 342 343 // <q> Channel Run in Standby 344 // <i> Indicates whether channel 1 is running in standby mode or not 345 // <id> dmac_runstdby_1 346 #ifndef CONF_DMAC_RUNSTDBY_1 347 #define CONF_DMAC_RUNSTDBY_1 0 348 #endif 349 350 // <o> Trigger action 351 // <0=> One trigger required for each block transfer 352 // <2=> One trigger required for each beat transfer 353 // <3=> One trigger required for each transaction 354 // <i> Defines the trigger action used for a transfer 355 // <id> dmac_trigact_1 356 #ifndef CONF_DMAC_TRIGACT_1 357 #define CONF_DMAC_TRIGACT_1 0 358 #endif 359 360 // <o> Trigger source 361 // <0x00=> Only software/event triggers 362 // <0x01=> SERCOM0 RX Trigger 363 // <0x02=> SERCOM0 TX Trigger 364 // <0x03=> SERCOM1 RX Trigger 365 // <0x04=> SERCOM1 TX Trigger 366 // <0x05=> SERCOM2 RX Trigger 367 // <0x06=> SERCOM2 TX Trigger 368 // <0x07=> SERCOM3 RX Trigger 369 // <0x08=> SERCOM3 TX Trigger 370 // <0x09=> SERCOM4 RX Trigger 371 // <0x0A=> SERCOM4 TX Trigger 372 // <0x0B=> TCC0 Overflow Trigger 373 // <0x0C=> TCC0 Match/Compare 0 Trigger 374 // <0x0D=> TCC0 Match/Compare 1 Trigger 375 // <0x0E=> TCC0 Match/Compare 2 Trigger 376 // <0x0F=> TCC0 Match/Compare 3 Trigger 377 // <0x10=> TCC1 Overflow Trigger 378 // <0x11=> TCC1 Match/Compare 0 Trigger 379 // <0x12=> TCC1 Match/Compare 1 Trigger 380 // <0x13=> TCC2 Overflow Trigger 381 // <0x14=> TCC2 Match/Compare 0 Trigger 382 // <0x15=> TCC2 Match/Compare 1 Trigger 383 // <0x16=> TC0 Overflow Trigger 384 // <0x17=> TC0 Match/Compare 0 Trigger 385 // <0x18=> TC0 Match/Compare 1 Trigger 386 // <0x19=> TC1 Overflow Trigger 387 // <0x1A=> TC1 Match/Compare 0 Trigger 388 // <0x1B=> TC1 Match/Compare 1 Trigger 389 // <0x1C=> TC2 Overflow Trigger 390 // <0x1D=> TC2 Match/Compare 0 Trigger 391 // <0x1E=> TC2 Match/Compare 1 Trigger 392 // <0x1F=> TC3 Overflow Trigger 393 // <0x20=> TC3 Match/Compare 0 Trigger 394 // <0x21=> TC3 Match/Compare 1 Trigger 395 // <0x22=> TC4 Overflow Trigger 396 // <0x23=> TC4 Match/Compare 0 Trigger 397 // <0x24=> TC4 Match/Compare 1 Trigger 398 // <0x25=> ADC Result Ready Trigger 399 // <0x26=> DAC0 Empty Trigger 400 // <0x27=> DAC1 Empty Trigger 401 // <0x2C=> AES Write Trigger 402 // <0x2D=> AES Read Trigger 403 // <i> Defines the peripheral trigger which is source of the transfer 404 // <id> dmac_trifsrc_1 405 #ifndef CONF_DMAC_TRIGSRC_1 406 #define CONF_DMAC_TRIGSRC_1 0 407 #endif 408 409 // <o> Channel Arbitration Level 410 // <0=> Channel priority 0 411 // <1=> Channel priority 1 412 // <2=> Channel priority 2 413 // <3=> Channel priority 3 414 // <i> Defines the arbitration level for this channel 415 // <id> dmac_lvl_1 416 #ifndef CONF_DMAC_LVL_1 417 #define CONF_DMAC_LVL_1 0 418 #endif 419 420 // <q> Channel Event Output 421 // <i> Indicates whether channel event generation is enabled or not 422 // <id> dmac_evoe_1 423 #ifndef CONF_DMAC_EVOE_1 424 #define CONF_DMAC_EVOE_1 0 425 #endif 426 427 // <q> Channel Event Input 428 // <i> Indicates whether channel event reception is enabled or not 429 // <id> dmac_evie_1 430 #ifndef CONF_DMAC_EVIE_1 431 #define CONF_DMAC_EVIE_1 0 432 #endif 433 434 // <o> Event Input Action 435 // <0=> No action 436 // <1=> Normal transfer and conditional transfer on strobe trigger 437 // <2=> Conditional transfer trigger 438 // <3=> Conditional block transfer 439 // <4=> Channel suspend operation 440 // <5=> Channel resume operation 441 // <6=> Skip next block suspend action 442 // <i> Defines the event input action 443 // <id> dmac_evact_1 444 #ifndef CONF_DMAC_EVACT_1 445 #define CONF_DMAC_EVACT_1 0 446 #endif 447 448 // <o> Address Increment Step Size 449 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 450 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 451 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 452 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 453 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 454 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 455 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 456 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 457 // <i> Defines the address increment step size, applies to source or destination address 458 // <id> dmac_stepsize_1 459 #ifndef CONF_DMAC_STEPSIZE_1 460 #define CONF_DMAC_STEPSIZE_1 0 461 #endif 462 463 // <o> Step Selection 464 // <0=> Step size settings apply to the destination address 465 // <1=> Step size settings apply to the source address 466 // <i> Defines whether source or destination addresses are using the step size settings 467 // <id> dmac_stepsel_1 468 #ifndef CONF_DMAC_STEPSEL_1 469 #define CONF_DMAC_STEPSEL_1 0 470 #endif 471 472 // <q> Source Address Increment 473 // <i> Indicates whether the source address incrementation is enabled or not 474 // <id> dmac_srcinc_1 475 #ifndef CONF_DMAC_SRCINC_1 476 #define CONF_DMAC_SRCINC_1 0 477 #endif 478 479 // <q> Destination Address Increment 480 // <i> Indicates whether the destination address incrementation is enabled or not 481 // <id> dmac_dstinc_1 482 #ifndef CONF_DMAC_DSTINC_1 483 #define CONF_DMAC_DSTINC_1 0 484 #endif 485 486 // <o> Beat Size 487 // <0=> 8-bit bus transfer 488 // <1=> 16-bit bus transfer 489 // <2=> 32-bit bus transfer 490 // <i> Defines the size of one beat 491 // <id> dmac_beatsize_1 492 #ifndef CONF_DMAC_BEATSIZE_1 493 #define CONF_DMAC_BEATSIZE_1 0 494 #endif 495 496 // <o> Block Action 497 // <0=> Channel will be disabled if it is the last block transfer in the transaction 498 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 499 // <2=> Channel suspend operation is complete 500 // <3=> Both channel suspend operation and block interrupt 501 // <i> Defines the the DMAC should take after a block transfer has completed 502 // <id> dmac_blockact_1 503 #ifndef CONF_DMAC_BLOCKACT_1 504 #define CONF_DMAC_BLOCKACT_1 0 505 #endif 506 507 // <o> Event Output Selection 508 // <0=> Event generation disabled 509 // <1=> Event strobe when block transfer complete 510 // <3=> Event strobe when beat transfer complete 511 // <i> Defines the event output selection 512 // <id> dmac_evosel_1 513 #ifndef CONF_DMAC_EVOSEL_1 514 #define CONF_DMAC_EVOSEL_1 0 515 #endif 516 // </e> 517 518 // <e> Channel 2 settings 519 // <id> dmac_channel_2_settings 520 #ifndef CONF_DMAC_CHANNEL_2_SETTINGS 521 #define CONF_DMAC_CHANNEL_2_SETTINGS 0 522 #endif 523 524 // <q> Channel Enable 525 // <i> Indicates whether channel 2 is enabled or not 526 // <id> dmac_enable_2 527 #ifndef CONF_DMAC_ENABLE_2 528 #define CONF_DMAC_ENABLE_2 0 529 #endif 530 531 // <q> Channel Run in Standby 532 // <i> Indicates whether channel 2 is running in standby mode or not 533 // <id> dmac_runstdby_2 534 #ifndef CONF_DMAC_RUNSTDBY_2 535 #define CONF_DMAC_RUNSTDBY_2 0 536 #endif 537 538 // <o> Trigger action 539 // <0=> One trigger required for each block transfer 540 // <2=> One trigger required for each beat transfer 541 // <3=> One trigger required for each transaction 542 // <i> Defines the trigger action used for a transfer 543 // <id> dmac_trigact_2 544 #ifndef CONF_DMAC_TRIGACT_2 545 #define CONF_DMAC_TRIGACT_2 0 546 #endif 547 548 // <o> Trigger source 549 // <0x00=> Only software/event triggers 550 // <0x01=> SERCOM0 RX Trigger 551 // <0x02=> SERCOM0 TX Trigger 552 // <0x03=> SERCOM1 RX Trigger 553 // <0x04=> SERCOM1 TX Trigger 554 // <0x05=> SERCOM2 RX Trigger 555 // <0x06=> SERCOM2 TX Trigger 556 // <0x07=> SERCOM3 RX Trigger 557 // <0x08=> SERCOM3 TX Trigger 558 // <0x09=> SERCOM4 RX Trigger 559 // <0x0A=> SERCOM4 TX Trigger 560 // <0x0B=> TCC0 Overflow Trigger 561 // <0x0C=> TCC0 Match/Compare 0 Trigger 562 // <0x0D=> TCC0 Match/Compare 1 Trigger 563 // <0x0E=> TCC0 Match/Compare 2 Trigger 564 // <0x0F=> TCC0 Match/Compare 3 Trigger 565 // <0x10=> TCC1 Overflow Trigger 566 // <0x11=> TCC1 Match/Compare 0 Trigger 567 // <0x12=> TCC1 Match/Compare 1 Trigger 568 // <0x13=> TCC2 Overflow Trigger 569 // <0x14=> TCC2 Match/Compare 0 Trigger 570 // <0x15=> TCC2 Match/Compare 1 Trigger 571 // <0x16=> TC0 Overflow Trigger 572 // <0x17=> TC0 Match/Compare 0 Trigger 573 // <0x18=> TC0 Match/Compare 1 Trigger 574 // <0x19=> TC1 Overflow Trigger 575 // <0x1A=> TC1 Match/Compare 0 Trigger 576 // <0x1B=> TC1 Match/Compare 1 Trigger 577 // <0x1C=> TC2 Overflow Trigger 578 // <0x1D=> TC2 Match/Compare 0 Trigger 579 // <0x1E=> TC2 Match/Compare 1 Trigger 580 // <0x1F=> TC3 Overflow Trigger 581 // <0x20=> TC3 Match/Compare 0 Trigger 582 // <0x21=> TC3 Match/Compare 1 Trigger 583 // <0x22=> TC4 Overflow Trigger 584 // <0x23=> TC4 Match/Compare 0 Trigger 585 // <0x24=> TC4 Match/Compare 1 Trigger 586 // <0x25=> ADC Result Ready Trigger 587 // <0x26=> DAC0 Empty Trigger 588 // <0x27=> DAC1 Empty Trigger 589 // <0x2C=> AES Write Trigger 590 // <0x2D=> AES Read Trigger 591 // <i> Defines the peripheral trigger which is source of the transfer 592 // <id> dmac_trifsrc_2 593 #ifndef CONF_DMAC_TRIGSRC_2 594 #define CONF_DMAC_TRIGSRC_2 0 595 #endif 596 597 // <o> Channel Arbitration Level 598 // <0=> Channel priority 0 599 // <1=> Channel priority 1 600 // <2=> Channel priority 2 601 // <3=> Channel priority 3 602 // <i> Defines the arbitration level for this channel 603 // <id> dmac_lvl_2 604 #ifndef CONF_DMAC_LVL_2 605 #define CONF_DMAC_LVL_2 0 606 #endif 607 608 // <q> Channel Event Output 609 // <i> Indicates whether channel event generation is enabled or not 610 // <id> dmac_evoe_2 611 #ifndef CONF_DMAC_EVOE_2 612 #define CONF_DMAC_EVOE_2 0 613 #endif 614 615 // <q> Channel Event Input 616 // <i> Indicates whether channel event reception is enabled or not 617 // <id> dmac_evie_2 618 #ifndef CONF_DMAC_EVIE_2 619 #define CONF_DMAC_EVIE_2 0 620 #endif 621 622 // <o> Event Input Action 623 // <0=> No action 624 // <1=> Normal transfer and conditional transfer on strobe trigger 625 // <2=> Conditional transfer trigger 626 // <3=> Conditional block transfer 627 // <4=> Channel suspend operation 628 // <5=> Channel resume operation 629 // <6=> Skip next block suspend action 630 // <i> Defines the event input action 631 // <id> dmac_evact_2 632 #ifndef CONF_DMAC_EVACT_2 633 #define CONF_DMAC_EVACT_2 0 634 #endif 635 636 // <o> Address Increment Step Size 637 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 638 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 639 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 640 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 641 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 642 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 643 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 644 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 645 // <i> Defines the address increment step size, applies to source or destination address 646 // <id> dmac_stepsize_2 647 #ifndef CONF_DMAC_STEPSIZE_2 648 #define CONF_DMAC_STEPSIZE_2 0 649 #endif 650 651 // <o> Step Selection 652 // <0=> Step size settings apply to the destination address 653 // <1=> Step size settings apply to the source address 654 // <i> Defines whether source or destination addresses are using the step size settings 655 // <id> dmac_stepsel_2 656 #ifndef CONF_DMAC_STEPSEL_2 657 #define CONF_DMAC_STEPSEL_2 0 658 #endif 659 660 // <q> Source Address Increment 661 // <i> Indicates whether the source address incrementation is enabled or not 662 // <id> dmac_srcinc_2 663 #ifndef CONF_DMAC_SRCINC_2 664 #define CONF_DMAC_SRCINC_2 0 665 #endif 666 667 // <q> Destination Address Increment 668 // <i> Indicates whether the destination address incrementation is enabled or not 669 // <id> dmac_dstinc_2 670 #ifndef CONF_DMAC_DSTINC_2 671 #define CONF_DMAC_DSTINC_2 0 672 #endif 673 674 // <o> Beat Size 675 // <0=> 8-bit bus transfer 676 // <1=> 16-bit bus transfer 677 // <2=> 32-bit bus transfer 678 // <i> Defines the size of one beat 679 // <id> dmac_beatsize_2 680 #ifndef CONF_DMAC_BEATSIZE_2 681 #define CONF_DMAC_BEATSIZE_2 0 682 #endif 683 684 // <o> Block Action 685 // <0=> Channel will be disabled if it is the last block transfer in the transaction 686 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 687 // <2=> Channel suspend operation is complete 688 // <3=> Both channel suspend operation and block interrupt 689 // <i> Defines the the DMAC should take after a block transfer has completed 690 // <id> dmac_blockact_2 691 #ifndef CONF_DMAC_BLOCKACT_2 692 #define CONF_DMAC_BLOCKACT_2 0 693 #endif 694 695 // <o> Event Output Selection 696 // <0=> Event generation disabled 697 // <1=> Event strobe when block transfer complete 698 // <3=> Event strobe when beat transfer complete 699 // <i> Defines the event output selection 700 // <id> dmac_evosel_2 701 #ifndef CONF_DMAC_EVOSEL_2 702 #define CONF_DMAC_EVOSEL_2 0 703 #endif 704 // </e> 705 706 // <e> Channel 3 settings 707 // <id> dmac_channel_3_settings 708 #ifndef CONF_DMAC_CHANNEL_3_SETTINGS 709 #define CONF_DMAC_CHANNEL_3_SETTINGS 0 710 #endif 711 712 // <q> Channel Enable 713 // <i> Indicates whether channel 3 is enabled or not 714 // <id> dmac_enable_3 715 #ifndef CONF_DMAC_ENABLE_3 716 #define CONF_DMAC_ENABLE_3 0 717 #endif 718 719 // <q> Channel Run in Standby 720 // <i> Indicates whether channel 3 is running in standby mode or not 721 // <id> dmac_runstdby_3 722 #ifndef CONF_DMAC_RUNSTDBY_3 723 #define CONF_DMAC_RUNSTDBY_3 0 724 #endif 725 726 // <o> Trigger action 727 // <0=> One trigger required for each block transfer 728 // <2=> One trigger required for each beat transfer 729 // <3=> One trigger required for each transaction 730 // <i> Defines the trigger action used for a transfer 731 // <id> dmac_trigact_3 732 #ifndef CONF_DMAC_TRIGACT_3 733 #define CONF_DMAC_TRIGACT_3 0 734 #endif 735 736 // <o> Trigger source 737 // <0x00=> Only software/event triggers 738 // <0x01=> SERCOM0 RX Trigger 739 // <0x02=> SERCOM0 TX Trigger 740 // <0x03=> SERCOM1 RX Trigger 741 // <0x04=> SERCOM1 TX Trigger 742 // <0x05=> SERCOM2 RX Trigger 743 // <0x06=> SERCOM2 TX Trigger 744 // <0x07=> SERCOM3 RX Trigger 745 // <0x08=> SERCOM3 TX Trigger 746 // <0x09=> SERCOM4 RX Trigger 747 // <0x0A=> SERCOM4 TX Trigger 748 // <0x0B=> TCC0 Overflow Trigger 749 // <0x0C=> TCC0 Match/Compare 0 Trigger 750 // <0x0D=> TCC0 Match/Compare 1 Trigger 751 // <0x0E=> TCC0 Match/Compare 2 Trigger 752 // <0x0F=> TCC0 Match/Compare 3 Trigger 753 // <0x10=> TCC1 Overflow Trigger 754 // <0x11=> TCC1 Match/Compare 0 Trigger 755 // <0x12=> TCC1 Match/Compare 1 Trigger 756 // <0x13=> TCC2 Overflow Trigger 757 // <0x14=> TCC2 Match/Compare 0 Trigger 758 // <0x15=> TCC2 Match/Compare 1 Trigger 759 // <0x16=> TC0 Overflow Trigger 760 // <0x17=> TC0 Match/Compare 0 Trigger 761 // <0x18=> TC0 Match/Compare 1 Trigger 762 // <0x19=> TC1 Overflow Trigger 763 // <0x1A=> TC1 Match/Compare 0 Trigger 764 // <0x1B=> TC1 Match/Compare 1 Trigger 765 // <0x1C=> TC2 Overflow Trigger 766 // <0x1D=> TC2 Match/Compare 0 Trigger 767 // <0x1E=> TC2 Match/Compare 1 Trigger 768 // <0x1F=> TC3 Overflow Trigger 769 // <0x20=> TC3 Match/Compare 0 Trigger 770 // <0x21=> TC3 Match/Compare 1 Trigger 771 // <0x22=> TC4 Overflow Trigger 772 // <0x23=> TC4 Match/Compare 0 Trigger 773 // <0x24=> TC4 Match/Compare 1 Trigger 774 // <0x25=> ADC Result Ready Trigger 775 // <0x26=> DAC0 Empty Trigger 776 // <0x27=> DAC1 Empty Trigger 777 // <0x2C=> AES Write Trigger 778 // <0x2D=> AES Read Trigger 779 // <i> Defines the peripheral trigger which is source of the transfer 780 // <id> dmac_trifsrc_3 781 #ifndef CONF_DMAC_TRIGSRC_3 782 #define CONF_DMAC_TRIGSRC_3 0 783 #endif 784 785 // <o> Channel Arbitration Level 786 // <0=> Channel priority 0 787 // <1=> Channel priority 1 788 // <2=> Channel priority 2 789 // <3=> Channel priority 3 790 // <i> Defines the arbitration level for this channel 791 // <id> dmac_lvl_3 792 #ifndef CONF_DMAC_LVL_3 793 #define CONF_DMAC_LVL_3 0 794 #endif 795 796 // <q> Channel Event Output 797 // <i> Indicates whether channel event generation is enabled or not 798 // <id> dmac_evoe_3 799 #ifndef CONF_DMAC_EVOE_3 800 #define CONF_DMAC_EVOE_3 0 801 #endif 802 803 // <q> Channel Event Input 804 // <i> Indicates whether channel event reception is enabled or not 805 // <id> dmac_evie_3 806 #ifndef CONF_DMAC_EVIE_3 807 #define CONF_DMAC_EVIE_3 0 808 #endif 809 810 // <o> Event Input Action 811 // <0=> No action 812 // <1=> Normal transfer and conditional transfer on strobe trigger 813 // <2=> Conditional transfer trigger 814 // <3=> Conditional block transfer 815 // <4=> Channel suspend operation 816 // <5=> Channel resume operation 817 // <6=> Skip next block suspend action 818 // <i> Defines the event input action 819 // <id> dmac_evact_3 820 #ifndef CONF_DMAC_EVACT_3 821 #define CONF_DMAC_EVACT_3 0 822 #endif 823 824 // <o> Address Increment Step Size 825 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 826 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 827 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 828 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 829 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 830 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 831 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 832 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 833 // <i> Defines the address increment step size, applies to source or destination address 834 // <id> dmac_stepsize_3 835 #ifndef CONF_DMAC_STEPSIZE_3 836 #define CONF_DMAC_STEPSIZE_3 0 837 #endif 838 839 // <o> Step Selection 840 // <0=> Step size settings apply to the destination address 841 // <1=> Step size settings apply to the source address 842 // <i> Defines whether source or destination addresses are using the step size settings 843 // <id> dmac_stepsel_3 844 #ifndef CONF_DMAC_STEPSEL_3 845 #define CONF_DMAC_STEPSEL_3 0 846 #endif 847 848 // <q> Source Address Increment 849 // <i> Indicates whether the source address incrementation is enabled or not 850 // <id> dmac_srcinc_3 851 #ifndef CONF_DMAC_SRCINC_3 852 #define CONF_DMAC_SRCINC_3 0 853 #endif 854 855 // <q> Destination Address Increment 856 // <i> Indicates whether the destination address incrementation is enabled or not 857 // <id> dmac_dstinc_3 858 #ifndef CONF_DMAC_DSTINC_3 859 #define CONF_DMAC_DSTINC_3 0 860 #endif 861 862 // <o> Beat Size 863 // <0=> 8-bit bus transfer 864 // <1=> 16-bit bus transfer 865 // <2=> 32-bit bus transfer 866 // <i> Defines the size of one beat 867 // <id> dmac_beatsize_3 868 #ifndef CONF_DMAC_BEATSIZE_3 869 #define CONF_DMAC_BEATSIZE_3 0 870 #endif 871 872 // <o> Block Action 873 // <0=> Channel will be disabled if it is the last block transfer in the transaction 874 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 875 // <2=> Channel suspend operation is complete 876 // <3=> Both channel suspend operation and block interrupt 877 // <i> Defines the the DMAC should take after a block transfer has completed 878 // <id> dmac_blockact_3 879 #ifndef CONF_DMAC_BLOCKACT_3 880 #define CONF_DMAC_BLOCKACT_3 0 881 #endif 882 883 // <o> Event Output Selection 884 // <0=> Event generation disabled 885 // <1=> Event strobe when block transfer complete 886 // <3=> Event strobe when beat transfer complete 887 // <i> Defines the event output selection 888 // <id> dmac_evosel_3 889 #ifndef CONF_DMAC_EVOSEL_3 890 #define CONF_DMAC_EVOSEL_3 0 891 #endif 892 // </e> 893 894 // <e> Channel 4 settings 895 // <id> dmac_channel_4_settings 896 #ifndef CONF_DMAC_CHANNEL_4_SETTINGS 897 #define CONF_DMAC_CHANNEL_4_SETTINGS 0 898 #endif 899 900 // <q> Channel Enable 901 // <i> Indicates whether channel 4 is enabled or not 902 // <id> dmac_enable_4 903 #ifndef CONF_DMAC_ENABLE_4 904 #define CONF_DMAC_ENABLE_4 0 905 #endif 906 907 // <q> Channel Run in Standby 908 // <i> Indicates whether channel 4 is running in standby mode or not 909 // <id> dmac_runstdby_4 910 #ifndef CONF_DMAC_RUNSTDBY_4 911 #define CONF_DMAC_RUNSTDBY_4 0 912 #endif 913 914 // <o> Trigger action 915 // <0=> One trigger required for each block transfer 916 // <2=> One trigger required for each beat transfer 917 // <3=> One trigger required for each transaction 918 // <i> Defines the trigger action used for a transfer 919 // <id> dmac_trigact_4 920 #ifndef CONF_DMAC_TRIGACT_4 921 #define CONF_DMAC_TRIGACT_4 0 922 #endif 923 924 // <o> Trigger source 925 // <0x00=> Only software/event triggers 926 // <0x01=> SERCOM0 RX Trigger 927 // <0x02=> SERCOM0 TX Trigger 928 // <0x03=> SERCOM1 RX Trigger 929 // <0x04=> SERCOM1 TX Trigger 930 // <0x05=> SERCOM2 RX Trigger 931 // <0x06=> SERCOM2 TX Trigger 932 // <0x07=> SERCOM3 RX Trigger 933 // <0x08=> SERCOM3 TX Trigger 934 // <0x09=> SERCOM4 RX Trigger 935 // <0x0A=> SERCOM4 TX Trigger 936 // <0x0B=> TCC0 Overflow Trigger 937 // <0x0C=> TCC0 Match/Compare 0 Trigger 938 // <0x0D=> TCC0 Match/Compare 1 Trigger 939 // <0x0E=> TCC0 Match/Compare 2 Trigger 940 // <0x0F=> TCC0 Match/Compare 3 Trigger 941 // <0x10=> TCC1 Overflow Trigger 942 // <0x11=> TCC1 Match/Compare 0 Trigger 943 // <0x12=> TCC1 Match/Compare 1 Trigger 944 // <0x13=> TCC2 Overflow Trigger 945 // <0x14=> TCC2 Match/Compare 0 Trigger 946 // <0x15=> TCC2 Match/Compare 1 Trigger 947 // <0x16=> TC0 Overflow Trigger 948 // <0x17=> TC0 Match/Compare 0 Trigger 949 // <0x18=> TC0 Match/Compare 1 Trigger 950 // <0x19=> TC1 Overflow Trigger 951 // <0x1A=> TC1 Match/Compare 0 Trigger 952 // <0x1B=> TC1 Match/Compare 1 Trigger 953 // <0x1C=> TC2 Overflow Trigger 954 // <0x1D=> TC2 Match/Compare 0 Trigger 955 // <0x1E=> TC2 Match/Compare 1 Trigger 956 // <0x1F=> TC3 Overflow Trigger 957 // <0x20=> TC3 Match/Compare 0 Trigger 958 // <0x21=> TC3 Match/Compare 1 Trigger 959 // <0x22=> TC4 Overflow Trigger 960 // <0x23=> TC4 Match/Compare 0 Trigger 961 // <0x24=> TC4 Match/Compare 1 Trigger 962 // <0x25=> ADC Result Ready Trigger 963 // <0x26=> DAC0 Empty Trigger 964 // <0x27=> DAC1 Empty Trigger 965 // <0x2C=> AES Write Trigger 966 // <0x2D=> AES Read Trigger 967 // <i> Defines the peripheral trigger which is source of the transfer 968 // <id> dmac_trifsrc_4 969 #ifndef CONF_DMAC_TRIGSRC_4 970 #define CONF_DMAC_TRIGSRC_4 0 971 #endif 972 973 // <o> Channel Arbitration Level 974 // <0=> Channel priority 0 975 // <1=> Channel priority 1 976 // <2=> Channel priority 2 977 // <3=> Channel priority 3 978 // <i> Defines the arbitration level for this channel 979 // <id> dmac_lvl_4 980 #ifndef CONF_DMAC_LVL_4 981 #define CONF_DMAC_LVL_4 0 982 #endif 983 984 // <q> Channel Event Output 985 // <i> Indicates whether channel event generation is enabled or not 986 // <id> dmac_evoe_4 987 #ifndef CONF_DMAC_EVOE_4 988 #define CONF_DMAC_EVOE_4 0 989 #endif 990 991 // <q> Channel Event Input 992 // <i> Indicates whether channel event reception is enabled or not 993 // <id> dmac_evie_4 994 #ifndef CONF_DMAC_EVIE_4 995 #define CONF_DMAC_EVIE_4 0 996 #endif 997 998 // <o> Event Input Action 999 // <0=> No action 1000 // <1=> Normal transfer and conditional transfer on strobe trigger 1001 // <2=> Conditional transfer trigger 1002 // <3=> Conditional block transfer 1003 // <4=> Channel suspend operation 1004 // <5=> Channel resume operation 1005 // <6=> Skip next block suspend action 1006 // <i> Defines the event input action 1007 // <id> dmac_evact_4 1008 #ifndef CONF_DMAC_EVACT_4 1009 #define CONF_DMAC_EVACT_4 0 1010 #endif 1011 1012 // <o> Address Increment Step Size 1013 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1014 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1015 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1016 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1017 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1018 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1019 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1020 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1021 // <i> Defines the address increment step size, applies to source or destination address 1022 // <id> dmac_stepsize_4 1023 #ifndef CONF_DMAC_STEPSIZE_4 1024 #define CONF_DMAC_STEPSIZE_4 0 1025 #endif 1026 1027 // <o> Step Selection 1028 // <0=> Step size settings apply to the destination address 1029 // <1=> Step size settings apply to the source address 1030 // <i> Defines whether source or destination addresses are using the step size settings 1031 // <id> dmac_stepsel_4 1032 #ifndef CONF_DMAC_STEPSEL_4 1033 #define CONF_DMAC_STEPSEL_4 0 1034 #endif 1035 1036 // <q> Source Address Increment 1037 // <i> Indicates whether the source address incrementation is enabled or not 1038 // <id> dmac_srcinc_4 1039 #ifndef CONF_DMAC_SRCINC_4 1040 #define CONF_DMAC_SRCINC_4 0 1041 #endif 1042 1043 // <q> Destination Address Increment 1044 // <i> Indicates whether the destination address incrementation is enabled or not 1045 // <id> dmac_dstinc_4 1046 #ifndef CONF_DMAC_DSTINC_4 1047 #define CONF_DMAC_DSTINC_4 0 1048 #endif 1049 1050 // <o> Beat Size 1051 // <0=> 8-bit bus transfer 1052 // <1=> 16-bit bus transfer 1053 // <2=> 32-bit bus transfer 1054 // <i> Defines the size of one beat 1055 // <id> dmac_beatsize_4 1056 #ifndef CONF_DMAC_BEATSIZE_4 1057 #define CONF_DMAC_BEATSIZE_4 0 1058 #endif 1059 1060 // <o> Block Action 1061 // <0=> Channel will be disabled if it is the last block transfer in the transaction 1062 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 1063 // <2=> Channel suspend operation is complete 1064 // <3=> Both channel suspend operation and block interrupt 1065 // <i> Defines the the DMAC should take after a block transfer has completed 1066 // <id> dmac_blockact_4 1067 #ifndef CONF_DMAC_BLOCKACT_4 1068 #define CONF_DMAC_BLOCKACT_4 0 1069 #endif 1070 1071 // <o> Event Output Selection 1072 // <0=> Event generation disabled 1073 // <1=> Event strobe when block transfer complete 1074 // <3=> Event strobe when beat transfer complete 1075 // <i> Defines the event output selection 1076 // <id> dmac_evosel_4 1077 #ifndef CONF_DMAC_EVOSEL_4 1078 #define CONF_DMAC_EVOSEL_4 0 1079 #endif 1080 // </e> 1081 1082 // <e> Channel 5 settings 1083 // <id> dmac_channel_5_settings 1084 #ifndef CONF_DMAC_CHANNEL_5_SETTINGS 1085 #define CONF_DMAC_CHANNEL_5_SETTINGS 0 1086 #endif 1087 1088 // <q> Channel Enable 1089 // <i> Indicates whether channel 5 is enabled or not 1090 // <id> dmac_enable_5 1091 #ifndef CONF_DMAC_ENABLE_5 1092 #define CONF_DMAC_ENABLE_5 0 1093 #endif 1094 1095 // <q> Channel Run in Standby 1096 // <i> Indicates whether channel 5 is running in standby mode or not 1097 // <id> dmac_runstdby_5 1098 #ifndef CONF_DMAC_RUNSTDBY_5 1099 #define CONF_DMAC_RUNSTDBY_5 0 1100 #endif 1101 1102 // <o> Trigger action 1103 // <0=> One trigger required for each block transfer 1104 // <2=> One trigger required for each beat transfer 1105 // <3=> One trigger required for each transaction 1106 // <i> Defines the trigger action used for a transfer 1107 // <id> dmac_trigact_5 1108 #ifndef CONF_DMAC_TRIGACT_5 1109 #define CONF_DMAC_TRIGACT_5 0 1110 #endif 1111 1112 // <o> Trigger source 1113 // <0x00=> Only software/event triggers 1114 // <0x01=> SERCOM0 RX Trigger 1115 // <0x02=> SERCOM0 TX Trigger 1116 // <0x03=> SERCOM1 RX Trigger 1117 // <0x04=> SERCOM1 TX Trigger 1118 // <0x05=> SERCOM2 RX Trigger 1119 // <0x06=> SERCOM2 TX Trigger 1120 // <0x07=> SERCOM3 RX Trigger 1121 // <0x08=> SERCOM3 TX Trigger 1122 // <0x09=> SERCOM4 RX Trigger 1123 // <0x0A=> SERCOM4 TX Trigger 1124 // <0x0B=> TCC0 Overflow Trigger 1125 // <0x0C=> TCC0 Match/Compare 0 Trigger 1126 // <0x0D=> TCC0 Match/Compare 1 Trigger 1127 // <0x0E=> TCC0 Match/Compare 2 Trigger 1128 // <0x0F=> TCC0 Match/Compare 3 Trigger 1129 // <0x10=> TCC1 Overflow Trigger 1130 // <0x11=> TCC1 Match/Compare 0 Trigger 1131 // <0x12=> TCC1 Match/Compare 1 Trigger 1132 // <0x13=> TCC2 Overflow Trigger 1133 // <0x14=> TCC2 Match/Compare 0 Trigger 1134 // <0x15=> TCC2 Match/Compare 1 Trigger 1135 // <0x16=> TC0 Overflow Trigger 1136 // <0x17=> TC0 Match/Compare 0 Trigger 1137 // <0x18=> TC0 Match/Compare 1 Trigger 1138 // <0x19=> TC1 Overflow Trigger 1139 // <0x1A=> TC1 Match/Compare 0 Trigger 1140 // <0x1B=> TC1 Match/Compare 1 Trigger 1141 // <0x1C=> TC2 Overflow Trigger 1142 // <0x1D=> TC2 Match/Compare 0 Trigger 1143 // <0x1E=> TC2 Match/Compare 1 Trigger 1144 // <0x1F=> TC3 Overflow Trigger 1145 // <0x20=> TC3 Match/Compare 0 Trigger 1146 // <0x21=> TC3 Match/Compare 1 Trigger 1147 // <0x22=> TC4 Overflow Trigger 1148 // <0x23=> TC4 Match/Compare 0 Trigger 1149 // <0x24=> TC4 Match/Compare 1 Trigger 1150 // <0x25=> ADC Result Ready Trigger 1151 // <0x26=> DAC0 Empty Trigger 1152 // <0x27=> DAC1 Empty Trigger 1153 // <0x2C=> AES Write Trigger 1154 // <0x2D=> AES Read Trigger 1155 // <i> Defines the peripheral trigger which is source of the transfer 1156 // <id> dmac_trifsrc_5 1157 #ifndef CONF_DMAC_TRIGSRC_5 1158 #define CONF_DMAC_TRIGSRC_5 0 1159 #endif 1160 1161 // <o> Channel Arbitration Level 1162 // <0=> Channel priority 0 1163 // <1=> Channel priority 1 1164 // <2=> Channel priority 2 1165 // <3=> Channel priority 3 1166 // <i> Defines the arbitration level for this channel 1167 // <id> dmac_lvl_5 1168 #ifndef CONF_DMAC_LVL_5 1169 #define CONF_DMAC_LVL_5 0 1170 #endif 1171 1172 // <q> Channel Event Output 1173 // <i> Indicates whether channel event generation is enabled or not 1174 // <id> dmac_evoe_5 1175 #ifndef CONF_DMAC_EVOE_5 1176 #define CONF_DMAC_EVOE_5 0 1177 #endif 1178 1179 // <q> Channel Event Input 1180 // <i> Indicates whether channel event reception is enabled or not 1181 // <id> dmac_evie_5 1182 #ifndef CONF_DMAC_EVIE_5 1183 #define CONF_DMAC_EVIE_5 0 1184 #endif 1185 1186 // <o> Event Input Action 1187 // <0=> No action 1188 // <1=> Normal transfer and conditional transfer on strobe trigger 1189 // <2=> Conditional transfer trigger 1190 // <3=> Conditional block transfer 1191 // <4=> Channel suspend operation 1192 // <5=> Channel resume operation 1193 // <6=> Skip next block suspend action 1194 // <i> Defines the event input action 1195 // <id> dmac_evact_5 1196 #ifndef CONF_DMAC_EVACT_5 1197 #define CONF_DMAC_EVACT_5 0 1198 #endif 1199 1200 // <o> Address Increment Step Size 1201 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1202 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1203 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1204 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1205 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1206 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1207 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1208 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1209 // <i> Defines the address increment step size, applies to source or destination address 1210 // <id> dmac_stepsize_5 1211 #ifndef CONF_DMAC_STEPSIZE_5 1212 #define CONF_DMAC_STEPSIZE_5 0 1213 #endif 1214 1215 // <o> Step Selection 1216 // <0=> Step size settings apply to the destination address 1217 // <1=> Step size settings apply to the source address 1218 // <i> Defines whether source or destination addresses are using the step size settings 1219 // <id> dmac_stepsel_5 1220 #ifndef CONF_DMAC_STEPSEL_5 1221 #define CONF_DMAC_STEPSEL_5 0 1222 #endif 1223 1224 // <q> Source Address Increment 1225 // <i> Indicates whether the source address incrementation is enabled or not 1226 // <id> dmac_srcinc_5 1227 #ifndef CONF_DMAC_SRCINC_5 1228 #define CONF_DMAC_SRCINC_5 0 1229 #endif 1230 1231 // <q> Destination Address Increment 1232 // <i> Indicates whether the destination address incrementation is enabled or not 1233 // <id> dmac_dstinc_5 1234 #ifndef CONF_DMAC_DSTINC_5 1235 #define CONF_DMAC_DSTINC_5 0 1236 #endif 1237 1238 // <o> Beat Size 1239 // <0=> 8-bit bus transfer 1240 // <1=> 16-bit bus transfer 1241 // <2=> 32-bit bus transfer 1242 // <i> Defines the size of one beat 1243 // <id> dmac_beatsize_5 1244 #ifndef CONF_DMAC_BEATSIZE_5 1245 #define CONF_DMAC_BEATSIZE_5 0 1246 #endif 1247 1248 // <o> Block Action 1249 // <0=> Channel will be disabled if it is the last block transfer in the transaction 1250 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 1251 // <2=> Channel suspend operation is complete 1252 // <3=> Both channel suspend operation and block interrupt 1253 // <i> Defines the the DMAC should take after a block transfer has completed 1254 // <id> dmac_blockact_5 1255 #ifndef CONF_DMAC_BLOCKACT_5 1256 #define CONF_DMAC_BLOCKACT_5 0 1257 #endif 1258 1259 // <o> Event Output Selection 1260 // <0=> Event generation disabled 1261 // <1=> Event strobe when block transfer complete 1262 // <3=> Event strobe when beat transfer complete 1263 // <i> Defines the event output selection 1264 // <id> dmac_evosel_5 1265 #ifndef CONF_DMAC_EVOSEL_5 1266 #define CONF_DMAC_EVOSEL_5 0 1267 #endif 1268 // </e> 1269 1270 // <e> Channel 6 settings 1271 // <id> dmac_channel_6_settings 1272 #ifndef CONF_DMAC_CHANNEL_6_SETTINGS 1273 #define CONF_DMAC_CHANNEL_6_SETTINGS 0 1274 #endif 1275 1276 // <q> Channel Enable 1277 // <i> Indicates whether channel 6 is enabled or not 1278 // <id> dmac_enable_6 1279 #ifndef CONF_DMAC_ENABLE_6 1280 #define CONF_DMAC_ENABLE_6 0 1281 #endif 1282 1283 // <q> Channel Run in Standby 1284 // <i> Indicates whether channel 6 is running in standby mode or not 1285 // <id> dmac_runstdby_6 1286 #ifndef CONF_DMAC_RUNSTDBY_6 1287 #define CONF_DMAC_RUNSTDBY_6 0 1288 #endif 1289 1290 // <o> Trigger action 1291 // <0=> One trigger required for each block transfer 1292 // <2=> One trigger required for each beat transfer 1293 // <3=> One trigger required for each transaction 1294 // <i> Defines the trigger action used for a transfer 1295 // <id> dmac_trigact_6 1296 #ifndef CONF_DMAC_TRIGACT_6 1297 #define CONF_DMAC_TRIGACT_6 0 1298 #endif 1299 1300 // <o> Trigger source 1301 // <0x00=> Only software/event triggers 1302 // <0x01=> SERCOM0 RX Trigger 1303 // <0x02=> SERCOM0 TX Trigger 1304 // <0x03=> SERCOM1 RX Trigger 1305 // <0x04=> SERCOM1 TX Trigger 1306 // <0x05=> SERCOM2 RX Trigger 1307 // <0x06=> SERCOM2 TX Trigger 1308 // <0x07=> SERCOM3 RX Trigger 1309 // <0x08=> SERCOM3 TX Trigger 1310 // <0x09=> SERCOM4 RX Trigger 1311 // <0x0A=> SERCOM4 TX Trigger 1312 // <0x0B=> TCC0 Overflow Trigger 1313 // <0x0C=> TCC0 Match/Compare 0 Trigger 1314 // <0x0D=> TCC0 Match/Compare 1 Trigger 1315 // <0x0E=> TCC0 Match/Compare 2 Trigger 1316 // <0x0F=> TCC0 Match/Compare 3 Trigger 1317 // <0x10=> TCC1 Overflow Trigger 1318 // <0x11=> TCC1 Match/Compare 0 Trigger 1319 // <0x12=> TCC1 Match/Compare 1 Trigger 1320 // <0x13=> TCC2 Overflow Trigger 1321 // <0x14=> TCC2 Match/Compare 0 Trigger 1322 // <0x15=> TCC2 Match/Compare 1 Trigger 1323 // <0x16=> TC0 Overflow Trigger 1324 // <0x17=> TC0 Match/Compare 0 Trigger 1325 // <0x18=> TC0 Match/Compare 1 Trigger 1326 // <0x19=> TC1 Overflow Trigger 1327 // <0x1A=> TC1 Match/Compare 0 Trigger 1328 // <0x1B=> TC1 Match/Compare 1 Trigger 1329 // <0x1C=> TC2 Overflow Trigger 1330 // <0x1D=> TC2 Match/Compare 0 Trigger 1331 // <0x1E=> TC2 Match/Compare 1 Trigger 1332 // <0x1F=> TC3 Overflow Trigger 1333 // <0x20=> TC3 Match/Compare 0 Trigger 1334 // <0x21=> TC3 Match/Compare 1 Trigger 1335 // <0x22=> TC4 Overflow Trigger 1336 // <0x23=> TC4 Match/Compare 0 Trigger 1337 // <0x24=> TC4 Match/Compare 1 Trigger 1338 // <0x25=> ADC Result Ready Trigger 1339 // <0x26=> DAC0 Empty Trigger 1340 // <0x27=> DAC1 Empty Trigger 1341 // <0x2C=> AES Write Trigger 1342 // <0x2D=> AES Read Trigger 1343 // <i> Defines the peripheral trigger which is source of the transfer 1344 // <id> dmac_trifsrc_6 1345 #ifndef CONF_DMAC_TRIGSRC_6 1346 #define CONF_DMAC_TRIGSRC_6 0 1347 #endif 1348 1349 // <o> Channel Arbitration Level 1350 // <0=> Channel priority 0 1351 // <1=> Channel priority 1 1352 // <2=> Channel priority 2 1353 // <3=> Channel priority 3 1354 // <i> Defines the arbitration level for this channel 1355 // <id> dmac_lvl_6 1356 #ifndef CONF_DMAC_LVL_6 1357 #define CONF_DMAC_LVL_6 0 1358 #endif 1359 1360 // <q> Channel Event Output 1361 // <i> Indicates whether channel event generation is enabled or not 1362 // <id> dmac_evoe_6 1363 #ifndef CONF_DMAC_EVOE_6 1364 #define CONF_DMAC_EVOE_6 0 1365 #endif 1366 1367 // <q> Channel Event Input 1368 // <i> Indicates whether channel event reception is enabled or not 1369 // <id> dmac_evie_6 1370 #ifndef CONF_DMAC_EVIE_6 1371 #define CONF_DMAC_EVIE_6 0 1372 #endif 1373 1374 // <o> Event Input Action 1375 // <0=> No action 1376 // <1=> Normal transfer and conditional transfer on strobe trigger 1377 // <2=> Conditional transfer trigger 1378 // <3=> Conditional block transfer 1379 // <4=> Channel suspend operation 1380 // <5=> Channel resume operation 1381 // <6=> Skip next block suspend action 1382 // <i> Defines the event input action 1383 // <id> dmac_evact_6 1384 #ifndef CONF_DMAC_EVACT_6 1385 #define CONF_DMAC_EVACT_6 0 1386 #endif 1387 1388 // <o> Address Increment Step Size 1389 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1390 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1391 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1392 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1393 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1394 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1395 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1396 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1397 // <i> Defines the address increment step size, applies to source or destination address 1398 // <id> dmac_stepsize_6 1399 #ifndef CONF_DMAC_STEPSIZE_6 1400 #define CONF_DMAC_STEPSIZE_6 0 1401 #endif 1402 1403 // <o> Step Selection 1404 // <0=> Step size settings apply to the destination address 1405 // <1=> Step size settings apply to the source address 1406 // <i> Defines whether source or destination addresses are using the step size settings 1407 // <id> dmac_stepsel_6 1408 #ifndef CONF_DMAC_STEPSEL_6 1409 #define CONF_DMAC_STEPSEL_6 0 1410 #endif 1411 1412 // <q> Source Address Increment 1413 // <i> Indicates whether the source address incrementation is enabled or not 1414 // <id> dmac_srcinc_6 1415 #ifndef CONF_DMAC_SRCINC_6 1416 #define CONF_DMAC_SRCINC_6 0 1417 #endif 1418 1419 // <q> Destination Address Increment 1420 // <i> Indicates whether the destination address incrementation is enabled or not 1421 // <id> dmac_dstinc_6 1422 #ifndef CONF_DMAC_DSTINC_6 1423 #define CONF_DMAC_DSTINC_6 0 1424 #endif 1425 1426 // <o> Beat Size 1427 // <0=> 8-bit bus transfer 1428 // <1=> 16-bit bus transfer 1429 // <2=> 32-bit bus transfer 1430 // <i> Defines the size of one beat 1431 // <id> dmac_beatsize_6 1432 #ifndef CONF_DMAC_BEATSIZE_6 1433 #define CONF_DMAC_BEATSIZE_6 0 1434 #endif 1435 1436 // <o> Block Action 1437 // <0=> Channel will be disabled if it is the last block transfer in the transaction 1438 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 1439 // <2=> Channel suspend operation is complete 1440 // <3=> Both channel suspend operation and block interrupt 1441 // <i> Defines the the DMAC should take after a block transfer has completed 1442 // <id> dmac_blockact_6 1443 #ifndef CONF_DMAC_BLOCKACT_6 1444 #define CONF_DMAC_BLOCKACT_6 0 1445 #endif 1446 1447 // <o> Event Output Selection 1448 // <0=> Event generation disabled 1449 // <1=> Event strobe when block transfer complete 1450 // <3=> Event strobe when beat transfer complete 1451 // <i> Defines the event output selection 1452 // <id> dmac_evosel_6 1453 #ifndef CONF_DMAC_EVOSEL_6 1454 #define CONF_DMAC_EVOSEL_6 0 1455 #endif 1456 // </e> 1457 1458 // <e> Channel 7 settings 1459 // <id> dmac_channel_7_settings 1460 #ifndef CONF_DMAC_CHANNEL_7_SETTINGS 1461 #define CONF_DMAC_CHANNEL_7_SETTINGS 0 1462 #endif 1463 1464 // <q> Channel Enable 1465 // <i> Indicates whether channel 7 is enabled or not 1466 // <id> dmac_enable_7 1467 #ifndef CONF_DMAC_ENABLE_7 1468 #define CONF_DMAC_ENABLE_7 0 1469 #endif 1470 1471 // <q> Channel Run in Standby 1472 // <i> Indicates whether channel 7 is running in standby mode or not 1473 // <id> dmac_runstdby_7 1474 #ifndef CONF_DMAC_RUNSTDBY_7 1475 #define CONF_DMAC_RUNSTDBY_7 0 1476 #endif 1477 1478 // <o> Trigger action 1479 // <0=> One trigger required for each block transfer 1480 // <2=> One trigger required for each beat transfer 1481 // <3=> One trigger required for each transaction 1482 // <i> Defines the trigger action used for a transfer 1483 // <id> dmac_trigact_7 1484 #ifndef CONF_DMAC_TRIGACT_7 1485 #define CONF_DMAC_TRIGACT_7 0 1486 #endif 1487 1488 // <o> Trigger source 1489 // <0x00=> Only software/event triggers 1490 // <0x01=> SERCOM0 RX Trigger 1491 // <0x02=> SERCOM0 TX Trigger 1492 // <0x03=> SERCOM1 RX Trigger 1493 // <0x04=> SERCOM1 TX Trigger 1494 // <0x05=> SERCOM2 RX Trigger 1495 // <0x06=> SERCOM2 TX Trigger 1496 // <0x07=> SERCOM3 RX Trigger 1497 // <0x08=> SERCOM3 TX Trigger 1498 // <0x09=> SERCOM4 RX Trigger 1499 // <0x0A=> SERCOM4 TX Trigger 1500 // <0x0B=> TCC0 Overflow Trigger 1501 // <0x0C=> TCC0 Match/Compare 0 Trigger 1502 // <0x0D=> TCC0 Match/Compare 1 Trigger 1503 // <0x0E=> TCC0 Match/Compare 2 Trigger 1504 // <0x0F=> TCC0 Match/Compare 3 Trigger 1505 // <0x10=> TCC1 Overflow Trigger 1506 // <0x11=> TCC1 Match/Compare 0 Trigger 1507 // <0x12=> TCC1 Match/Compare 1 Trigger 1508 // <0x13=> TCC2 Overflow Trigger 1509 // <0x14=> TCC2 Match/Compare 0 Trigger 1510 // <0x15=> TCC2 Match/Compare 1 Trigger 1511 // <0x16=> TC0 Overflow Trigger 1512 // <0x17=> TC0 Match/Compare 0 Trigger 1513 // <0x18=> TC0 Match/Compare 1 Trigger 1514 // <0x19=> TC1 Overflow Trigger 1515 // <0x1A=> TC1 Match/Compare 0 Trigger 1516 // <0x1B=> TC1 Match/Compare 1 Trigger 1517 // <0x1C=> TC2 Overflow Trigger 1518 // <0x1D=> TC2 Match/Compare 0 Trigger 1519 // <0x1E=> TC2 Match/Compare 1 Trigger 1520 // <0x1F=> TC3 Overflow Trigger 1521 // <0x20=> TC3 Match/Compare 0 Trigger 1522 // <0x21=> TC3 Match/Compare 1 Trigger 1523 // <0x22=> TC4 Overflow Trigger 1524 // <0x23=> TC4 Match/Compare 0 Trigger 1525 // <0x24=> TC4 Match/Compare 1 Trigger 1526 // <0x25=> ADC Result Ready Trigger 1527 // <0x26=> DAC0 Empty Trigger 1528 // <0x27=> DAC1 Empty Trigger 1529 // <0x2C=> AES Write Trigger 1530 // <0x2D=> AES Read Trigger 1531 // <i> Defines the peripheral trigger which is source of the transfer 1532 // <id> dmac_trifsrc_7 1533 #ifndef CONF_DMAC_TRIGSRC_7 1534 #define CONF_DMAC_TRIGSRC_7 0 1535 #endif 1536 1537 // <o> Channel Arbitration Level 1538 // <0=> Channel priority 0 1539 // <1=> Channel priority 1 1540 // <2=> Channel priority 2 1541 // <3=> Channel priority 3 1542 // <i> Defines the arbitration level for this channel 1543 // <id> dmac_lvl_7 1544 #ifndef CONF_DMAC_LVL_7 1545 #define CONF_DMAC_LVL_7 0 1546 #endif 1547 1548 // <q> Channel Event Output 1549 // <i> Indicates whether channel event generation is enabled or not 1550 // <id> dmac_evoe_7 1551 #ifndef CONF_DMAC_EVOE_7 1552 #define CONF_DMAC_EVOE_7 0 1553 #endif 1554 1555 // <q> Channel Event Input 1556 // <i> Indicates whether channel event reception is enabled or not 1557 // <id> dmac_evie_7 1558 #ifndef CONF_DMAC_EVIE_7 1559 #define CONF_DMAC_EVIE_7 0 1560 #endif 1561 1562 // <o> Event Input Action 1563 // <0=> No action 1564 // <1=> Normal transfer and conditional transfer on strobe trigger 1565 // <2=> Conditional transfer trigger 1566 // <3=> Conditional block transfer 1567 // <4=> Channel suspend operation 1568 // <5=> Channel resume operation 1569 // <6=> Skip next block suspend action 1570 // <i> Defines the event input action 1571 // <id> dmac_evact_7 1572 #ifndef CONF_DMAC_EVACT_7 1573 #define CONF_DMAC_EVACT_7 0 1574 #endif 1575 1576 // <o> Address Increment Step Size 1577 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1578 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1579 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1580 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1581 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1582 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1583 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1584 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1585 // <i> Defines the address increment step size, applies to source or destination address 1586 // <id> dmac_stepsize_7 1587 #ifndef CONF_DMAC_STEPSIZE_7 1588 #define CONF_DMAC_STEPSIZE_7 0 1589 #endif 1590 1591 // <o> Step Selection 1592 // <0=> Step size settings apply to the destination address 1593 // <1=> Step size settings apply to the source address 1594 // <i> Defines whether source or destination addresses are using the step size settings 1595 // <id> dmac_stepsel_7 1596 #ifndef CONF_DMAC_STEPSEL_7 1597 #define CONF_DMAC_STEPSEL_7 0 1598 #endif 1599 1600 // <q> Source Address Increment 1601 // <i> Indicates whether the source address incrementation is enabled or not 1602 // <id> dmac_srcinc_7 1603 #ifndef CONF_DMAC_SRCINC_7 1604 #define CONF_DMAC_SRCINC_7 0 1605 #endif 1606 1607 // <q> Destination Address Increment 1608 // <i> Indicates whether the destination address incrementation is enabled or not 1609 // <id> dmac_dstinc_7 1610 #ifndef CONF_DMAC_DSTINC_7 1611 #define CONF_DMAC_DSTINC_7 0 1612 #endif 1613 1614 // <o> Beat Size 1615 // <0=> 8-bit bus transfer 1616 // <1=> 16-bit bus transfer 1617 // <2=> 32-bit bus transfer 1618 // <i> Defines the size of one beat 1619 // <id> dmac_beatsize_7 1620 #ifndef CONF_DMAC_BEATSIZE_7 1621 #define CONF_DMAC_BEATSIZE_7 0 1622 #endif 1623 1624 // <o> Block Action 1625 // <0=> Channel will be disabled if it is the last block transfer in the transaction 1626 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 1627 // <2=> Channel suspend operation is complete 1628 // <3=> Both channel suspend operation and block interrupt 1629 // <i> Defines the the DMAC should take after a block transfer has completed 1630 // <id> dmac_blockact_7 1631 #ifndef CONF_DMAC_BLOCKACT_7 1632 #define CONF_DMAC_BLOCKACT_7 0 1633 #endif 1634 1635 // <o> Event Output Selection 1636 // <0=> Event generation disabled 1637 // <1=> Event strobe when block transfer complete 1638 // <3=> Event strobe when beat transfer complete 1639 // <i> Defines the event output selection 1640 // <id> dmac_evosel_7 1641 #ifndef CONF_DMAC_EVOSEL_7 1642 #define CONF_DMAC_EVOSEL_7 0 1643 #endif 1644 // </e> 1645 1646 // <e> Channel 8 settings 1647 // <id> dmac_channel_8_settings 1648 #ifndef CONF_DMAC_CHANNEL_8_SETTINGS 1649 #define CONF_DMAC_CHANNEL_8_SETTINGS 0 1650 #endif 1651 1652 // <q> Channel Enable 1653 // <i> Indicates whether channel 8 is enabled or not 1654 // <id> dmac_enable_8 1655 #ifndef CONF_DMAC_ENABLE_8 1656 #define CONF_DMAC_ENABLE_8 0 1657 #endif 1658 1659 // <q> Channel Run in Standby 1660 // <i> Indicates whether channel 8 is running in standby mode or not 1661 // <id> dmac_runstdby_8 1662 #ifndef CONF_DMAC_RUNSTDBY_8 1663 #define CONF_DMAC_RUNSTDBY_8 0 1664 #endif 1665 1666 // <o> Trigger action 1667 // <0=> One trigger required for each block transfer 1668 // <2=> One trigger required for each beat transfer 1669 // <3=> One trigger required for each transaction 1670 // <i> Defines the trigger action used for a transfer 1671 // <id> dmac_trigact_8 1672 #ifndef CONF_DMAC_TRIGACT_8 1673 #define CONF_DMAC_TRIGACT_8 0 1674 #endif 1675 1676 // <o> Trigger source 1677 // <0x00=> Only software/event triggers 1678 // <0x01=> SERCOM0 RX Trigger 1679 // <0x02=> SERCOM0 TX Trigger 1680 // <0x03=> SERCOM1 RX Trigger 1681 // <0x04=> SERCOM1 TX Trigger 1682 // <0x05=> SERCOM2 RX Trigger 1683 // <0x06=> SERCOM2 TX Trigger 1684 // <0x07=> SERCOM3 RX Trigger 1685 // <0x08=> SERCOM3 TX Trigger 1686 // <0x09=> SERCOM4 RX Trigger 1687 // <0x0A=> SERCOM4 TX Trigger 1688 // <0x0B=> TCC0 Overflow Trigger 1689 // <0x0C=> TCC0 Match/Compare 0 Trigger 1690 // <0x0D=> TCC0 Match/Compare 1 Trigger 1691 // <0x0E=> TCC0 Match/Compare 2 Trigger 1692 // <0x0F=> TCC0 Match/Compare 3 Trigger 1693 // <0x10=> TCC1 Overflow Trigger 1694 // <0x11=> TCC1 Match/Compare 0 Trigger 1695 // <0x12=> TCC1 Match/Compare 1 Trigger 1696 // <0x13=> TCC2 Overflow Trigger 1697 // <0x14=> TCC2 Match/Compare 0 Trigger 1698 // <0x15=> TCC2 Match/Compare 1 Trigger 1699 // <0x16=> TC0 Overflow Trigger 1700 // <0x17=> TC0 Match/Compare 0 Trigger 1701 // <0x18=> TC0 Match/Compare 1 Trigger 1702 // <0x19=> TC1 Overflow Trigger 1703 // <0x1A=> TC1 Match/Compare 0 Trigger 1704 // <0x1B=> TC1 Match/Compare 1 Trigger 1705 // <0x1C=> TC2 Overflow Trigger 1706 // <0x1D=> TC2 Match/Compare 0 Trigger 1707 // <0x1E=> TC2 Match/Compare 1 Trigger 1708 // <0x1F=> TC3 Overflow Trigger 1709 // <0x20=> TC3 Match/Compare 0 Trigger 1710 // <0x21=> TC3 Match/Compare 1 Trigger 1711 // <0x22=> TC4 Overflow Trigger 1712 // <0x23=> TC4 Match/Compare 0 Trigger 1713 // <0x24=> TC4 Match/Compare 1 Trigger 1714 // <0x25=> ADC Result Ready Trigger 1715 // <0x26=> DAC0 Empty Trigger 1716 // <0x27=> DAC1 Empty Trigger 1717 // <0x2C=> AES Write Trigger 1718 // <0x2D=> AES Read Trigger 1719 // <i> Defines the peripheral trigger which is source of the transfer 1720 // <id> dmac_trifsrc_8 1721 #ifndef CONF_DMAC_TRIGSRC_8 1722 #define CONF_DMAC_TRIGSRC_8 0 1723 #endif 1724 1725 // <o> Channel Arbitration Level 1726 // <0=> Channel priority 0 1727 // <1=> Channel priority 1 1728 // <2=> Channel priority 2 1729 // <3=> Channel priority 3 1730 // <i> Defines the arbitration level for this channel 1731 // <id> dmac_lvl_8 1732 #ifndef CONF_DMAC_LVL_8 1733 #define CONF_DMAC_LVL_8 0 1734 #endif 1735 1736 // <q> Channel Event Output 1737 // <i> Indicates whether channel event generation is enabled or not 1738 // <id> dmac_evoe_8 1739 #ifndef CONF_DMAC_EVOE_8 1740 #define CONF_DMAC_EVOE_8 0 1741 #endif 1742 1743 // <q> Channel Event Input 1744 // <i> Indicates whether channel event reception is enabled or not 1745 // <id> dmac_evie_8 1746 #ifndef CONF_DMAC_EVIE_8 1747 #define CONF_DMAC_EVIE_8 0 1748 #endif 1749 1750 // <o> Event Input Action 1751 // <0=> No action 1752 // <1=> Normal transfer and conditional transfer on strobe trigger 1753 // <2=> Conditional transfer trigger 1754 // <3=> Conditional block transfer 1755 // <4=> Channel suspend operation 1756 // <5=> Channel resume operation 1757 // <6=> Skip next block suspend action 1758 // <i> Defines the event input action 1759 // <id> dmac_evact_8 1760 #ifndef CONF_DMAC_EVACT_8 1761 #define CONF_DMAC_EVACT_8 0 1762 #endif 1763 1764 // <o> Address Increment Step Size 1765 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1766 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1767 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1768 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1769 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1770 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1771 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1772 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1773 // <i> Defines the address increment step size, applies to source or destination address 1774 // <id> dmac_stepsize_8 1775 #ifndef CONF_DMAC_STEPSIZE_8 1776 #define CONF_DMAC_STEPSIZE_8 0 1777 #endif 1778 1779 // <o> Step Selection 1780 // <0=> Step size settings apply to the destination address 1781 // <1=> Step size settings apply to the source address 1782 // <i> Defines whether source or destination addresses are using the step size settings 1783 // <id> dmac_stepsel_8 1784 #ifndef CONF_DMAC_STEPSEL_8 1785 #define CONF_DMAC_STEPSEL_8 0 1786 #endif 1787 1788 // <q> Source Address Increment 1789 // <i> Indicates whether the source address incrementation is enabled or not 1790 // <id> dmac_srcinc_8 1791 #ifndef CONF_DMAC_SRCINC_8 1792 #define CONF_DMAC_SRCINC_8 0 1793 #endif 1794 1795 // <q> Destination Address Increment 1796 // <i> Indicates whether the destination address incrementation is enabled or not 1797 // <id> dmac_dstinc_8 1798 #ifndef CONF_DMAC_DSTINC_8 1799 #define CONF_DMAC_DSTINC_8 0 1800 #endif 1801 1802 // <o> Beat Size 1803 // <0=> 8-bit bus transfer 1804 // <1=> 16-bit bus transfer 1805 // <2=> 32-bit bus transfer 1806 // <i> Defines the size of one beat 1807 // <id> dmac_beatsize_8 1808 #ifndef CONF_DMAC_BEATSIZE_8 1809 #define CONF_DMAC_BEATSIZE_8 0 1810 #endif 1811 1812 // <o> Block Action 1813 // <0=> Channel will be disabled if it is the last block transfer in the transaction 1814 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 1815 // <2=> Channel suspend operation is complete 1816 // <3=> Both channel suspend operation and block interrupt 1817 // <i> Defines the the DMAC should take after a block transfer has completed 1818 // <id> dmac_blockact_8 1819 #ifndef CONF_DMAC_BLOCKACT_8 1820 #define CONF_DMAC_BLOCKACT_8 0 1821 #endif 1822 1823 // <o> Event Output Selection 1824 // <0=> Event generation disabled 1825 // <1=> Event strobe when block transfer complete 1826 // <3=> Event strobe when beat transfer complete 1827 // <i> Defines the event output selection 1828 // <id> dmac_evosel_8 1829 #ifndef CONF_DMAC_EVOSEL_8 1830 #define CONF_DMAC_EVOSEL_8 0 1831 #endif 1832 // </e> 1833 1834 // <e> Channel 9 settings 1835 // <id> dmac_channel_9_settings 1836 #ifndef CONF_DMAC_CHANNEL_9_SETTINGS 1837 #define CONF_DMAC_CHANNEL_9_SETTINGS 0 1838 #endif 1839 1840 // <q> Channel Enable 1841 // <i> Indicates whether channel 9 is enabled or not 1842 // <id> dmac_enable_9 1843 #ifndef CONF_DMAC_ENABLE_9 1844 #define CONF_DMAC_ENABLE_9 0 1845 #endif 1846 1847 // <q> Channel Run in Standby 1848 // <i> Indicates whether channel 9 is running in standby mode or not 1849 // <id> dmac_runstdby_9 1850 #ifndef CONF_DMAC_RUNSTDBY_9 1851 #define CONF_DMAC_RUNSTDBY_9 0 1852 #endif 1853 1854 // <o> Trigger action 1855 // <0=> One trigger required for each block transfer 1856 // <2=> One trigger required for each beat transfer 1857 // <3=> One trigger required for each transaction 1858 // <i> Defines the trigger action used for a transfer 1859 // <id> dmac_trigact_9 1860 #ifndef CONF_DMAC_TRIGACT_9 1861 #define CONF_DMAC_TRIGACT_9 0 1862 #endif 1863 1864 // <o> Trigger source 1865 // <0x00=> Only software/event triggers 1866 // <0x01=> SERCOM0 RX Trigger 1867 // <0x02=> SERCOM0 TX Trigger 1868 // <0x03=> SERCOM1 RX Trigger 1869 // <0x04=> SERCOM1 TX Trigger 1870 // <0x05=> SERCOM2 RX Trigger 1871 // <0x06=> SERCOM2 TX Trigger 1872 // <0x07=> SERCOM3 RX Trigger 1873 // <0x08=> SERCOM3 TX Trigger 1874 // <0x09=> SERCOM4 RX Trigger 1875 // <0x0A=> SERCOM4 TX Trigger 1876 // <0x0B=> TCC0 Overflow Trigger 1877 // <0x0C=> TCC0 Match/Compare 0 Trigger 1878 // <0x0D=> TCC0 Match/Compare 1 Trigger 1879 // <0x0E=> TCC0 Match/Compare 2 Trigger 1880 // <0x0F=> TCC0 Match/Compare 3 Trigger 1881 // <0x10=> TCC1 Overflow Trigger 1882 // <0x11=> TCC1 Match/Compare 0 Trigger 1883 // <0x12=> TCC1 Match/Compare 1 Trigger 1884 // <0x13=> TCC2 Overflow Trigger 1885 // <0x14=> TCC2 Match/Compare 0 Trigger 1886 // <0x15=> TCC2 Match/Compare 1 Trigger 1887 // <0x16=> TC0 Overflow Trigger 1888 // <0x17=> TC0 Match/Compare 0 Trigger 1889 // <0x18=> TC0 Match/Compare 1 Trigger 1890 // <0x19=> TC1 Overflow Trigger 1891 // <0x1A=> TC1 Match/Compare 0 Trigger 1892 // <0x1B=> TC1 Match/Compare 1 Trigger 1893 // <0x1C=> TC2 Overflow Trigger 1894 // <0x1D=> TC2 Match/Compare 0 Trigger 1895 // <0x1E=> TC2 Match/Compare 1 Trigger 1896 // <0x1F=> TC3 Overflow Trigger 1897 // <0x20=> TC3 Match/Compare 0 Trigger 1898 // <0x21=> TC3 Match/Compare 1 Trigger 1899 // <0x22=> TC4 Overflow Trigger 1900 // <0x23=> TC4 Match/Compare 0 Trigger 1901 // <0x24=> TC4 Match/Compare 1 Trigger 1902 // <0x25=> ADC Result Ready Trigger 1903 // <0x26=> DAC0 Empty Trigger 1904 // <0x27=> DAC1 Empty Trigger 1905 // <0x2C=> AES Write Trigger 1906 // <0x2D=> AES Read Trigger 1907 // <i> Defines the peripheral trigger which is source of the transfer 1908 // <id> dmac_trifsrc_9 1909 #ifndef CONF_DMAC_TRIGSRC_9 1910 #define CONF_DMAC_TRIGSRC_9 0 1911 #endif 1912 1913 // <o> Channel Arbitration Level 1914 // <0=> Channel priority 0 1915 // <1=> Channel priority 1 1916 // <2=> Channel priority 2 1917 // <3=> Channel priority 3 1918 // <i> Defines the arbitration level for this channel 1919 // <id> dmac_lvl_9 1920 #ifndef CONF_DMAC_LVL_9 1921 #define CONF_DMAC_LVL_9 0 1922 #endif 1923 1924 // <q> Channel Event Output 1925 // <i> Indicates whether channel event generation is enabled or not 1926 // <id> dmac_evoe_9 1927 #ifndef CONF_DMAC_EVOE_9 1928 #define CONF_DMAC_EVOE_9 0 1929 #endif 1930 1931 // <q> Channel Event Input 1932 // <i> Indicates whether channel event reception is enabled or not 1933 // <id> dmac_evie_9 1934 #ifndef CONF_DMAC_EVIE_9 1935 #define CONF_DMAC_EVIE_9 0 1936 #endif 1937 1938 // <o> Event Input Action 1939 // <0=> No action 1940 // <1=> Normal transfer and conditional transfer on strobe trigger 1941 // <2=> Conditional transfer trigger 1942 // <3=> Conditional block transfer 1943 // <4=> Channel suspend operation 1944 // <5=> Channel resume operation 1945 // <6=> Skip next block suspend action 1946 // <i> Defines the event input action 1947 // <id> dmac_evact_9 1948 #ifndef CONF_DMAC_EVACT_9 1949 #define CONF_DMAC_EVACT_9 0 1950 #endif 1951 1952 // <o> Address Increment Step Size 1953 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 1954 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 1955 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 1956 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 1957 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 1958 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 1959 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 1960 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 1961 // <i> Defines the address increment step size, applies to source or destination address 1962 // <id> dmac_stepsize_9 1963 #ifndef CONF_DMAC_STEPSIZE_9 1964 #define CONF_DMAC_STEPSIZE_9 0 1965 #endif 1966 1967 // <o> Step Selection 1968 // <0=> Step size settings apply to the destination address 1969 // <1=> Step size settings apply to the source address 1970 // <i> Defines whether source or destination addresses are using the step size settings 1971 // <id> dmac_stepsel_9 1972 #ifndef CONF_DMAC_STEPSEL_9 1973 #define CONF_DMAC_STEPSEL_9 0 1974 #endif 1975 1976 // <q> Source Address Increment 1977 // <i> Indicates whether the source address incrementation is enabled or not 1978 // <id> dmac_srcinc_9 1979 #ifndef CONF_DMAC_SRCINC_9 1980 #define CONF_DMAC_SRCINC_9 0 1981 #endif 1982 1983 // <q> Destination Address Increment 1984 // <i> Indicates whether the destination address incrementation is enabled or not 1985 // <id> dmac_dstinc_9 1986 #ifndef CONF_DMAC_DSTINC_9 1987 #define CONF_DMAC_DSTINC_9 0 1988 #endif 1989 1990 // <o> Beat Size 1991 // <0=> 8-bit bus transfer 1992 // <1=> 16-bit bus transfer 1993 // <2=> 32-bit bus transfer 1994 // <i> Defines the size of one beat 1995 // <id> dmac_beatsize_9 1996 #ifndef CONF_DMAC_BEATSIZE_9 1997 #define CONF_DMAC_BEATSIZE_9 0 1998 #endif 1999 2000 // <o> Block Action 2001 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2002 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2003 // <2=> Channel suspend operation is complete 2004 // <3=> Both channel suspend operation and block interrupt 2005 // <i> Defines the the DMAC should take after a block transfer has completed 2006 // <id> dmac_blockact_9 2007 #ifndef CONF_DMAC_BLOCKACT_9 2008 #define CONF_DMAC_BLOCKACT_9 0 2009 #endif 2010 2011 // <o> Event Output Selection 2012 // <0=> Event generation disabled 2013 // <1=> Event strobe when block transfer complete 2014 // <3=> Event strobe when beat transfer complete 2015 // <i> Defines the event output selection 2016 // <id> dmac_evosel_9 2017 #ifndef CONF_DMAC_EVOSEL_9 2018 #define CONF_DMAC_EVOSEL_9 0 2019 #endif 2020 // </e> 2021 2022 // <e> Channel 10 settings 2023 // <id> dmac_channel_10_settings 2024 #ifndef CONF_DMAC_CHANNEL_10_SETTINGS 2025 #define CONF_DMAC_CHANNEL_10_SETTINGS 0 2026 #endif 2027 2028 // <q> Channel Enable 2029 // <i> Indicates whether channel 10 is enabled or not 2030 // <id> dmac_enable_10 2031 #ifndef CONF_DMAC_ENABLE_10 2032 #define CONF_DMAC_ENABLE_10 0 2033 #endif 2034 2035 // <q> Channel Run in Standby 2036 // <i> Indicates whether channel 10 is running in standby mode or not 2037 // <id> dmac_runstdby_10 2038 #ifndef CONF_DMAC_RUNSTDBY_10 2039 #define CONF_DMAC_RUNSTDBY_10 0 2040 #endif 2041 2042 // <o> Trigger action 2043 // <0=> One trigger required for each block transfer 2044 // <2=> One trigger required for each beat transfer 2045 // <3=> One trigger required for each transaction 2046 // <i> Defines the trigger action used for a transfer 2047 // <id> dmac_trigact_10 2048 #ifndef CONF_DMAC_TRIGACT_10 2049 #define CONF_DMAC_TRIGACT_10 0 2050 #endif 2051 2052 // <o> Trigger source 2053 // <0x00=> Only software/event triggers 2054 // <0x01=> SERCOM0 RX Trigger 2055 // <0x02=> SERCOM0 TX Trigger 2056 // <0x03=> SERCOM1 RX Trigger 2057 // <0x04=> SERCOM1 TX Trigger 2058 // <0x05=> SERCOM2 RX Trigger 2059 // <0x06=> SERCOM2 TX Trigger 2060 // <0x07=> SERCOM3 RX Trigger 2061 // <0x08=> SERCOM3 TX Trigger 2062 // <0x09=> SERCOM4 RX Trigger 2063 // <0x0A=> SERCOM4 TX Trigger 2064 // <0x0B=> TCC0 Overflow Trigger 2065 // <0x0C=> TCC0 Match/Compare 0 Trigger 2066 // <0x0D=> TCC0 Match/Compare 1 Trigger 2067 // <0x0E=> TCC0 Match/Compare 2 Trigger 2068 // <0x0F=> TCC0 Match/Compare 3 Trigger 2069 // <0x10=> TCC1 Overflow Trigger 2070 // <0x11=> TCC1 Match/Compare 0 Trigger 2071 // <0x12=> TCC1 Match/Compare 1 Trigger 2072 // <0x13=> TCC2 Overflow Trigger 2073 // <0x14=> TCC2 Match/Compare 0 Trigger 2074 // <0x15=> TCC2 Match/Compare 1 Trigger 2075 // <0x16=> TC0 Overflow Trigger 2076 // <0x17=> TC0 Match/Compare 0 Trigger 2077 // <0x18=> TC0 Match/Compare 1 Trigger 2078 // <0x19=> TC1 Overflow Trigger 2079 // <0x1A=> TC1 Match/Compare 0 Trigger 2080 // <0x1B=> TC1 Match/Compare 1 Trigger 2081 // <0x1C=> TC2 Overflow Trigger 2082 // <0x1D=> TC2 Match/Compare 0 Trigger 2083 // <0x1E=> TC2 Match/Compare 1 Trigger 2084 // <0x1F=> TC3 Overflow Trigger 2085 // <0x20=> TC3 Match/Compare 0 Trigger 2086 // <0x21=> TC3 Match/Compare 1 Trigger 2087 // <0x22=> TC4 Overflow Trigger 2088 // <0x23=> TC4 Match/Compare 0 Trigger 2089 // <0x24=> TC4 Match/Compare 1 Trigger 2090 // <0x25=> ADC Result Ready Trigger 2091 // <0x26=> DAC0 Empty Trigger 2092 // <0x27=> DAC1 Empty Trigger 2093 // <0x2C=> AES Write Trigger 2094 // <0x2D=> AES Read Trigger 2095 // <i> Defines the peripheral trigger which is source of the transfer 2096 // <id> dmac_trifsrc_10 2097 #ifndef CONF_DMAC_TRIGSRC_10 2098 #define CONF_DMAC_TRIGSRC_10 0 2099 #endif 2100 2101 // <o> Channel Arbitration Level 2102 // <0=> Channel priority 0 2103 // <1=> Channel priority 1 2104 // <2=> Channel priority 2 2105 // <3=> Channel priority 3 2106 // <i> Defines the arbitration level for this channel 2107 // <id> dmac_lvl_10 2108 #ifndef CONF_DMAC_LVL_10 2109 #define CONF_DMAC_LVL_10 0 2110 #endif 2111 2112 // <q> Channel Event Output 2113 // <i> Indicates whether channel event generation is enabled or not 2114 // <id> dmac_evoe_10 2115 #ifndef CONF_DMAC_EVOE_10 2116 #define CONF_DMAC_EVOE_10 0 2117 #endif 2118 2119 // <q> Channel Event Input 2120 // <i> Indicates whether channel event reception is enabled or not 2121 // <id> dmac_evie_10 2122 #ifndef CONF_DMAC_EVIE_10 2123 #define CONF_DMAC_EVIE_10 0 2124 #endif 2125 2126 // <o> Event Input Action 2127 // <0=> No action 2128 // <1=> Normal transfer and conditional transfer on strobe trigger 2129 // <2=> Conditional transfer trigger 2130 // <3=> Conditional block transfer 2131 // <4=> Channel suspend operation 2132 // <5=> Channel resume operation 2133 // <6=> Skip next block suspend action 2134 // <i> Defines the event input action 2135 // <id> dmac_evact_10 2136 #ifndef CONF_DMAC_EVACT_10 2137 #define CONF_DMAC_EVACT_10 0 2138 #endif 2139 2140 // <o> Address Increment Step Size 2141 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 2142 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 2143 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 2144 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 2145 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 2146 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 2147 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 2148 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 2149 // <i> Defines the address increment step size, applies to source or destination address 2150 // <id> dmac_stepsize_10 2151 #ifndef CONF_DMAC_STEPSIZE_10 2152 #define CONF_DMAC_STEPSIZE_10 0 2153 #endif 2154 2155 // <o> Step Selection 2156 // <0=> Step size settings apply to the destination address 2157 // <1=> Step size settings apply to the source address 2158 // <i> Defines whether source or destination addresses are using the step size settings 2159 // <id> dmac_stepsel_10 2160 #ifndef CONF_DMAC_STEPSEL_10 2161 #define CONF_DMAC_STEPSEL_10 0 2162 #endif 2163 2164 // <q> Source Address Increment 2165 // <i> Indicates whether the source address incrementation is enabled or not 2166 // <id> dmac_srcinc_10 2167 #ifndef CONF_DMAC_SRCINC_10 2168 #define CONF_DMAC_SRCINC_10 0 2169 #endif 2170 2171 // <q> Destination Address Increment 2172 // <i> Indicates whether the destination address incrementation is enabled or not 2173 // <id> dmac_dstinc_10 2174 #ifndef CONF_DMAC_DSTINC_10 2175 #define CONF_DMAC_DSTINC_10 0 2176 #endif 2177 2178 // <o> Beat Size 2179 // <0=> 8-bit bus transfer 2180 // <1=> 16-bit bus transfer 2181 // <2=> 32-bit bus transfer 2182 // <i> Defines the size of one beat 2183 // <id> dmac_beatsize_10 2184 #ifndef CONF_DMAC_BEATSIZE_10 2185 #define CONF_DMAC_BEATSIZE_10 0 2186 #endif 2187 2188 // <o> Block Action 2189 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2190 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2191 // <2=> Channel suspend operation is complete 2192 // <3=> Both channel suspend operation and block interrupt 2193 // <i> Defines the the DMAC should take after a block transfer has completed 2194 // <id> dmac_blockact_10 2195 #ifndef CONF_DMAC_BLOCKACT_10 2196 #define CONF_DMAC_BLOCKACT_10 0 2197 #endif 2198 2199 // <o> Event Output Selection 2200 // <0=> Event generation disabled 2201 // <1=> Event strobe when block transfer complete 2202 // <3=> Event strobe when beat transfer complete 2203 // <i> Defines the event output selection 2204 // <id> dmac_evosel_10 2205 #ifndef CONF_DMAC_EVOSEL_10 2206 #define CONF_DMAC_EVOSEL_10 0 2207 #endif 2208 // </e> 2209 2210 // <e> Channel 11 settings 2211 // <id> dmac_channel_11_settings 2212 #ifndef CONF_DMAC_CHANNEL_11_SETTINGS 2213 #define CONF_DMAC_CHANNEL_11_SETTINGS 0 2214 #endif 2215 2216 // <q> Channel Enable 2217 // <i> Indicates whether channel 11 is enabled or not 2218 // <id> dmac_enable_11 2219 #ifndef CONF_DMAC_ENABLE_11 2220 #define CONF_DMAC_ENABLE_11 0 2221 #endif 2222 2223 // <q> Channel Run in Standby 2224 // <i> Indicates whether channel 11 is running in standby mode or not 2225 // <id> dmac_runstdby_11 2226 #ifndef CONF_DMAC_RUNSTDBY_11 2227 #define CONF_DMAC_RUNSTDBY_11 0 2228 #endif 2229 2230 // <o> Trigger action 2231 // <0=> One trigger required for each block transfer 2232 // <2=> One trigger required for each beat transfer 2233 // <3=> One trigger required for each transaction 2234 // <i> Defines the trigger action used for a transfer 2235 // <id> dmac_trigact_11 2236 #ifndef CONF_DMAC_TRIGACT_11 2237 #define CONF_DMAC_TRIGACT_11 0 2238 #endif 2239 2240 // <o> Trigger source 2241 // <0x00=> Only software/event triggers 2242 // <0x01=> SERCOM0 RX Trigger 2243 // <0x02=> SERCOM0 TX Trigger 2244 // <0x03=> SERCOM1 RX Trigger 2245 // <0x04=> SERCOM1 TX Trigger 2246 // <0x05=> SERCOM2 RX Trigger 2247 // <0x06=> SERCOM2 TX Trigger 2248 // <0x07=> SERCOM3 RX Trigger 2249 // <0x08=> SERCOM3 TX Trigger 2250 // <0x09=> SERCOM4 RX Trigger 2251 // <0x0A=> SERCOM4 TX Trigger 2252 // <0x0B=> TCC0 Overflow Trigger 2253 // <0x0C=> TCC0 Match/Compare 0 Trigger 2254 // <0x0D=> TCC0 Match/Compare 1 Trigger 2255 // <0x0E=> TCC0 Match/Compare 2 Trigger 2256 // <0x0F=> TCC0 Match/Compare 3 Trigger 2257 // <0x10=> TCC1 Overflow Trigger 2258 // <0x11=> TCC1 Match/Compare 0 Trigger 2259 // <0x12=> TCC1 Match/Compare 1 Trigger 2260 // <0x13=> TCC2 Overflow Trigger 2261 // <0x14=> TCC2 Match/Compare 0 Trigger 2262 // <0x15=> TCC2 Match/Compare 1 Trigger 2263 // <0x16=> TC0 Overflow Trigger 2264 // <0x17=> TC0 Match/Compare 0 Trigger 2265 // <0x18=> TC0 Match/Compare 1 Trigger 2266 // <0x19=> TC1 Overflow Trigger 2267 // <0x1A=> TC1 Match/Compare 0 Trigger 2268 // <0x1B=> TC1 Match/Compare 1 Trigger 2269 // <0x1C=> TC2 Overflow Trigger 2270 // <0x1D=> TC2 Match/Compare 0 Trigger 2271 // <0x1E=> TC2 Match/Compare 1 Trigger 2272 // <0x1F=> TC3 Overflow Trigger 2273 // <0x20=> TC3 Match/Compare 0 Trigger 2274 // <0x21=> TC3 Match/Compare 1 Trigger 2275 // <0x22=> TC4 Overflow Trigger 2276 // <0x23=> TC4 Match/Compare 0 Trigger 2277 // <0x24=> TC4 Match/Compare 1 Trigger 2278 // <0x25=> ADC Result Ready Trigger 2279 // <0x26=> DAC0 Empty Trigger 2280 // <0x27=> DAC1 Empty Trigger 2281 // <0x2C=> AES Write Trigger 2282 // <0x2D=> AES Read Trigger 2283 // <i> Defines the peripheral trigger which is source of the transfer 2284 // <id> dmac_trifsrc_11 2285 #ifndef CONF_DMAC_TRIGSRC_11 2286 #define CONF_DMAC_TRIGSRC_11 0 2287 #endif 2288 2289 // <o> Channel Arbitration Level 2290 // <0=> Channel priority 0 2291 // <1=> Channel priority 1 2292 // <2=> Channel priority 2 2293 // <3=> Channel priority 3 2294 // <i> Defines the arbitration level for this channel 2295 // <id> dmac_lvl_11 2296 #ifndef CONF_DMAC_LVL_11 2297 #define CONF_DMAC_LVL_11 0 2298 #endif 2299 2300 // <q> Channel Event Output 2301 // <i> Indicates whether channel event generation is enabled or not 2302 // <id> dmac_evoe_11 2303 #ifndef CONF_DMAC_EVOE_11 2304 #define CONF_DMAC_EVOE_11 0 2305 #endif 2306 2307 // <q> Channel Event Input 2308 // <i> Indicates whether channel event reception is enabled or not 2309 // <id> dmac_evie_11 2310 #ifndef CONF_DMAC_EVIE_11 2311 #define CONF_DMAC_EVIE_11 0 2312 #endif 2313 2314 // <o> Event Input Action 2315 // <0=> No action 2316 // <1=> Normal transfer and conditional transfer on strobe trigger 2317 // <2=> Conditional transfer trigger 2318 // <3=> Conditional block transfer 2319 // <4=> Channel suspend operation 2320 // <5=> Channel resume operation 2321 // <6=> Skip next block suspend action 2322 // <i> Defines the event input action 2323 // <id> dmac_evact_11 2324 #ifndef CONF_DMAC_EVACT_11 2325 #define CONF_DMAC_EVACT_11 0 2326 #endif 2327 2328 // <o> Address Increment Step Size 2329 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 2330 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 2331 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 2332 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 2333 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 2334 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 2335 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 2336 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 2337 // <i> Defines the address increment step size, applies to source or destination address 2338 // <id> dmac_stepsize_11 2339 #ifndef CONF_DMAC_STEPSIZE_11 2340 #define CONF_DMAC_STEPSIZE_11 0 2341 #endif 2342 2343 // <o> Step Selection 2344 // <0=> Step size settings apply to the destination address 2345 // <1=> Step size settings apply to the source address 2346 // <i> Defines whether source or destination addresses are using the step size settings 2347 // <id> dmac_stepsel_11 2348 #ifndef CONF_DMAC_STEPSEL_11 2349 #define CONF_DMAC_STEPSEL_11 0 2350 #endif 2351 2352 // <q> Source Address Increment 2353 // <i> Indicates whether the source address incrementation is enabled or not 2354 // <id> dmac_srcinc_11 2355 #ifndef CONF_DMAC_SRCINC_11 2356 #define CONF_DMAC_SRCINC_11 0 2357 #endif 2358 2359 // <q> Destination Address Increment 2360 // <i> Indicates whether the destination address incrementation is enabled or not 2361 // <id> dmac_dstinc_11 2362 #ifndef CONF_DMAC_DSTINC_11 2363 #define CONF_DMAC_DSTINC_11 0 2364 #endif 2365 2366 // <o> Beat Size 2367 // <0=> 8-bit bus transfer 2368 // <1=> 16-bit bus transfer 2369 // <2=> 32-bit bus transfer 2370 // <i> Defines the size of one beat 2371 // <id> dmac_beatsize_11 2372 #ifndef CONF_DMAC_BEATSIZE_11 2373 #define CONF_DMAC_BEATSIZE_11 0 2374 #endif 2375 2376 // <o> Block Action 2377 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2378 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2379 // <2=> Channel suspend operation is complete 2380 // <3=> Both channel suspend operation and block interrupt 2381 // <i> Defines the the DMAC should take after a block transfer has completed 2382 // <id> dmac_blockact_11 2383 #ifndef CONF_DMAC_BLOCKACT_11 2384 #define CONF_DMAC_BLOCKACT_11 0 2385 #endif 2386 2387 // <o> Event Output Selection 2388 // <0=> Event generation disabled 2389 // <1=> Event strobe when block transfer complete 2390 // <3=> Event strobe when beat transfer complete 2391 // <i> Defines the event output selection 2392 // <id> dmac_evosel_11 2393 #ifndef CONF_DMAC_EVOSEL_11 2394 #define CONF_DMAC_EVOSEL_11 0 2395 #endif 2396 // </e> 2397 2398 // <e> Channel 12 settings 2399 // <id> dmac_channel_12_settings 2400 #ifndef CONF_DMAC_CHANNEL_12_SETTINGS 2401 #define CONF_DMAC_CHANNEL_12_SETTINGS 0 2402 #endif 2403 2404 // <q> Channel Enable 2405 // <i> Indicates whether channel 12 is enabled or not 2406 // <id> dmac_enable_12 2407 #ifndef CONF_DMAC_ENABLE_12 2408 #define CONF_DMAC_ENABLE_12 0 2409 #endif 2410 2411 // <q> Channel Run in Standby 2412 // <i> Indicates whether channel 12 is running in standby mode or not 2413 // <id> dmac_runstdby_12 2414 #ifndef CONF_DMAC_RUNSTDBY_12 2415 #define CONF_DMAC_RUNSTDBY_12 0 2416 #endif 2417 2418 // <o> Trigger action 2419 // <0=> One trigger required for each block transfer 2420 // <2=> One trigger required for each beat transfer 2421 // <3=> One trigger required for each transaction 2422 // <i> Defines the trigger action used for a transfer 2423 // <id> dmac_trigact_12 2424 #ifndef CONF_DMAC_TRIGACT_12 2425 #define CONF_DMAC_TRIGACT_12 0 2426 #endif 2427 2428 // <o> Trigger source 2429 // <0x00=> Only software/event triggers 2430 // <0x01=> SERCOM0 RX Trigger 2431 // <0x02=> SERCOM0 TX Trigger 2432 // <0x03=> SERCOM1 RX Trigger 2433 // <0x04=> SERCOM1 TX Trigger 2434 // <0x05=> SERCOM2 RX Trigger 2435 // <0x06=> SERCOM2 TX Trigger 2436 // <0x07=> SERCOM3 RX Trigger 2437 // <0x08=> SERCOM3 TX Trigger 2438 // <0x09=> SERCOM4 RX Trigger 2439 // <0x0A=> SERCOM4 TX Trigger 2440 // <0x0B=> TCC0 Overflow Trigger 2441 // <0x0C=> TCC0 Match/Compare 0 Trigger 2442 // <0x0D=> TCC0 Match/Compare 1 Trigger 2443 // <0x0E=> TCC0 Match/Compare 2 Trigger 2444 // <0x0F=> TCC0 Match/Compare 3 Trigger 2445 // <0x10=> TCC1 Overflow Trigger 2446 // <0x11=> TCC1 Match/Compare 0 Trigger 2447 // <0x12=> TCC1 Match/Compare 1 Trigger 2448 // <0x13=> TCC2 Overflow Trigger 2449 // <0x14=> TCC2 Match/Compare 0 Trigger 2450 // <0x15=> TCC2 Match/Compare 1 Trigger 2451 // <0x16=> TC0 Overflow Trigger 2452 // <0x17=> TC0 Match/Compare 0 Trigger 2453 // <0x18=> TC0 Match/Compare 1 Trigger 2454 // <0x19=> TC1 Overflow Trigger 2455 // <0x1A=> TC1 Match/Compare 0 Trigger 2456 // <0x1B=> TC1 Match/Compare 1 Trigger 2457 // <0x1C=> TC2 Overflow Trigger 2458 // <0x1D=> TC2 Match/Compare 0 Trigger 2459 // <0x1E=> TC2 Match/Compare 1 Trigger 2460 // <0x1F=> TC3 Overflow Trigger 2461 // <0x20=> TC3 Match/Compare 0 Trigger 2462 // <0x21=> TC3 Match/Compare 1 Trigger 2463 // <0x22=> TC4 Overflow Trigger 2464 // <0x23=> TC4 Match/Compare 0 Trigger 2465 // <0x24=> TC4 Match/Compare 1 Trigger 2466 // <0x25=> ADC Result Ready Trigger 2467 // <0x26=> DAC0 Empty Trigger 2468 // <0x27=> DAC1 Empty Trigger 2469 // <0x2C=> AES Write Trigger 2470 // <0x2D=> AES Read Trigger 2471 // <i> Defines the peripheral trigger which is source of the transfer 2472 // <id> dmac_trifsrc_12 2473 #ifndef CONF_DMAC_TRIGSRC_12 2474 #define CONF_DMAC_TRIGSRC_12 0 2475 #endif 2476 2477 // <o> Channel Arbitration Level 2478 // <0=> Channel priority 0 2479 // <1=> Channel priority 1 2480 // <2=> Channel priority 2 2481 // <3=> Channel priority 3 2482 // <i> Defines the arbitration level for this channel 2483 // <id> dmac_lvl_12 2484 #ifndef CONF_DMAC_LVL_12 2485 #define CONF_DMAC_LVL_12 0 2486 #endif 2487 2488 // <q> Channel Event Output 2489 // <i> Indicates whether channel event generation is enabled or not 2490 // <id> dmac_evoe_12 2491 #ifndef CONF_DMAC_EVOE_12 2492 #define CONF_DMAC_EVOE_12 0 2493 #endif 2494 2495 // <q> Channel Event Input 2496 // <i> Indicates whether channel event reception is enabled or not 2497 // <id> dmac_evie_12 2498 #ifndef CONF_DMAC_EVIE_12 2499 #define CONF_DMAC_EVIE_12 0 2500 #endif 2501 2502 // <o> Event Input Action 2503 // <0=> No action 2504 // <1=> Normal transfer and conditional transfer on strobe trigger 2505 // <2=> Conditional transfer trigger 2506 // <3=> Conditional block transfer 2507 // <4=> Channel suspend operation 2508 // <5=> Channel resume operation 2509 // <6=> Skip next block suspend action 2510 // <i> Defines the event input action 2511 // <id> dmac_evact_12 2512 #ifndef CONF_DMAC_EVACT_12 2513 #define CONF_DMAC_EVACT_12 0 2514 #endif 2515 2516 // <o> Address Increment Step Size 2517 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 2518 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 2519 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 2520 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 2521 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 2522 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 2523 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 2524 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 2525 // <i> Defines the address increment step size, applies to source or destination address 2526 // <id> dmac_stepsize_12 2527 #ifndef CONF_DMAC_STEPSIZE_12 2528 #define CONF_DMAC_STEPSIZE_12 0 2529 #endif 2530 2531 // <o> Step Selection 2532 // <0=> Step size settings apply to the destination address 2533 // <1=> Step size settings apply to the source address 2534 // <i> Defines whether source or destination addresses are using the step size settings 2535 // <id> dmac_stepsel_12 2536 #ifndef CONF_DMAC_STEPSEL_12 2537 #define CONF_DMAC_STEPSEL_12 0 2538 #endif 2539 2540 // <q> Source Address Increment 2541 // <i> Indicates whether the source address incrementation is enabled or not 2542 // <id> dmac_srcinc_12 2543 #ifndef CONF_DMAC_SRCINC_12 2544 #define CONF_DMAC_SRCINC_12 0 2545 #endif 2546 2547 // <q> Destination Address Increment 2548 // <i> Indicates whether the destination address incrementation is enabled or not 2549 // <id> dmac_dstinc_12 2550 #ifndef CONF_DMAC_DSTINC_12 2551 #define CONF_DMAC_DSTINC_12 0 2552 #endif 2553 2554 // <o> Beat Size 2555 // <0=> 8-bit bus transfer 2556 // <1=> 16-bit bus transfer 2557 // <2=> 32-bit bus transfer 2558 // <i> Defines the size of one beat 2559 // <id> dmac_beatsize_12 2560 #ifndef CONF_DMAC_BEATSIZE_12 2561 #define CONF_DMAC_BEATSIZE_12 0 2562 #endif 2563 2564 // <o> Block Action 2565 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2566 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2567 // <2=> Channel suspend operation is complete 2568 // <3=> Both channel suspend operation and block interrupt 2569 // <i> Defines the the DMAC should take after a block transfer has completed 2570 // <id> dmac_blockact_12 2571 #ifndef CONF_DMAC_BLOCKACT_12 2572 #define CONF_DMAC_BLOCKACT_12 0 2573 #endif 2574 2575 // <o> Event Output Selection 2576 // <0=> Event generation disabled 2577 // <1=> Event strobe when block transfer complete 2578 // <3=> Event strobe when beat transfer complete 2579 // <i> Defines the event output selection 2580 // <id> dmac_evosel_12 2581 #ifndef CONF_DMAC_EVOSEL_12 2582 #define CONF_DMAC_EVOSEL_12 0 2583 #endif 2584 // </e> 2585 2586 // <e> Channel 13 settings 2587 // <id> dmac_channel_13_settings 2588 #ifndef CONF_DMAC_CHANNEL_13_SETTINGS 2589 #define CONF_DMAC_CHANNEL_13_SETTINGS 0 2590 #endif 2591 2592 // <q> Channel Enable 2593 // <i> Indicates whether channel 13 is enabled or not 2594 // <id> dmac_enable_13 2595 #ifndef CONF_DMAC_ENABLE_13 2596 #define CONF_DMAC_ENABLE_13 0 2597 #endif 2598 2599 // <q> Channel Run in Standby 2600 // <i> Indicates whether channel 13 is running in standby mode or not 2601 // <id> dmac_runstdby_13 2602 #ifndef CONF_DMAC_RUNSTDBY_13 2603 #define CONF_DMAC_RUNSTDBY_13 0 2604 #endif 2605 2606 // <o> Trigger action 2607 // <0=> One trigger required for each block transfer 2608 // <2=> One trigger required for each beat transfer 2609 // <3=> One trigger required for each transaction 2610 // <i> Defines the trigger action used for a transfer 2611 // <id> dmac_trigact_13 2612 #ifndef CONF_DMAC_TRIGACT_13 2613 #define CONF_DMAC_TRIGACT_13 0 2614 #endif 2615 2616 // <o> Trigger source 2617 // <0x00=> Only software/event triggers 2618 // <0x01=> SERCOM0 RX Trigger 2619 // <0x02=> SERCOM0 TX Trigger 2620 // <0x03=> SERCOM1 RX Trigger 2621 // <0x04=> SERCOM1 TX Trigger 2622 // <0x05=> SERCOM2 RX Trigger 2623 // <0x06=> SERCOM2 TX Trigger 2624 // <0x07=> SERCOM3 RX Trigger 2625 // <0x08=> SERCOM3 TX Trigger 2626 // <0x09=> SERCOM4 RX Trigger 2627 // <0x0A=> SERCOM4 TX Trigger 2628 // <0x0B=> TCC0 Overflow Trigger 2629 // <0x0C=> TCC0 Match/Compare 0 Trigger 2630 // <0x0D=> TCC0 Match/Compare 1 Trigger 2631 // <0x0E=> TCC0 Match/Compare 2 Trigger 2632 // <0x0F=> TCC0 Match/Compare 3 Trigger 2633 // <0x10=> TCC1 Overflow Trigger 2634 // <0x11=> TCC1 Match/Compare 0 Trigger 2635 // <0x12=> TCC1 Match/Compare 1 Trigger 2636 // <0x13=> TCC2 Overflow Trigger 2637 // <0x14=> TCC2 Match/Compare 0 Trigger 2638 // <0x15=> TCC2 Match/Compare 1 Trigger 2639 // <0x16=> TC0 Overflow Trigger 2640 // <0x17=> TC0 Match/Compare 0 Trigger 2641 // <0x18=> TC0 Match/Compare 1 Trigger 2642 // <0x19=> TC1 Overflow Trigger 2643 // <0x1A=> TC1 Match/Compare 0 Trigger 2644 // <0x1B=> TC1 Match/Compare 1 Trigger 2645 // <0x1C=> TC2 Overflow Trigger 2646 // <0x1D=> TC2 Match/Compare 0 Trigger 2647 // <0x1E=> TC2 Match/Compare 1 Trigger 2648 // <0x1F=> TC3 Overflow Trigger 2649 // <0x20=> TC3 Match/Compare 0 Trigger 2650 // <0x21=> TC3 Match/Compare 1 Trigger 2651 // <0x22=> TC4 Overflow Trigger 2652 // <0x23=> TC4 Match/Compare 0 Trigger 2653 // <0x24=> TC4 Match/Compare 1 Trigger 2654 // <0x25=> ADC Result Ready Trigger 2655 // <0x26=> DAC0 Empty Trigger 2656 // <0x27=> DAC1 Empty Trigger 2657 // <0x2C=> AES Write Trigger 2658 // <0x2D=> AES Read Trigger 2659 // <i> Defines the peripheral trigger which is source of the transfer 2660 // <id> dmac_trifsrc_13 2661 #ifndef CONF_DMAC_TRIGSRC_13 2662 #define CONF_DMAC_TRIGSRC_13 0 2663 #endif 2664 2665 // <o> Channel Arbitration Level 2666 // <0=> Channel priority 0 2667 // <1=> Channel priority 1 2668 // <2=> Channel priority 2 2669 // <3=> Channel priority 3 2670 // <i> Defines the arbitration level for this channel 2671 // <id> dmac_lvl_13 2672 #ifndef CONF_DMAC_LVL_13 2673 #define CONF_DMAC_LVL_13 0 2674 #endif 2675 2676 // <q> Channel Event Output 2677 // <i> Indicates whether channel event generation is enabled or not 2678 // <id> dmac_evoe_13 2679 #ifndef CONF_DMAC_EVOE_13 2680 #define CONF_DMAC_EVOE_13 0 2681 #endif 2682 2683 // <q> Channel Event Input 2684 // <i> Indicates whether channel event reception is enabled or not 2685 // <id> dmac_evie_13 2686 #ifndef CONF_DMAC_EVIE_13 2687 #define CONF_DMAC_EVIE_13 0 2688 #endif 2689 2690 // <o> Event Input Action 2691 // <0=> No action 2692 // <1=> Normal transfer and conditional transfer on strobe trigger 2693 // <2=> Conditional transfer trigger 2694 // <3=> Conditional block transfer 2695 // <4=> Channel suspend operation 2696 // <5=> Channel resume operation 2697 // <6=> Skip next block suspend action 2698 // <i> Defines the event input action 2699 // <id> dmac_evact_13 2700 #ifndef CONF_DMAC_EVACT_13 2701 #define CONF_DMAC_EVACT_13 0 2702 #endif 2703 2704 // <o> Address Increment Step Size 2705 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 2706 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 2707 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 2708 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 2709 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 2710 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 2711 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 2712 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 2713 // <i> Defines the address increment step size, applies to source or destination address 2714 // <id> dmac_stepsize_13 2715 #ifndef CONF_DMAC_STEPSIZE_13 2716 #define CONF_DMAC_STEPSIZE_13 0 2717 #endif 2718 2719 // <o> Step Selection 2720 // <0=> Step size settings apply to the destination address 2721 // <1=> Step size settings apply to the source address 2722 // <i> Defines whether source or destination addresses are using the step size settings 2723 // <id> dmac_stepsel_13 2724 #ifndef CONF_DMAC_STEPSEL_13 2725 #define CONF_DMAC_STEPSEL_13 0 2726 #endif 2727 2728 // <q> Source Address Increment 2729 // <i> Indicates whether the source address incrementation is enabled or not 2730 // <id> dmac_srcinc_13 2731 #ifndef CONF_DMAC_SRCINC_13 2732 #define CONF_DMAC_SRCINC_13 0 2733 #endif 2734 2735 // <q> Destination Address Increment 2736 // <i> Indicates whether the destination address incrementation is enabled or not 2737 // <id> dmac_dstinc_13 2738 #ifndef CONF_DMAC_DSTINC_13 2739 #define CONF_DMAC_DSTINC_13 0 2740 #endif 2741 2742 // <o> Beat Size 2743 // <0=> 8-bit bus transfer 2744 // <1=> 16-bit bus transfer 2745 // <2=> 32-bit bus transfer 2746 // <i> Defines the size of one beat 2747 // <id> dmac_beatsize_13 2748 #ifndef CONF_DMAC_BEATSIZE_13 2749 #define CONF_DMAC_BEATSIZE_13 0 2750 #endif 2751 2752 // <o> Block Action 2753 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2754 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2755 // <2=> Channel suspend operation is complete 2756 // <3=> Both channel suspend operation and block interrupt 2757 // <i> Defines the the DMAC should take after a block transfer has completed 2758 // <id> dmac_blockact_13 2759 #ifndef CONF_DMAC_BLOCKACT_13 2760 #define CONF_DMAC_BLOCKACT_13 0 2761 #endif 2762 2763 // <o> Event Output Selection 2764 // <0=> Event generation disabled 2765 // <1=> Event strobe when block transfer complete 2766 // <3=> Event strobe when beat transfer complete 2767 // <i> Defines the event output selection 2768 // <id> dmac_evosel_13 2769 #ifndef CONF_DMAC_EVOSEL_13 2770 #define CONF_DMAC_EVOSEL_13 0 2771 #endif 2772 // </e> 2773 2774 // <e> Channel 14 settings 2775 // <id> dmac_channel_14_settings 2776 #ifndef CONF_DMAC_CHANNEL_14_SETTINGS 2777 #define CONF_DMAC_CHANNEL_14_SETTINGS 0 2778 #endif 2779 2780 // <q> Channel Enable 2781 // <i> Indicates whether channel 14 is enabled or not 2782 // <id> dmac_enable_14 2783 #ifndef CONF_DMAC_ENABLE_14 2784 #define CONF_DMAC_ENABLE_14 0 2785 #endif 2786 2787 // <q> Channel Run in Standby 2788 // <i> Indicates whether channel 14 is running in standby mode or not 2789 // <id> dmac_runstdby_14 2790 #ifndef CONF_DMAC_RUNSTDBY_14 2791 #define CONF_DMAC_RUNSTDBY_14 0 2792 #endif 2793 2794 // <o> Trigger action 2795 // <0=> One trigger required for each block transfer 2796 // <2=> One trigger required for each beat transfer 2797 // <3=> One trigger required for each transaction 2798 // <i> Defines the trigger action used for a transfer 2799 // <id> dmac_trigact_14 2800 #ifndef CONF_DMAC_TRIGACT_14 2801 #define CONF_DMAC_TRIGACT_14 0 2802 #endif 2803 2804 // <o> Trigger source 2805 // <0x00=> Only software/event triggers 2806 // <0x01=> SERCOM0 RX Trigger 2807 // <0x02=> SERCOM0 TX Trigger 2808 // <0x03=> SERCOM1 RX Trigger 2809 // <0x04=> SERCOM1 TX Trigger 2810 // <0x05=> SERCOM2 RX Trigger 2811 // <0x06=> SERCOM2 TX Trigger 2812 // <0x07=> SERCOM3 RX Trigger 2813 // <0x08=> SERCOM3 TX Trigger 2814 // <0x09=> SERCOM4 RX Trigger 2815 // <0x0A=> SERCOM4 TX Trigger 2816 // <0x0B=> TCC0 Overflow Trigger 2817 // <0x0C=> TCC0 Match/Compare 0 Trigger 2818 // <0x0D=> TCC0 Match/Compare 1 Trigger 2819 // <0x0E=> TCC0 Match/Compare 2 Trigger 2820 // <0x0F=> TCC0 Match/Compare 3 Trigger 2821 // <0x10=> TCC1 Overflow Trigger 2822 // <0x11=> TCC1 Match/Compare 0 Trigger 2823 // <0x12=> TCC1 Match/Compare 1 Trigger 2824 // <0x13=> TCC2 Overflow Trigger 2825 // <0x14=> TCC2 Match/Compare 0 Trigger 2826 // <0x15=> TCC2 Match/Compare 1 Trigger 2827 // <0x16=> TC0 Overflow Trigger 2828 // <0x17=> TC0 Match/Compare 0 Trigger 2829 // <0x18=> TC0 Match/Compare 1 Trigger 2830 // <0x19=> TC1 Overflow Trigger 2831 // <0x1A=> TC1 Match/Compare 0 Trigger 2832 // <0x1B=> TC1 Match/Compare 1 Trigger 2833 // <0x1C=> TC2 Overflow Trigger 2834 // <0x1D=> TC2 Match/Compare 0 Trigger 2835 // <0x1E=> TC2 Match/Compare 1 Trigger 2836 // <0x1F=> TC3 Overflow Trigger 2837 // <0x20=> TC3 Match/Compare 0 Trigger 2838 // <0x21=> TC3 Match/Compare 1 Trigger 2839 // <0x22=> TC4 Overflow Trigger 2840 // <0x23=> TC4 Match/Compare 0 Trigger 2841 // <0x24=> TC4 Match/Compare 1 Trigger 2842 // <0x25=> ADC Result Ready Trigger 2843 // <0x26=> DAC0 Empty Trigger 2844 // <0x27=> DAC1 Empty Trigger 2845 // <0x2C=> AES Write Trigger 2846 // <0x2D=> AES Read Trigger 2847 // <i> Defines the peripheral trigger which is source of the transfer 2848 // <id> dmac_trifsrc_14 2849 #ifndef CONF_DMAC_TRIGSRC_14 2850 #define CONF_DMAC_TRIGSRC_14 0 2851 #endif 2852 2853 // <o> Channel Arbitration Level 2854 // <0=> Channel priority 0 2855 // <1=> Channel priority 1 2856 // <2=> Channel priority 2 2857 // <3=> Channel priority 3 2858 // <i> Defines the arbitration level for this channel 2859 // <id> dmac_lvl_14 2860 #ifndef CONF_DMAC_LVL_14 2861 #define CONF_DMAC_LVL_14 0 2862 #endif 2863 2864 // <q> Channel Event Output 2865 // <i> Indicates whether channel event generation is enabled or not 2866 // <id> dmac_evoe_14 2867 #ifndef CONF_DMAC_EVOE_14 2868 #define CONF_DMAC_EVOE_14 0 2869 #endif 2870 2871 // <q> Channel Event Input 2872 // <i> Indicates whether channel event reception is enabled or not 2873 // <id> dmac_evie_14 2874 #ifndef CONF_DMAC_EVIE_14 2875 #define CONF_DMAC_EVIE_14 0 2876 #endif 2877 2878 // <o> Event Input Action 2879 // <0=> No action 2880 // <1=> Normal transfer and conditional transfer on strobe trigger 2881 // <2=> Conditional transfer trigger 2882 // <3=> Conditional block transfer 2883 // <4=> Channel suspend operation 2884 // <5=> Channel resume operation 2885 // <6=> Skip next block suspend action 2886 // <i> Defines the event input action 2887 // <id> dmac_evact_14 2888 #ifndef CONF_DMAC_EVACT_14 2889 #define CONF_DMAC_EVACT_14 0 2890 #endif 2891 2892 // <o> Address Increment Step Size 2893 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 2894 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 2895 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 2896 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 2897 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 2898 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 2899 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 2900 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 2901 // <i> Defines the address increment step size, applies to source or destination address 2902 // <id> dmac_stepsize_14 2903 #ifndef CONF_DMAC_STEPSIZE_14 2904 #define CONF_DMAC_STEPSIZE_14 0 2905 #endif 2906 2907 // <o> Step Selection 2908 // <0=> Step size settings apply to the destination address 2909 // <1=> Step size settings apply to the source address 2910 // <i> Defines whether source or destination addresses are using the step size settings 2911 // <id> dmac_stepsel_14 2912 #ifndef CONF_DMAC_STEPSEL_14 2913 #define CONF_DMAC_STEPSEL_14 0 2914 #endif 2915 2916 // <q> Source Address Increment 2917 // <i> Indicates whether the source address incrementation is enabled or not 2918 // <id> dmac_srcinc_14 2919 #ifndef CONF_DMAC_SRCINC_14 2920 #define CONF_DMAC_SRCINC_14 0 2921 #endif 2922 2923 // <q> Destination Address Increment 2924 // <i> Indicates whether the destination address incrementation is enabled or not 2925 // <id> dmac_dstinc_14 2926 #ifndef CONF_DMAC_DSTINC_14 2927 #define CONF_DMAC_DSTINC_14 0 2928 #endif 2929 2930 // <o> Beat Size 2931 // <0=> 8-bit bus transfer 2932 // <1=> 16-bit bus transfer 2933 // <2=> 32-bit bus transfer 2934 // <i> Defines the size of one beat 2935 // <id> dmac_beatsize_14 2936 #ifndef CONF_DMAC_BEATSIZE_14 2937 #define CONF_DMAC_BEATSIZE_14 0 2938 #endif 2939 2940 // <o> Block Action 2941 // <0=> Channel will be disabled if it is the last block transfer in the transaction 2942 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 2943 // <2=> Channel suspend operation is complete 2944 // <3=> Both channel suspend operation and block interrupt 2945 // <i> Defines the the DMAC should take after a block transfer has completed 2946 // <id> dmac_blockact_14 2947 #ifndef CONF_DMAC_BLOCKACT_14 2948 #define CONF_DMAC_BLOCKACT_14 0 2949 #endif 2950 2951 // <o> Event Output Selection 2952 // <0=> Event generation disabled 2953 // <1=> Event strobe when block transfer complete 2954 // <3=> Event strobe when beat transfer complete 2955 // <i> Defines the event output selection 2956 // <id> dmac_evosel_14 2957 #ifndef CONF_DMAC_EVOSEL_14 2958 #define CONF_DMAC_EVOSEL_14 0 2959 #endif 2960 // </e> 2961 2962 // <e> Channel 15 settings 2963 // <id> dmac_channel_15_settings 2964 #ifndef CONF_DMAC_CHANNEL_15_SETTINGS 2965 #define CONF_DMAC_CHANNEL_15_SETTINGS 0 2966 #endif 2967 2968 // <q> Channel Enable 2969 // <i> Indicates whether channel 15 is enabled or not 2970 // <id> dmac_enable_15 2971 #ifndef CONF_DMAC_ENABLE_15 2972 #define CONF_DMAC_ENABLE_15 0 2973 #endif 2974 2975 // <q> Channel Run in Standby 2976 // <i> Indicates whether channel 15 is running in standby mode or not 2977 // <id> dmac_runstdby_15 2978 #ifndef CONF_DMAC_RUNSTDBY_15 2979 #define CONF_DMAC_RUNSTDBY_15 0 2980 #endif 2981 2982 // <o> Trigger action 2983 // <0=> One trigger required for each block transfer 2984 // <2=> One trigger required for each beat transfer 2985 // <3=> One trigger required for each transaction 2986 // <i> Defines the trigger action used for a transfer 2987 // <id> dmac_trigact_15 2988 #ifndef CONF_DMAC_TRIGACT_15 2989 #define CONF_DMAC_TRIGACT_15 0 2990 #endif 2991 2992 // <o> Trigger source 2993 // <0x00=> Only software/event triggers 2994 // <0x01=> SERCOM0 RX Trigger 2995 // <0x02=> SERCOM0 TX Trigger 2996 // <0x03=> SERCOM1 RX Trigger 2997 // <0x04=> SERCOM1 TX Trigger 2998 // <0x05=> SERCOM2 RX Trigger 2999 // <0x06=> SERCOM2 TX Trigger 3000 // <0x07=> SERCOM3 RX Trigger 3001 // <0x08=> SERCOM3 TX Trigger 3002 // <0x09=> SERCOM4 RX Trigger 3003 // <0x0A=> SERCOM4 TX Trigger 3004 // <0x0B=> TCC0 Overflow Trigger 3005 // <0x0C=> TCC0 Match/Compare 0 Trigger 3006 // <0x0D=> TCC0 Match/Compare 1 Trigger 3007 // <0x0E=> TCC0 Match/Compare 2 Trigger 3008 // <0x0F=> TCC0 Match/Compare 3 Trigger 3009 // <0x10=> TCC1 Overflow Trigger 3010 // <0x11=> TCC1 Match/Compare 0 Trigger 3011 // <0x12=> TCC1 Match/Compare 1 Trigger 3012 // <0x13=> TCC2 Overflow Trigger 3013 // <0x14=> TCC2 Match/Compare 0 Trigger 3014 // <0x15=> TCC2 Match/Compare 1 Trigger 3015 // <0x16=> TC0 Overflow Trigger 3016 // <0x17=> TC0 Match/Compare 0 Trigger 3017 // <0x18=> TC0 Match/Compare 1 Trigger 3018 // <0x19=> TC1 Overflow Trigger 3019 // <0x1A=> TC1 Match/Compare 0 Trigger 3020 // <0x1B=> TC1 Match/Compare 1 Trigger 3021 // <0x1C=> TC2 Overflow Trigger 3022 // <0x1D=> TC2 Match/Compare 0 Trigger 3023 // <0x1E=> TC2 Match/Compare 1 Trigger 3024 // <0x1F=> TC3 Overflow Trigger 3025 // <0x20=> TC3 Match/Compare 0 Trigger 3026 // <0x21=> TC3 Match/Compare 1 Trigger 3027 // <0x22=> TC4 Overflow Trigger 3028 // <0x23=> TC4 Match/Compare 0 Trigger 3029 // <0x24=> TC4 Match/Compare 1 Trigger 3030 // <0x25=> ADC Result Ready Trigger 3031 // <0x26=> DAC0 Empty Trigger 3032 // <0x27=> DAC1 Empty Trigger 3033 // <0x2C=> AES Write Trigger 3034 // <0x2D=> AES Read Trigger 3035 // <i> Defines the peripheral trigger which is source of the transfer 3036 // <id> dmac_trifsrc_15 3037 #ifndef CONF_DMAC_TRIGSRC_15 3038 #define CONF_DMAC_TRIGSRC_15 0 3039 #endif 3040 3041 // <o> Channel Arbitration Level 3042 // <0=> Channel priority 0 3043 // <1=> Channel priority 1 3044 // <2=> Channel priority 2 3045 // <3=> Channel priority 3 3046 // <i> Defines the arbitration level for this channel 3047 // <id> dmac_lvl_15 3048 #ifndef CONF_DMAC_LVL_15 3049 #define CONF_DMAC_LVL_15 0 3050 #endif 3051 3052 // <q> Channel Event Output 3053 // <i> Indicates whether channel event generation is enabled or not 3054 // <id> dmac_evoe_15 3055 #ifndef CONF_DMAC_EVOE_15 3056 #define CONF_DMAC_EVOE_15 0 3057 #endif 3058 3059 // <q> Channel Event Input 3060 // <i> Indicates whether channel event reception is enabled or not 3061 // <id> dmac_evie_15 3062 #ifndef CONF_DMAC_EVIE_15 3063 #define CONF_DMAC_EVIE_15 0 3064 #endif 3065 3066 // <o> Event Input Action 3067 // <0=> No action 3068 // <1=> Normal transfer and conditional transfer on strobe trigger 3069 // <2=> Conditional transfer trigger 3070 // <3=> Conditional block transfer 3071 // <4=> Channel suspend operation 3072 // <5=> Channel resume operation 3073 // <6=> Skip next block suspend action 3074 // <i> Defines the event input action 3075 // <id> dmac_evact_15 3076 #ifndef CONF_DMAC_EVACT_15 3077 #define CONF_DMAC_EVACT_15 0 3078 #endif 3079 3080 // <o> Address Increment Step Size 3081 // <0=> Next ADDR = ADDR + (BEATSIZE + 1) * 1 3082 // <1=> Next ADDR = ADDR + (BEATSIZE + 1) * 2 3083 // <2=> Next ADDR = ADDR + (BEATSIZE + 1) * 4 3084 // <3=> Next ADDR = ADDR + (BEATSIZE + 1) * 8 3085 // <4=> Next ADDR = ADDR + (BEATSIZE + 1) * 16 3086 // <5=> Next ADDR = ADDR + (BEATSIZE + 1) * 32 3087 // <6=> Next ADDR = ADDR + (BEATSIZE + 1) * 64 3088 // <7=> Next ADDR = ADDR + (BEATSIZE + 1) * 128 3089 // <i> Defines the address increment step size, applies to source or destination address 3090 // <id> dmac_stepsize_15 3091 #ifndef CONF_DMAC_STEPSIZE_15 3092 #define CONF_DMAC_STEPSIZE_15 0 3093 #endif 3094 3095 // <o> Step Selection 3096 // <0=> Step size settings apply to the destination address 3097 // <1=> Step size settings apply to the source address 3098 // <i> Defines whether source or destination addresses are using the step size settings 3099 // <id> dmac_stepsel_15 3100 #ifndef CONF_DMAC_STEPSEL_15 3101 #define CONF_DMAC_STEPSEL_15 0 3102 #endif 3103 3104 // <q> Source Address Increment 3105 // <i> Indicates whether the source address incrementation is enabled or not 3106 // <id> dmac_srcinc_15 3107 #ifndef CONF_DMAC_SRCINC_15 3108 #define CONF_DMAC_SRCINC_15 0 3109 #endif 3110 3111 // <q> Destination Address Increment 3112 // <i> Indicates whether the destination address incrementation is enabled or not 3113 // <id> dmac_dstinc_15 3114 #ifndef CONF_DMAC_DSTINC_15 3115 #define CONF_DMAC_DSTINC_15 0 3116 #endif 3117 3118 // <o> Beat Size 3119 // <0=> 8-bit bus transfer 3120 // <1=> 16-bit bus transfer 3121 // <2=> 32-bit bus transfer 3122 // <i> Defines the size of one beat 3123 // <id> dmac_beatsize_15 3124 #ifndef CONF_DMAC_BEATSIZE_15 3125 #define CONF_DMAC_BEATSIZE_15 0 3126 #endif 3127 3128 // <o> Block Action 3129 // <0=> Channel will be disabled if it is the last block transfer in the transaction 3130 // <1=> Channel will be disabled if it is the last block transfer in the transaction and block interrupt 3131 // <2=> Channel suspend operation is complete 3132 // <3=> Both channel suspend operation and block interrupt 3133 // <i> Defines the the DMAC should take after a block transfer has completed 3134 // <id> dmac_blockact_15 3135 #ifndef CONF_DMAC_BLOCKACT_15 3136 #define CONF_DMAC_BLOCKACT_15 0 3137 #endif 3138 3139 // <o> Event Output Selection 3140 // <0=> Event generation disabled 3141 // <1=> Event strobe when block transfer complete 3142 // <3=> Event strobe when beat transfer complete 3143 // <i> Defines the event output selection 3144 // <id> dmac_evosel_15 3145 #ifndef CONF_DMAC_EVOSEL_15 3146 #define CONF_DMAC_EVOSEL_15 0 3147 #endif 3148 // </e> 3149 3150 // </e> 3151 3152 // <<< end of configuration section >>> 3153 3154 #endif // HPL_DMAC_CONFIG_H 3155
