1 /* Auto-generated config file hpl_oscctrl_config.h */ 2 #ifndef HPL_OSCCTRL_CONFIG_H 3 #define HPL_OSCCTRL_CONFIG_H 4 5 // <<< Use Configuration Wizard in Context Menu >>> 6 7 // <e> External Multipurpose Crystal Oscillator Configuration 8 // <i> Indicates whether configuration for XOSC is enabled or not 9 // <id> enable_xosc 10 #ifndef CONF_XOSC_CONFIG 11 #define CONF_XOSC_CONFIG 0 12 #endif 13 14 // <o> Frequency <400000-32000000> 15 // <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator. 16 // <id> xosc_frequency 17 #ifndef CONF_XOSC_FREQUENCY 18 #define CONF_XOSC_FREQUENCY 400000 19 #endif 20 21 // <h> External Multipurpose Crystal Oscillator Control 22 // <q> Oscillator enable 23 // <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not 24 // <id> xosc_arch_enable 25 #ifndef CONF_XOSC_ENABLE 26 #define CONF_XOSC_ENABLE 0 27 #endif 28 29 // <o> Start-Up Time 30 // <0x0=>31us 31 // <0x1=>61us 32 // <0x2=>122us 33 // <0x3=>244us 34 // <0x4=>488us 35 // <0x5=>977us 36 // <0x6=>1953us 37 // <0x7=>3906us 38 // <0x8=>7813us 39 // <0x9=>15625us 40 // <0xA=>31250us 41 // <0xB=>62500us 42 // <0xC=>125000us 43 // <0xD=>250000us 44 // <0xE=>500000us 45 // <0xF=>1000000us 46 // <id> xosc_arch_startup 47 #ifndef CONF_XOSC_STARTUP 48 #define CONF_XOSC_STARTUP 0x0 49 #endif 50 51 // <q> Automatic Amplitude Gain Control 52 // <i> Indicates whether Automatic Amplitude Gain Control is enabled or not 53 // <id> xosc_arch_ampgc 54 #ifndef CONF_XOSC_AMPGC 55 #define CONF_XOSC_AMPGC 0 56 #endif 57 58 // <o> External Multipurpose Crystal Oscillator Gain 59 // <0x0=>2MHz 60 // <0x1=>4MHz 61 // <0x2=>8MHz 62 // <0x3=>16MHz 63 // <0x4=>30MHz 64 // <id> xosc_arch_gain 65 #ifndef CONF_XOSC_GAIN 66 #define CONF_XOSC_GAIN 0x0 67 #endif 68 69 // <q> On Demand Control 70 // <i> Indicates whether On Demand Control is enabled or not 71 // <id> xosc_arch_ondemand 72 #ifndef CONF_XOSC_ONDEMAND 73 #define CONF_XOSC_ONDEMAND 1 74 #endif 75 76 // <q> Run in Standby 77 // <i> Indicates whether Run in Standby is enabled or not 78 // <id> xosc_arch_runstdby 79 #ifndef CONF_XOSC_RUNSTDBY 80 #define CONF_XOSC_RUNSTDBY 0 81 #endif 82 83 // <q> Crystal connected to XIN/XOUT Enable 84 // <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not 85 // <id> xosc_arch_xtalen 86 #ifndef CONF_XOSC_XTALEN 87 #define CONF_XOSC_XTALEN 0 88 #endif 89 //</h> 90 //</e> 91 92 // <e> 16MHz Internal Oscillator Configuration 93 // <i> Indicates whether configuration for OSC8M is enabled or not 94 // <id> enable_osc16m 95 #ifndef CONF_OSC16M_CONFIG 96 #define CONF_OSC16M_CONFIG 1 97 #endif 98 99 // <h> 16MHz Internal Oscillator Control 100 // <q> Enable 101 // <i> Indicates whether 16MHz Internal Oscillator is enabled or not 102 // <id> osc16m_arch_enable 103 #ifndef CONF_OSC16M_ENABLE 104 #define CONF_OSC16M_ENABLE 1 105 #endif 106 107 // <q> On Demand Control 108 // <i> Indicates whether On Demand Control is enabled or not 109 // <id> osc16m_arch_ondemand 110 #ifndef CONF_OSC16M_ONDEMAND 111 #define CONF_OSC16M_ONDEMAND 1 112 #endif 113 114 // <q> Run in Standby 115 // <i> Indicates whether Run in Standby is enabled or not 116 // <id> osc16m_arch_runstdby 117 #ifndef CONF_OSC16M_RUNSTDBY 118 #define CONF_OSC16M_RUNSTDBY 0 119 #endif 120 121 // <y> Oscillator Frequency Selection(Mhz) 122 // <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4 123 // <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8 124 // <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12 125 // <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16 126 // <i> This defines the oscillator frequency (Mhz) 127 // <id> osc16m_freq 128 #ifndef CONF_OSC16M_FSEL 129 #define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_16_Val 130 #endif 131 132 // <q> Oscillator Calibration Control 133 // <i> Indicates whether Oscillator Calibration is enabled or not 134 // <id> osc16m_arch_calib_enable 135 #ifndef CONF_OSC16M_CALIB_ENABLE 136 #define CONF_OSC16M_CALIB_ENABLE 0 137 #endif 138 139 // <o> 4MHz Frequency Calibration <0x0-0x3F> 140 // <id> osc16m_arch_4m_fcal 141 #ifndef CONF_OSC16M_FCAL 142 #define CONF_OSC16M_4M_FCAL 0 143 #endif 144 145 // <o> 4MHz Temperature Calibration <0x0-0x3F> 146 // <id> osc16m_arch_4m_tcal 147 #ifndef CONF_OSC16M_TCAL 148 #define CONF_OSC16M_4M_TCAL 0 149 #endif 150 151 // <o> 8MHz Frequency Calibration <0x0-0x3F> 152 // <id> osc16m_arch_8m_fcal 153 #ifndef CONF_OSC16M_FCAL 154 #define CONF_OSC16M_8M_FCAL 0 155 #endif 156 157 // <o> 8MHz Temperature Calibration <0x0-0x3F> 158 // <id> osc16m_arch_8m_tcal 159 #ifndef CONF_OSC16M_TCAL 160 #define CONF_OSC16M_8M_TCAL 0 161 #endif 162 163 // <o> 12MHz Frequency Calibration <0x0-0x3F> 164 // <id> osc16m_arch_12m_fcal 165 #ifndef CONF_OSC16M_FCAL 166 #define CONF_OSC16M_12M_FCAL 0 167 #endif 168 169 // <o> 12MHz Temperature Calibration <0x0-0x3F> 170 // <id> osc16m_arch_12m_tcal 171 #ifndef CONF_OSC16M_TCAL 172 #define CONF_OSC16M_12M_TCAL 0 173 #endif 174 175 // <o> 16MHz Frequency Calibration <0x0-0x3F> 176 // <id> osc16m_arch_fcal 177 #ifndef CONF_OSC16M_FCAL 178 #define CONF_OSC16M_16M_FCAL 0 179 #endif 180 181 // <o> 16MHz Temperature Calibration <0x0-0x3F> 182 // <id> osc16m_arch_16m_tcal 183 #ifndef CONF_OSC16M_TCAL 184 #define CONF_OSC16M_16M_TCAL 0 185 #endif 186 //</h> 187 //</e> 188 189 // <e> DFLL Configuration 190 // <i> Indicates whether configuration for DFLL is enabled or not 191 // <id> enable_dfll48m 192 #ifndef CONF_DFLL_CONFIG 193 #define CONF_DFLL_CONFIG 0 194 #endif 195 196 // <y> Reference Clock Source 197 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 198 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 199 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 200 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 201 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 202 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 203 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 204 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 205 // <i> Select the clock source. 206 // <id> dfll48m_ref_clock 207 #ifndef CONF_DFLL_GCLK 208 #define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val 209 #endif 210 211 // <h> Digital Frequency Locked Loop Control 212 // <q> DFLL Enable 213 // <i> Indicates whether DFLL is enabled or not 214 // <id> dfll48m_arch_enable 215 #ifndef CONF_DFLL_ENABLE 216 #define CONF_DFLL_ENABLE 0 217 #endif 218 219 // <q> Wait Lock 220 // <i> Indicates whether Wait Lock is enabled or not 221 // <id> dfll_arch_waitlock 222 #ifndef CONF_DFLL_WAITLOCK 223 #define CONF_DFLL_WAITLOCK 0 224 #endif 225 226 // <q> Bypass Coarse Lock 227 // <i> Indicates whether Bypass Coarse Lock is enabled or not 228 // <id> dfll_arch_bplckc 229 #ifndef CONF_DFLL_BPLCKC 230 #define CONF_DFLL_BPLCKC 0 231 #endif 232 233 // <q> Quick Lock Disable 234 // <i> Indicates whether Quick Lock Disable is enabled or not 235 // <id> dfll_arch_qldis 236 #ifndef CONF_DFLL_QLDIS 237 #define CONF_DFLL_QLDIS 0 238 #endif 239 240 // <q> Chill Cycle Disable 241 // <i> Indicates whether Chill Cycle Disable is enabled or not 242 // <id> dfll_arch_ccdis 243 #ifndef CONF_DFLL_CCDIS 244 #define CONF_DFLL_CCDIS 0 245 #endif 246 247 // <q> On Demand Control 248 // <i> Indicates whether On Demand Control is enabled or not 249 // <id> dfll_arch_ondemand 250 #ifndef CONF_DFLL_ONDEMAND 251 #define CONF_DFLL_ONDEMAND 1 252 #endif 253 254 // <q> Run in Standby 255 // <i> Indicates whether Run in Standby is enabled or not 256 // <id> dfll_arch_runstdby 257 #ifndef CONF_DFLL_RUNSTDBY 258 #define CONF_DFLL_RUNSTDBY 0 259 #endif 260 261 // <q> USB Clock Recovery Mode 262 // <i> Indicates whether USB Clock Recovery Mode is enabled or not 263 // <id> dfll_arch_usbcrm 264 #ifndef CONF_DFLL_USBCRM 265 #define CONF_DFLL_USBCRM 0 266 #endif 267 268 // <q> Lose Lock After Wake 269 // <i> Indicates whether Lose Lock After Wake is enabled or not 270 // <id> dfll_arch_llaw 271 #ifndef CONF_DFLL_LLAW 272 #define CONF_DFLL_LLAW 0 273 #endif 274 275 // <q> Stable DFLL Frequency 276 // <i> Indicates whether Stable DFLL Frequency is enabled or not 277 // <id> dfll_arch_stable 278 #ifndef CONF_DFLL_STABLE 279 #define CONF_DFLL_STABLE 0 280 #endif 281 282 // <o> Operating Mode Selection 283 // <0=>Open Loop Mode 284 // <1=>Closed Loop Mode 285 // <id> dfll48m_mode 286 #ifndef CONF_DFLL_MODE 287 #define CONF_DFLL_MODE 0 288 #endif 289 290 // <o> Coarse Maximum Step <0x0-0x1F> 291 // <id> dfll_arch_cstep 292 #ifndef CONF_DFLL_CSTEP 293 #define CONF_DFLL_CSTEP 1 294 #endif 295 296 // <o> Fine Maximum Step <0x0-0x3FF> 297 // <id> dfll_arch_fstep 298 #ifndef CONF_DFLL_FSTEP 299 #define CONF_DFLL_FSTEP 1 300 #endif 301 302 // <o> DFLL Multiply Factor <0x0-0xFFFF> 303 // <id> dfll48m_mul 304 #ifndef CONF_DFLL_MUL 305 #define CONF_DFLL_MUL 0 306 #endif 307 308 // <e> DFLL Calibration Overwrite 309 // <i> Indicates whether Overwrite Calibration value of DFLL 310 // <id> dfll_arch_calibration 311 #ifndef CONF_DFLL_OVERWRITE_CALIBRATION 312 #define CONF_DFLL_OVERWRITE_CALIBRATION 0 313 #endif 314 315 // <o> Coarse Value <0x0-0x3F> 316 // <id> dfll_arch_coarse 317 #ifndef CONF_DFLL_COARSE 318 #define CONF_DFLL_COARSE (0x1f / 4) 319 #endif 320 321 // <o> Fine Value <0x0-0x3FF> 322 // <id> dfll_arch_fine 323 #ifndef CONF_DFLL_FINE 324 #define CONF_DFLL_FINE (0x200) 325 #endif 326 327 //</e> 328 329 //</h> 330 331 //</e> 332 333 // <e> DPLL Configuration 334 // <i> Indicates whether configuration for DPLL is enabled or not 335 // <id> enable_fdpll96m 336 #ifndef CONF_DPLL_CONFIG 337 #define CONF_DPLL_CONFIG 0 338 #endif 339 340 // <y> Reference Clock Source 341 // <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K) 342 // <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC) 343 // <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0 344 // <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1 345 // <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2 346 // <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3 347 // <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4 348 // <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5 349 // <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6 350 // <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7 351 // <i> Select the clock source. 352 // <id> fdpll96m_ref_clock 353 #ifndef CONF_DPLL_GCLK 354 #define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K 355 356 #endif 357 358 // <h> Digital Phase Locked Loop Control 359 // <q> Enable 360 // <i> Indicates whether Digital Phase Locked Loop is enabled or not 361 // <id> fdpll96m_arch_enable 362 #ifndef CONF_DPLL_ENABLE 363 #define CONF_DPLL_ENABLE 0 364 #endif 365 366 // <q> On Demand Control 367 // <i> Indicates whether On Demand Control is enabled or not 368 // <id> fdpll96m_arch_ondemand 369 #ifndef CONF_DPLL_ONDEMAND 370 #define CONF_DPLL_ONDEMAND 1 371 #endif 372 373 // <q> Run in Standby 374 // <i> Indicates whether Run in Standby is enabled or not 375 // <id> fdpll96m_arch_runstdby 376 #ifndef CONF_DPLL_RUNSTDBY 377 #define CONF_DPLL_RUNSTDBY 0 378 #endif 379 380 // <o> Loop Divider Ratio Fractional Part <0x0-0xF> 381 // <id> fdpll96m_ldrfrac 382 #ifndef CONF_DPLL_LDRFRAC 383 #define CONF_DPLL_LDRFRAC 0xd 384 #endif 385 386 // <o> Loop Divider Ratio Integer Part <0x0-0xFFF> 387 // <id> fdpll96m_ldr 388 #ifndef CONF_DPLL_LDR 389 #define CONF_DPLL_LDR 0x5b7 390 #endif 391 392 // <o> Clock Divider <0x0-0x3FF> 393 // <id> fdpll96m_clock_div 394 #ifndef CONF_DPLL_DIV 395 #define CONF_DPLL_DIV 0 396 #endif 397 398 // <q> Lock Bypass 399 // <i> Indicates whether Lock Bypass is enabled or not 400 // <id> fdpll96m_arch_lbypass 401 #ifndef CONF_DPLL_LBYPASS 402 #define CONF_DPLL_LBYPASS 0 403 #endif 404 405 // <o> Lock Time 406 // <0=>No time-out, automatic lock 407 // <4=>The Time-out if no lock within 8 ms 408 // <5=>The Time-out if no lock within 9 ms 409 // <6=>The Time-out if no lock within 10 ms 410 // <7=>The Time-out if no lock within 11 ms 411 // <id> fdpll96m_arch_ltime 412 #ifndef CONF_DPLL_LTIME 413 #define CONF_DPLL_LTIME 0 414 #endif 415 416 // <o> Reference Clock Selection 417 // <0=>XOSC32K clock reference 418 // <1=>XOSC clock reference 419 // <2=>GCLK clock reference 420 // <id> fdpll96m_arch_refclk 421 #ifndef CONF_DPLL_REFCLK 422 #define CONF_DPLL_REFCLK 0 423 #endif 424 425 // <q> Wake Up Fast 426 // <i> Indicates whether Wake Up Fast is enabled or not 427 // <id> fdpll96m_arch_wuf 428 #ifndef CONF_DPLL_WUF 429 #define CONF_DPLL_WUF 0 430 #endif 431 432 // <q> Low-Power Enable 433 // <i> Indicates whether Low-Power Enable is enabled or not 434 // <id> fdpll96m_arch_lpen 435 #ifndef CONF_DPLL_LPEN 436 #define CONF_DPLL_LPEN 0 437 #endif 438 439 // <o> Reference Clock Selection 440 // <0=>Default filter mode 441 // <1=>Low bandwidth filter 442 // <2=>High bandwidth filter 443 // <3=>High damping filter 444 // <id> fdpll96m_arch_filter 445 #ifndef CONF_DPLL_FILTER 446 #define CONF_DPLL_FILTER 0 447 #endif 448 449 // <y> Output Clock Prescaler 450 // <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1 451 // <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2 452 // <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4 453 // <id> fdpll96m_presc 454 #ifndef CONF_DPLL_PRESC 455 #define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val 456 #endif 457 //</h> 458 //</e> 459 460 // <<< end of configuration section >>> 461 462 #endif // HPL_OSCCTRL_CONFIG_H 463
