1# ARM Cortex-M platform configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6# NOTE: We have the specific core implementations first and outside of the 7# if CPU_CORTEX_M block so that SoCs can select which core they are using 8# without having to select all the options related to that core. Everything 9# else is captured inside the if CPU_CORTEX_M block so they are not exposed 10# if one select a differnet ARM Cortex Family (Cortex-A or Cortex-R) 11 12config CPU_CORTEX_M0 13 bool 14 select CPU_CORTEX_M 15 select ARMV6_M_ARMV8_M_BASELINE 16 help 17 This option signifies the use of a Cortex-M0 CPU 18 19config CPU_CORTEX_M0PLUS 20 bool 21 select CPU_CORTEX_M 22 select ARMV6_M_ARMV8_M_BASELINE 23 help 24 This option signifies the use of a Cortex-M0+ CPU 25 26config CPU_CORTEX_M1 27 bool 28 select CPU_CORTEX_M 29 select ARMV6_M_ARMV8_M_BASELINE 30 help 31 This option signifies the use of a Cortex-M1 CPU 32 33config CPU_CORTEX_M3 34 bool 35 select CPU_CORTEX_M 36 select ARMV7_M_ARMV8_M_MAINLINE 37 help 38 This option signifies the use of a Cortex-M3 CPU 39 40config CPU_CORTEX_M4 41 bool 42 select CPU_CORTEX_M 43 select ARMV7_M_ARMV8_M_MAINLINE 44 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 45 help 46 This option signifies the use of a Cortex-M4 CPU 47 48config CPU_CORTEX_M23 49 bool 50 select CPU_CORTEX_M 51 select ARMV8_M_BASELINE 52 select ARMV8_M_SE if CPU_HAS_TEE 53 help 54 This option signifies the use of a Cortex-M23 CPU 55 56config CPU_CORTEX_M33 57 bool 58 select CPU_CORTEX_M 59 select ARMV8_M_MAINLINE 60 select ARMV8_M_SE if CPU_HAS_TEE 61 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 62 help 63 This option signifies the use of a Cortex-M33 CPU 64 65config CPU_CORTEX_M55 66 bool 67 select CPU_CORTEX_M 68 select ARMV8_1_M_MAINLINE 69 select ARMV8_M_SE if CPU_HAS_TEE 70 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 71 help 72 This option signifies the use of a Cortex-M55 CPU 73 74config CPU_CORTEX_M7 75 bool 76 select CPU_CORTEX_M 77 select ARMV7_M_ARMV8_M_MAINLINE 78 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 79 help 80 This option signifies the use of a Cortex-M7 CPU 81 82if CPU_CORTEX_M 83 84config CPU_CORTEX_M_HAS_SYSTICK 85 bool 86 help 87 This option is enabled when the CPU implements the SysTick timer. 88 89config CPU_CORTEX_M_HAS_DWT 90 bool 91 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1 92 help 93 This option signifies that the CPU implements the Data Watchpoint and 94 Trace (DWT) unit specified by the ARMv7-M and above. 95 96 While ARMv6-M does define a "DWT" unit, this is significantly different 97 from the DWT specified by the ARMv7-M and above in terms of both feature 98 set and register mappings. 99 100config CPU_CORTEX_M_HAS_BASEPRI 101 bool 102 depends on ARMV7_M_ARMV8_M_MAINLINE 103 help 104 This option signifies the CPU has the BASEPRI register. 105 106 The BASEPRI register defines the minimum priority for 107 exception processing. When BASEPRI is set to a nonzero 108 value, it prevents the activation of all exceptions with 109 the same or lower priority level as the BASEPRI value. 110 Always present in CPUs that implement the ARMv7-M or 111 ARM8-M Mainline architectures. 112 113config CPU_CORTEX_M_HAS_VTOR 114 bool 115 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1 116 help 117 This option signifies the CPU has the VTOR register. 118 The VTOR indicates the offset of the vector table base 119 address from memory address 0x00000000. Always present 120 in CPUs implementing the ARMv7-M or ARMv8-M architectures. 121 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline 122 architectures (except for Cortex-M0/M1, where it is never 123 implemented). 124 125config CPU_CORTEX_M_HAS_SPLIM 126 bool 127 depends on ARMV8_M_MAINLINE || (ARMV8_M_SE && !ARM_NONSECURE_FIRMWARE) 128 help 129 This option signifies the CPU has the MSPLIM, PSPLIM registers. 130 131 The stack pointer limit registers, MSPLIM, PSPLIM, limit the 132 extend to which the Main and Process Stack Pointers, respectively, 133 can descend. MSPLIM, PSPLIM are always present in ARMv8-M 134 MCUs that implement the ARMv8-M Main Extension (Mainline). 135 136 In an ARMv8-M Mainline implementation with the Security Extension 137 the MSPLIM, PSPLIM registers have additional Secure instances. 138 In an ARMv8-M Baseline implementation with the Security Extension 139 the MSPLIM, PSPLIM registers have only Secure instances. 140 141config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 142 bool 143 depends on ARMV7_M_ARMV8_M_MAINLINE 144 help 145 This option signifies the CPU may trigger system faults 146 (other than HardFault) with configurable priority, and, 147 therefore, it needs to reserve a priority level for them. 148 149config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 150 bool 151 depends on ARMV6_M_ARMV8_M_BASELINE 152 help 153 This option signifies the Cortex-M0 has some mechanisms that can map 154 the vector table to SRAM 155 156config CPU_CORTEX_M_HAS_CMSE 157 bool 158 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 159 help 160 This option signifies the Cortex-M CPU has the CMSE intrinsics. 161 162config ARMV6_M_ARMV8_M_BASELINE 163 bool 164 select ATOMIC_OPERATIONS_C 165 select ISA_THUMB2 166 help 167 This option signifies the use of an ARMv6-M processor 168 implementation, or the use of an ARMv8-M processor 169 supporting the Baseline implementation. 170 171 Notes: 172 - A Processing Element (PE) without the Main Extension 173 is also referred to as a Baseline Implementation. A 174 Baseline implementation has a subset of the instructions, 175 registers, and features, of a Mainline implementation. 176 - ARMv6-M compatibility is provided by all ARMv8-M 177 implementations. 178 179config ARMV8_M_BASELINE 180 bool 181 select ARMV6_M_ARMV8_M_BASELINE 182 select CPU_CORTEX_M_HAS_CMSE 183 help 184 This option signifies the use of an ARMv8-M processor 185 implementation. 186 187 ARMv8-M Baseline includes additional features 188 not present in the ARMv6-M architecture. 189 190config ARMV7_M_ARMV8_M_MAINLINE 191 bool 192 select ATOMIC_OPERATIONS_BUILTIN 193 select ISA_THUMB2 194 select CPU_CORTEX_M_HAS_BASEPRI 195 select CPU_CORTEX_M_HAS_VTOR 196 select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 197 select CPU_CORTEX_M_HAS_SYSTICK 198 help 199 This option signifies the use of an ARMv7-M processor 200 implementation, or the use of a backwards-compatible 201 ARMv8-M processor implementation supporting the Main 202 Extension. 203 204 Notes: 205 - A Processing Element (PE) with the Main Extension is also 206 referred to as a Mainline Implementation. 207 - ARMv7-M compatibility requires the Main Extension. 208 209 From https://developer.arm.com/products/architecture/m-profile: 210 The Main Extension provides backwards compatibility 211 with ARMv7-M. 212 213config ARMV8_M_MAINLINE 214 bool 215 select ARMV7_M_ARMV8_M_MAINLINE 216 select CPU_CORTEX_M_HAS_SPLIM 217 select CPU_CORTEX_M_HAS_CMSE 218 help 219 This option signifies the use of an ARMv8-M processor 220 implementation, supporting the Main Extension. 221 222 ARMv8-M Main Extension includes additional features 223 not present in the ARMv7-M architecture. 224 225config ARMV8_1_M_MAINLINE 226 bool 227 select ARMV8_M_MAINLINE 228 help 229 This option signifies the use of an ARMv8.1-M processor 230 implementation, supporting the Main Extension. 231 232 ARMv8.1-M Main Extension includes additional features 233 not present in the ARMv8-M architecture. 234 235config ARMV8_M_SE 236 bool 237 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 238 select CPU_CORTEX_M_HAS_SPLIM if !ARM_NONSECURE_FIRMWARE 239 help 240 This option signifies the use of an ARMv8-M processor 241 implementation (Baseline or Mainline) supporting the 242 Security Extensions. 243 244config ARMV7_M_ARMV8_M_FP 245 bool 246 depends on ARMV7_M_ARMV8_M_MAINLINE && !CPU_CORTEX_M3 247 imply FPU_SHARING 248 help 249 This option signifies the use of an ARMv7-M processor 250 implementation, or the use of an ARMv8-M processor 251 implementation supporting the Floating-Point Extension. 252 253config ARMV8_M_DSP 254 bool 255 depends on ARMV8_M_MAINLINE 256 help 257 This option signifies the use of an ARMv8-M processor 258 implementation supporting the DSP Extension. 259 260config ARMV8_1_M_MVEI 261 bool 262 depends on ARMV8_1_M_MAINLINE 263 depends on ARMV8_M_DSP 264 help 265 This option signifies the use of an ARMv8.1-M processor implementation 266 supporting the M-Profile Vector Extension (MVE) integer instruction set. 267 268config ARMV8_1_M_MVEF 269 bool 270 depends on ARMV8_1_M_MVEI 271 help 272 This option signifies the use of an ARMv8.1-M processor implementation 273 supporting the M-Profile Vector Extension (MVE) floating-point 274 instruction set. 275 276menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33 options" 277 depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE 278 279config GEN_ISR_TABLES 280 default y 281 282config ZERO_LATENCY_IRQS 283 bool "Enable zero-latency interrupts" 284 depends on CPU_CORTEX_M_HAS_BASEPRI 285 help 286 The kernel may reserve some of the highest interrupts priorities in 287 the system for its own use. These interrupts will not be masked 288 by interrupt locking. 289 When connecting interrupts the kernel will offset all interrupts 290 to lower priority than those reserved by the kernel. 291 Zero-latency interrupt can be used to set up an interrupt at the 292 highest interrupt priority which will not be blocked by interrupt 293 locking. 294 Since Zero-latency ISRs will run in the same priority or possibly at 295 higher priority than the rest of the kernel they cannot use any 296 kernel functionality. 297 298config DYNAMIC_DIRECT_INTERRUPTS 299 bool "Enable support for dynamic direct interrupts" 300 depends on DYNAMIC_INTERRUPTS 301 help 302 Direct interrupts are designed for performance-critical interrupt 303 handling and do not go through all of the common interrupt handling 304 code. This option enables the installation of interrupt service 305 routines for direct interrupts at runtime. 306 Note: this requires enabling support for dynamic interrupts in the 307 kernel. 308 309config SW_VECTOR_RELAY 310 bool "Enable Software Vector Relay" 311 help 312 When building a bootloader firmware this option adds a 313 vector table relay handler and a vector relay table, to 314 relay interrupts based on a vector table pointer. 315 This is only required but not limited to Cortex-M Baseline CPUs 316 with no hardware vector table relocation mechanisms (e.g. VTOR). 317 318config SW_VECTOR_RELAY_CLIENT 319 bool "Enable Software Vector Relay (client)" 320 default y if BOOTLOADER_MCUBOOT && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 321 depends on !CPU_CORTEX_M_HAS_VTOR 322 help 323 Another image has enabled SW_VECTOR_RELAY, and will be forwarding 324 exceptions and HW interrupts to this image. Enable this option to make 325 sure the vector table pointer in RAM is set properly by the image upon 326 initialization. 327 328config CORTEX_M_DWT 329 bool "Enable and use the DWT" 330 depends on CPU_CORTEX_M_HAS_DWT 331 default y if TIMING_FUNCTIONS 332 help 333 Enable and use the Data Watchpoint and Trace (DWT) unit for 334 timing functions. 335 336# Additional stack for tests when building with FPU_SHARING 337# enabled, which may increase ESF stacking requirements for 338# threads. 339config TEST_EXTRA_STACKSIZE 340 default 512 if TEST_ARM_CORTEX_M && FPU_SHARING 341 342endmenu 343 344# Implement the null pointer detection using either the Data Watchpoint and 345# Trace Unit and the Debug Monitor Exception, or the Memory Protection Unit. 346 347choice NULL_POINTER_EXCEPTION_DETECTION 348 bool "Enable and use null-pointer exception" 349 # Disable this until https://github.com/zephyrproject-rtos/zephyr/issues/32984 is fixed 350 # default NULL_POINTER_EXCEPTION_DETECTION_DWT if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && CPU_CORTEX_M_HAS_DWT 351 default NULL_POINTER_EXCEPTION_DETECTION_MPU if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && ARM_MPU && !CPU_CORTEX_M_HAS_DWT 352 default NULL_POINTER_EXCEPTION_DETECTION_NONE 353 help 354 There are 2 implementations available, one based 355 on DWT and the other based on MPU. Use this choice 356 symbol to select one of the options. By default the 357 feature is disabled. In the test suite the feature 358 is enabled and the DWT-based solution is preferred. 359 360config NULL_POINTER_EXCEPTION_DETECTION_NONE 361 bool "Do not enable null pointer exception detection" 362 help 363 Null pointer exception detection feature is not 364 enabled. 365 366config NULL_POINTER_EXCEPTION_DETECTION_DWT 367 bool "Use DWT for null pointer exception detection" 368 depends on CPU_CORTEX_M_HAS_DWT 369 depends on !TRUSTED_EXECUTION_NONSECURE 370 select CORTEX_M_DWT 371 select CORTEX_M_NULL_POINTER_EXCEPTION 372 help 373 Null pointer dereference detection implemented 374 using the DWT unit functionality. 375 Notes: 376 - Not enabled for Non-Secure FW images, where 377 null-pointer dereferencing is likely caught as 378 a SecureFault. 379 - Requires DWT functionality in the Cortex-M SoC 380 implementation (1 comparator for ARMv7-M, 2 comparators 381 for ARMv8-M). 382 - Requires the Cortex-M core be in normal mode. 383 384config NULL_POINTER_EXCEPTION_DETECTION_MPU 385 bool "Use MPU for null pointer exception detection" 386 depends on !TRUSTED_EXECUTION_NONSECURE 387 depends on ARM_MPU 388 select CORTEX_M_NULL_POINTER_EXCEPTION 389 help 390 Null pointer dereference detection implemented 391 using MPU functionality. 392 Notes: 393 - Mutually exclusive to the DWT-based solution 394 - Not enabled for Non-Secure FW images, where 395 null-pointer dereferencing is likely caught as 396 a SecureFault. 397 - Requires MPU functionality to be present and 398 enabled. The implementation consumes 1 MPU region. 399 - In ARMv8-M, explicit null-pointer dereference 400 detection with MPU requires, additionally, that 401 the area: [0x0, 402 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) 403 is not unmapped (covered by an MPU region already). 404 If it is unmapped null-pointer dereferencing may 405 still be idirectly detected (e.g. via a precise 406 Bus access fault), but this is not guaranteed. A 407 build-time message warns the user of this scenario. 408 409endchoice 410 411config CORTEX_M_NULL_POINTER_EXCEPTION 412 bool 413 help 414 Enable and use the null pointer exception option. 415 This is a debug feature in Cortex-M, allowing for 416 detecting null pointer dereferencing (raising a 417 CPU fault). Supporting the feature results in an 418 increased code footprint, determined by option 419 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE. 420 421 Note: this hidden option is selected by the choice 422 symbols corresponding to the DWT-based or to the 423 MPU-based solution. 424 425if CORTEX_M_NULL_POINTER_EXCEPTION 426 427config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE 428 hex "Size of paged unmapped to implement null pointer detection" 429 default 0x400 430 help 431 Size of the page reserved for detecting null pointer 432 dereferencing. Must be a power of two. A large value 433 offers enhanced detection performance to the cost of 434 wasting a large flash area that code may not use. 435 436endif # CORTEX_M_NULL_POINTER_EXCEPTION 437 438rsource "tz/Kconfig" 439 440endif # CPU_CORTEX_M 441
