1# XTENSA architecture configuration options
2
3# Copyright (c) 2016 Cadence Design Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6menu "XTENSA Options"
7	depends on XTENSA
8
9config ARCH
10	default "xtensa"
11
12config SIMULATOR_XTENSA
13	bool "Simulator Target"
14	help
15	  Enable if building to run on simulator.
16
17config XTENSA_RESET_VECTOR
18	bool "Build reset vector code"
19	default y
20	help
21	  This option controls whether the initial reset vector code is built.
22	  This is always needed for the simulator. Real boards may already
23	  implement this in boot ROM.
24
25config XTENSA_GEN_HANDLERS
26	bool "Automatically generate interrupt handlers"
27	default n
28	help
29	  When set, an "xtensa_handlers.h" file is generated
30	  containing definitions for the interrupt entry code of the
31	  target Xtensa core, based automatically on the details in
32	  the core-isa.h file.  This replaces the previous scheme
33	  where a _soc_inthandlers.h file would be generated offline.
34
35config XTENSA_USE_CORE_CRT1
36	bool "Use crt1.S from core"
37	default y
38	help
39	  SoC or boards might define their own __start by setting this setting
40	  to false.
41
42config XTENSA_ENABLE_BACKTRACE
43	bool "Backtrace on panic exception"
44	default y
45	depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP || SOC_XTENSA_DC233C
46	help
47	  Enable this config option to print backtrace on panic exception
48
49config XTENSA_SMALL_VECTOR_TABLE_ENTRY
50	bool "Workaround for small vector table entries"
51	help
52	  This option enables a small indirection to bypass the size
53	  constraint of the vector table entry and moved the default
54	  handlers to the end of vector table, renaming them to
55	  _Level\LVL\()VectorHelper.
56
57config XTENSA_RPO_CACHE
58	bool "Cached/uncached RPO mapping"
59	help
60	  Support Cached/uncached RPO mapping.
61
62	  A design trick on multi-core hardware is to map memory twice
63	  so that it can be seen in both (incoherent) cached mappings
64	  and a coherent "shared" area.
65
66if XTENSA_RPO_CACHE
67config XTENSA_CACHED_REGION
68	int "Cached RPO mapping"
69	range 0 7
70	help
71	  This specifies which 512M region (0-7, as defined by the Xtensa
72	  Region Protection Option) contains the "cached" mapping.
73
74config XTENSA_UNCACHED_REGION
75	int "Uncached RPO mapping"
76	range 0 7
77	help
78	  As for XTENSA_CACHED_REGION, this specifies which 512M
79	  region (0-7) contains the "uncached" mapping.
80
81endif
82
83config XTENSA_CCOUNT_HZ
84	int "CCOUNT cycle rate"
85	default 1000000
86	help
87	  Rate in HZ of the Xtensa core as measured by the value of
88	  the CCOUNT register.
89
90config XTENSA_MORE_SPIN_RELAX_NOPS
91	bool "Use Xtensa specific arch_spin_relax() with more NOPs"
92	help
93	  Some Xtensa SoCs, especially under SMP, may need extra
94	  NOPs after failure to lock a spinlock. This gives
95	  the bus extra time to synchronize the RCW transaction
96	  among CPUs.
97
98config XTENSA_NUM_SPIN_RELAX_NOPS
99	int "Number of NOPs to be used in arch_spin_relax()"
100	default 1
101	depends on XTENSA_MORE_SPIN_RELAX_NOPS
102	help
103	  Specify the number of NOPs in Xtensa specific
104	  arch_spin_relax().
105
106config XTENSA_BREAK_ON_UNRECOVERABLE_EXCEPTIONS
107	bool "Use BREAK instruction on unrecoverable exceptions"
108	help
109	  Use BREAK instruction when unrecoverable exceptions are
110	  encountered. This requires a debugger attached to catch
111	  the BREAK.
112
113menu "Xtensa HiFi Options"
114
115config XTENSA_CPU_HAS_HIFI
116	bool
117
118config XTENSA_CPU_HAS_HIFI3
119	select XTENSA_CPU_HAS_HIFI
120	bool
121
122config XTENSA_CPU_HAS_HIFI4
123	select XTENSA_CPU_HAS_HIFI
124	bool
125
126# Selected when at least one XTENSA_HIFIn version has been configured
127config XTENSA_HIFI
128	bool
129
130if XTENSA_CPU_HAS_HIFI
131
132config XTENSA_HIFI3
133	bool "HiFi3 AudioEngine instructions"
134	depends on XTENSA_CPU_HAS_HIFI3
135	default y
136	select XTENSA_HIFI
137	help
138	  This option enables HiFi 3 instruction support.
139
140config XTENSA_HIFI4
141	bool "HiFi4 AudioEngine instructions"
142	depends on XTENSA_CPU_HAS_HIFI4
143	default y
144	select XTENSA_HIFI
145	help
146	  This option enables HiFi 4 instruction support.
147
148config XTENSA_HIFI_SHARING
149	bool "HiFi register sharing"
150	depends on XTENSA_HIFI
151	help
152	  This option enables preservation of the hardware HiFi registers
153	  across context switches to allow multiple threads to perform
154	  concurrent HiFi operations.
155
156endif    # XTENSA_CPU_HAS_HIFI
157
158endmenu  # Xtensa HiFi Options
159
160config XTENSA_INTERRUPT_NONPREEMPTABLE
161	bool "Xtensa exceptions and interrupts cannot be pre-empted"
162	help
163	  Allow use of medium and high priority interrupts without
164	  pre-empting low priority interrupts and exceptions.
165
166if CPU_HAS_MMU
167
168config XTENSA_MMU
169	bool "Xtensa MMU Support"
170	select MMU
171	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
172	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
173	select KERNEL_VM_USE_CUSTOM_MEM_RANGE_CHECK if XTENSA_RPO_CACHE
174	select CURRENT_THREAD_USE_NO_TLS if USERSPACE
175	help
176	  Enable support for Xtensa Memory Management Unit.
177
178if XTENSA_MMU
179
180choice
181	prompt "PageTable virtual address"
182	default XTENSA_MMU_PTEVADDR_20000000
183	help
184	  The virtual address for Xtensa page table (PTEVADDR).
185
186config XTENSA_MMU_PTEVADDR_20000000
187	bool "0x20000000"
188
189endchoice
190
191config XTENSA_MMU_PTEVADDR
192	hex
193	default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
194	help
195	  The virtual address for Xtensa page table (PTEVADDR).
196
197config XTENSA_MMU_PTEVADDR_SHIFT
198	int
199	default 29 if XTENSA_MMU_PTEVADDR_20000000
200	help
201	  The bit shift number for the virtual address for Xtensa
202	  page table (PTEVADDR).
203
204config XTENSA_MMU_NUM_L1_TABLES
205	int "Number of L1 page tables"
206	default 1 if !USERSPACE
207	default 4
208	help
209	  This option specifies the maximum number of traslation tables.
210	  Translation tables are directly related to the number of
211	  memory domains in the target, considering the kernel itself requires one.
212
213config XTENSA_MMU_NUM_L2_TABLES
214	int "Number of L2 page tables"
215	default 20 if USERSPACE
216	default 10
217	help
218	  Each table can address up to 4MB memory address.
219
220config XTENSA_MMU_DOUBLE_MAP
221	bool "Map memory in cached and uncached region"
222	help
223	  This option specifies that the memory is mapped in two
224	  distinct region, cached and uncached.
225
226	config XTENSA_INVALIDATE_MEM_DOMAIN_TLB_ON_SWAP
227		bool
228		help
229		  This invalidates all TLBs referred by the incoming thread's
230		  memory domain when swapping page tables.
231
232config PRIVILEGED_STACK_SIZE
233	# Must be multiple of CONFIG_MMU_PAGE_SIZE
234	default 4096
235
236endif # XTENSA_MMU
237
238endif # CPU_HAS_MMU
239
240if CPU_HAS_MPU
241
242menuconfig XTENSA_MPU
243	bool "Xtensa MPU Support"
244	select MPU
245	select SRAM_REGION_PERMISSIONS
246	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
247	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
248	select CURRENT_THREAD_USE_NO_TLS if USERSPACE
249	select EXPERIMENTAL
250	# TODO: the target the MPU code developed on (basically sample_controller
251	#       plus MPU minus s32c1i) does not have cache or SMP capability.
252	#       Need to verify functionalities with targets supporting these.
253	depends on !CACHE && !SMP
254	help
255	  Enable support for Xtensa Memory Protection Unit.
256
257if XTENSA_MPU
258
259config XTENSA_MPU_DEFAULT_MEM_TYPE
260	hex "Default Memory Type"
261	default 0x18
262	help
263	  Default memory type for memory regions: non-cacheable memory,
264	  non-shareable, non-bufferable and interruptible.
265
266	  If userspace is enabled, it will be used to restore the memory type of
267	  the region being removed from a memory domain.
268
269config XTENSA_MPU_ONLY_SOC_RANGES
270	bool
271	help
272	  Enable this by the SoC to indicate to the architecture code to use
273	  the MPU ranges specified by SoC only, and skip the common ranges
274	  defined in the core architecture code. This gives total control to
275	  the SoC on the MPU ranges.
276
277endif # XTENSA_MPU
278
279endif # CPU_HAS_MPU
280
281config XTENSA_SYSCALL_USE_HELPER
282	bool "Use userspace syscall helper"
283	default y if "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "xt-clang"
284	depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE
285	help
286	  Use syscall helpers for passing more than 3 arguments.
287	  This is a workaround for toolchains where they have
288	  issue modeling register usage.
289
290config XTENSA_INSECURE_USERSPACE
291	bool
292	default y
293	depends on (XTENSA_MMU || XTENSA_MPU) && USERSPACE
294
295endmenu
296