1# XTENSA architecture configuration options
2
3# Copyright (c) 2016 Cadence Design Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6menu "XTENSA Options"
7	depends on XTENSA
8
9config ARCH
10	default "xtensa"
11
12config SIMULATOR_XTENSA
13	bool "Simulator Configuration"
14	help
15	  Specify if the board configuration should be treated as a simulator.
16
17config SYS_CLOCK_HW_CYCLES_PER_SEC
18	prompt "Hardware clock cycles per second, 2000000 for ISS"
19	default 2000000
20	range 1000000 1000000000
21	help
22	  This option specifies hardware clock.
23
24config XTENSA_NO_IPC
25	bool "Core has no IPC support"
26	select ATOMIC_OPERATIONS_C
27	help
28	  Uncheck this if your core does not implement "SCOMPARE1" register and "s32c1i"
29	  instruction.
30
31config XTENSA_RESET_VECTOR
32	bool "Build reset vector code"
33	default y
34	help
35	  This option controls whether the initial reset vector code is built.
36	  This is always needed for the simulator. Real boards may already
37	  implement this in boot ROM.
38
39config XTENSA_USE_CORE_CRT1
40	bool "Use crt1.S from core"
41	default y
42	help
43	  SoC or boards might define their own __start by setting this setting
44	  to false.
45
46config XTENSA_ENABLE_BACKTRACE
47	bool "Backtrace on panic exception"
48	default y
49	depends on SOC_SERIES_ESP32 || SOC_FAMILY_INTEL_ADSP || SOC_XTENSA_DC233C
50	help
51	  Enable this config option to print backtrace on panic exception
52
53config XTENSA_CPU_IDLE_SPIN
54	bool "Use busy loop for k_cpu_idle"
55	help
56	  Use a spin loop instead of WAITI for the CPU idle state.
57
58config XTENSA_WAITI_BUG
59	bool "Workaround sequence for WAITI bug on LX6"
60	help
61	  SOF traditionally contains this workaround on its ADSP
62	  platforms which prefixes a WAITI entry with 128 NOP
63	  instructions followed by an ISYNC and EXTW.
64
65config XTENSA_SMALL_VECTOR_TABLE_ENTRY
66	bool "Workaround for small vector table entries"
67	help
68	  This option enables a small indirection to bypass the size
69	  constraint of the vector table entry and moved the default
70	  handlers to the end of vector table, renaming them to
71	  _Level\LVL\()VectorHelper.
72
73config XTENSA_RPO_CACHE
74	bool "Cached/uncached RPO mapping"
75	help
76	  Support Cached/uncached RPO mapping.
77
78	  A design trick on multi-core hardware is to map memory twice
79	  so that it can be seen in both (incoherent) cached mappings
80	  and a coherent "shared" area.
81
82if XTENSA_RPO_CACHE
83config XTENSA_CACHED_REGION
84	int "Cached RPO mapping"
85	range 0 7
86	help
87	  This specifies which 512M region (0-7, as defined by the Xtensa
88	  Region Protection Option) contains the "cached" mapping.
89
90config XTENSA_UNCACHED_REGION
91	int "Uncached RPO mapping"
92	range 0 7
93	help
94	  As for XTENSA_CACHED_REGION, this specifies which 512M
95	  region (0-7) contains the "uncached" mapping.
96
97endif
98
99config XTENSA_CCOUNT_HZ
100	int "CCOUNT cycle rate"
101	default 1000000
102	help
103	  Rate in HZ of the Xtensa core as measured by the value of
104	  the CCOUNT register.
105
106config XTENSA_MORE_SPIN_RELAX_NOPS
107	bool "Use Xtensa specific arch_spin_relax() with more NOPs"
108	help
109	  Some Xtensa SoCs, especially under SMP, may need extra
110	  NOPs after failure to lock a spinlock. This gives
111	  the bus extra time to synchronize the RCW transaction
112	  among CPUs.
113
114config XTENSA_NUM_SPIN_RELAX_NOPS
115	int "Number of NOPs to be used in arch_spin_relax()"
116	default 1
117	depends on XTENSA_MORE_SPIN_RELAX_NOPS
118	help
119	  Specify the number of NOPs in Xtensa specific
120	  arch_spin_relax().
121
122if CPU_HAS_MMU
123
124config XTENSA_MMU
125	bool "Xtensa MMU Support"
126	default n
127	select MMU
128	select XTENSA_SMALL_VECTOR_TABLE_ENTRY
129	help
130	  Enable support for Xtensa Memory Management Unit.
131
132if XTENSA_MMU
133
134	choice
135		prompt "PageTable virtual adddress"
136		default XTENSA_MMU_PTEVADDR_20000000
137		help
138		  The virtual address for Xtensa page table (PTEVADDR).
139
140	config XTENSA_MMU_PTEVADDR_20000000
141		bool "0x20000000"
142
143	endchoice
144
145	config XTENSA_MMU_PTEVADDR
146		hex
147		default 0x20000000 if XTENSA_MMU_PTEVADDR_20000000
148		help
149		  The virtual address for Xtensa page table (PTEVADDR).
150
151	config XTENSA_MMU_PTEVADDR_SHIFT
152		int
153		default 29 if XTENSA_MMU_PTEVADDR_20000000
154		help
155		  The bit shift number for the virtual address for Xtensa
156		  page table (PTEVADDR).
157
158	config XTENSA_MMU_NUM_L2_TABLES
159		int "Number of L2 page tables"
160		default 10
161		help
162		  Each table can address up to 4MB memory address.
163
164	config XTENSA_MMU_DOUBLE_MAP
165		bool "Map memory in cached and uncached region"
166		default n
167		help
168			This option specifies that the memory is mapped in two
169			distinct region, cached and uncached.
170
171endif # XTENSA_MMU
172
173endif # CPU_HAS_MMU
174
175endmenu
176