1# General architecture configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2015 Intel Corporation 5# Copyright (c) 2016 Cadence Design Systems, Inc. 6# SPDX-License-Identifier: Apache-2.0 7 8# Include these first so that any properties (e.g. defaults) below can be 9# overridden (by defining symbols in multiple locations) 10 11# Note: $ARCH might be a glob pattern 12source "$(ARCH_DIR)/$(ARCH)/Kconfig" 13 14# Architecture symbols 15# 16# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that, 17# by SOC_*. 18 19config ARC 20 bool 21 select ARCH_IS_SET 22 select HAS_DTS 23 imply XIP 24 select ARCH_HAS_THREAD_LOCAL_STORAGE 25 help 26 ARC architecture 27 28config ARM 29 bool 30 select ARCH_IS_SET 31 select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M 32 select HAS_DTS 33 # FIXME: current state of the code for all ARM requires this, but 34 # is really only necessary for Cortex-M with ARM MPU! 35 select GEN_PRIV_STACKS 36 select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_CORTEX_R || CPU_CORTEX_M 37 help 38 ARM architecture 39 40config ARM64 41 bool 42 select ARCH_IS_SET 43 select 64BIT 44 select HAS_DTS 45 select HAS_ARM_SMCCC 46 select ARCH_HAS_THREAD_LOCAL_STORAGE 47 select USE_SWITCH 48 select USE_SWITCH_SUPPORTED 49 help 50 ARM64 (AArch64) architecture 51 52config SPARC 53 bool 54 select ARCH_IS_SET 55 select HAS_DTS 56 select USE_SWITCH 57 select USE_SWITCH_SUPPORTED 58 select BIG_ENDIAN 59 select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA 60 select ATOMIC_OPERATIONS_C if !SPARC_CASA 61 select ARCH_HAS_THREAD_LOCAL_STORAGE 62 select ARCH_HAS_EXTRA_EXCEPTION_INFO 63 help 64 SPARC architecture 65 66config X86 67 bool 68 select ARCH_IS_SET 69 select ATOMIC_OPERATIONS_BUILTIN 70 select HAS_DTS 71 select ARCH_SUPPORTS_COREDUMP 72 select CPU_HAS_MMU 73 select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE 74 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 75 select ARCH_HAS_GDBSTUB if !X86_64 76 select ARCH_HAS_TIMING_FUNCTIONS 77 select ARCH_HAS_THREAD_LOCAL_STORAGE 78 select ARCH_HAS_DEMAND_PAGING 79 select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ 80 && !BOARD_HAS_TIMING_FUNCTIONS \ 81 && !SOC_HAS_TIMING_FUNCTIONS 82 help 83 x86 architecture 84 85config NIOS2 86 bool 87 select ARCH_IS_SET 88 select ATOMIC_OPERATIONS_C 89 select HAS_DTS 90 imply XIP 91 select ARCH_HAS_TIMING_FUNCTIONS 92 help 93 Nios II Gen 2 architecture 94 95config RISCV 96 bool 97 select ARCH_IS_SET 98 select HAS_DTS 99 select ARCH_HAS_THREAD_LOCAL_STORAGE 100 imply XIP 101 help 102 RISCV architecture 103 104config XTENSA 105 bool 106 select ARCH_IS_SET 107 select HAS_DTS 108 select USE_SWITCH 109 select USE_SWITCH_SUPPORTED 110 imply ATOMIC_OPERATIONS_ARCH 111 help 112 Xtensa architecture 113 114config ARCH_POSIX 115 bool 116 select ARCH_IS_SET 117 select HAS_DTS 118 select ATOMIC_OPERATIONS_BUILTIN 119 select ARCH_HAS_CUSTOM_SWAP_TO_MAIN 120 select ARCH_HAS_CUSTOM_BUSY_WAIT 121 select ARCH_HAS_THREAD_ABORT 122 select NATIVE_APPLICATION 123 select HAS_COVERAGE_SUPPORT 124 help 125 POSIX (native) architecture 126 127config ARCH_IS_SET 128 bool 129 help 130 Helper symbol to detect SoCs forgetting to select one of the arch 131 symbols above. See the top-level CMakeLists.txt. 132 133menu "General Architecture Options" 134 135module = ARCH 136module-str = arch 137source "subsys/logging/Kconfig.template.log_config" 138 139module = MPU 140module-str = mpu 141source "subsys/logging/Kconfig.template.log_config" 142 143config BIG_ENDIAN 144 bool 145 help 146 This option tells the build system that the target system is big-endian. 147 Little-endian architecture is the default and should leave this option 148 unselected. This option is selected by arch/$ARCH/Kconfig, 149 soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid 150 modifying it. The option is used to select linker script OUTPUT_FORMAT 151 and command line option for gen_isr_tables.py. 152 153config 64BIT 154 bool 155 help 156 This option tells the build system that the target system is 157 using a 64-bit address space, meaning that pointer and long types 158 are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, 159 soc/**/Kconfig, or boards/**/Kconfig and the user should generally 160 avoid modifying it. 161 162# Workaround for not being able to have commas in macro arguments 163DT_CHOSEN_Z_SRAM := zephyr,sram 164 165config SRAM_SIZE 166 int "SRAM Size in kB" 167 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) 168 help 169 The SRAM size in kB. The default value comes from /chosen/zephyr,sram in 170 devicetree. The user should generally avoid changing it via menuconfig or 171 in configuration files. 172 173config SRAM_BASE_ADDRESS 174 hex "SRAM Base Address" 175 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 176 help 177 The SRAM base address. The default value comes from from 178 /chosen/zephyr,sram in devicetree. The user should generally avoid 179 changing it via menuconfig or in configuration files. 180 181if ARC || ARM || ARM64 || NIOS2 || X86 182 183# Workaround for not being able to have commas in macro arguments 184DT_CHOSEN_Z_FLASH := zephyr,flash 185 186config FLASH_SIZE 187 int "Flash Size in kB" 188 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM 189 help 190 This option specifies the size of the flash in kB. It is normally set by 191 the board's defconfig file and the user should generally avoid modifying 192 it via the menu configuration. 193 194config FLASH_BASE_ADDRESS 195 hex "Flash Base Address" 196 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM 197 help 198 This option specifies the base address of the flash on the board. It is 199 normally set by the board's defconfig file and the user should generally 200 avoid modifying it via the menu configuration. 201 202endif # ARM || ARM64 || ARC || NIOS2 || X86 203 204if ARCH_HAS_TRUSTED_EXECUTION 205 206config TRUSTED_EXECUTION_SECURE 207 bool "Trusted Execution: Secure firmware image" 208 help 209 Select this option to enable building a Secure firmware 210 image for a platform that supports Trusted Execution. A 211 Secure firmware image will execute in Secure state. It may 212 allow the CPU to execute in Non-Secure (Normal) state. 213 Therefore, a Secure firmware image shall be able to 214 configure security attributions of CPU resources (memory 215 areas, peripherals, interrupts, etc.) as well as to handle 216 faults, related to security violations. It may optionally 217 allow certain functions to be called from the Non-Secure 218 (Normal) domain. 219 220config TRUSTED_EXECUTION_NONSECURE 221 depends on !TRUSTED_EXECUTION_SECURE 222 bool "Trusted Execution: Non-Secure firmware image" 223 help 224 Select this option to enable building a Non-Secure 225 firmware image for a platform that supports Trusted 226 Execution. A Non-Secure firmware image will execute 227 in Non-Secure (Normal) state. Therefore, it shall not 228 access CPU resources (memory areas, peripherals, 229 interrupts etc.) belonging to the Secure domain. 230 231endif # ARCH_HAS_TRUSTED_EXECUTION 232 233config HW_STACK_PROTECTION 234 bool "Hardware Stack Protection" 235 depends on ARCH_HAS_STACK_PROTECTION 236 help 237 Select this option to enable hardware-based platform features to 238 catch stack overflows when the system is running in privileged 239 mode. If CONFIG_USERSPACE is not enabled, the system is always 240 running in privileged mode. 241 242 Note that this does not necessarily prevent corruption and assertions 243 about the overall system state when a fault is triggered cannot be 244 made. 245 246config USERSPACE 247 bool "User mode threads" 248 depends on ARCH_HAS_USERSPACE 249 depends on RUNTIME_ERROR_CHECKS 250 depends on SRAM_REGION_PERMISSIONS 251 select THREAD_STACK_INFO 252 help 253 When enabled, threads may be created or dropped down to user mode, 254 which has significantly restricted permissions and must interact 255 with the kernel via system calls. See Zephyr documentation for more 256 details about this feature. 257 258 If a user thread overflows its stack, this will be caught and the 259 kernel itself will be shielded from harm. Enabling this option 260 may or may not catch stack overflows when the system is in 261 privileged mode or handling a system call; to ensure these are always 262 caught, enable CONFIG_HW_STACK_PROTECTION. 263 264config PRIVILEGED_STACK_SIZE 265 int "Size of privileged stack" 266 default 1024 267 depends on ARCH_HAS_USERSPACE 268 help 269 This option sets the privileged stack region size that will be used 270 in addition to the user mode thread stack. During normal execution, 271 this region will be inaccessible from user mode. During system calls, 272 this region will be utilized by the system call. This value must be 273 a multiple of the minimum stack alignment. 274 275config KOBJECT_TEXT_AREA 276 int "Size of kobject text area" 277 default 512 if COVERAGE_GCOV 278 default 512 if NO_OPTIMIZATIONS 279 default 512 if STACK_CANARIES && RISCV 280 default 256 281 depends on ARCH_HAS_USERSPACE 282 help 283 Size of kernel object text area. Used in linker script. 284 285config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 286 int "Reserve extra kobject data area (in percentage)" 287 default 100 288 depends on ARCH_HAS_USERSPACE 289 help 290 Multiplication factor used to calculate the size of placeholder to 291 reserve space for kobject metadata hash table. The hash table is 292 generated via gperf is highly dependent on the absolute addresses of 293 kobjects which might change between prebuilts. To reserve enough 294 space for the hash table during final linking passes to keep 295 kobjects in same place, the size of reserved space is calculated 296 from the first prebuilt plus additional space calculated with 297 this percentage (of the kobject data area in first prebuilt). 298 299config KOBJECT_RODATA_AREA_EXTRA_BYTES 300 int "Reserve extra bytes for kobject rodata area" 301 default 16 302 depends on ARCH_HAS_USERSPACE 303 help 304 Reserve a few more bytes for the RODATA region for kobject metadata. 305 This is to account for the uncertainty of tables generated by gperf. 306 307config GEN_PRIV_STACKS 308 bool 309 help 310 Selected if the architecture requires that privilege elevation stacks 311 be allocated in a separate memory area. This is typical of arches 312 whose MPUs require regions to be power-of-two aligned/sized. 313 314 FIXME: This should be removed and replaced with checks against 315 CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC 316 changes will be necessary for this. 317 318config STACK_GROWS_UP 319 bool "Stack grows towards higher memory addresses" 320 help 321 Select this option if the architecture has upward growing thread 322 stacks. This is not common. 323 324config NO_UNUSED_STACK_INSPECTION 325 bool 326 help 327 Selected if the architecture will generate a fault if unused stack 328 memory is examined, which is the region between the current stack 329 pointer and the deepest available address in the current stack 330 region. 331 332config MAX_THREAD_BYTES 333 int "Bytes to use when tracking object thread permissions" 334 default 2 335 depends on USERSPACE 336 help 337 Every kernel object will have an associated bitfield to store 338 thread permissions for that object. This controls the size of the 339 bitfield (in bytes) and imposes a limit on how many threads can 340 be created in the system. 341 342config DYNAMIC_OBJECTS 343 bool "Allow kernel objects to be allocated at runtime" 344 depends on USERSPACE 345 help 346 Enabling this option allows for kernel objects to be requested from 347 the calling thread's resource pool, at a slight cost in performance 348 due to the supplemental run-time tables required to validate such 349 objects. 350 351 Objects allocated in this way can be freed with a supervisor-only 352 API call, or when the number of references to that object drops to 353 zero. 354 355config NOCACHE_MEMORY 356 bool "Support for uncached memory" 357 depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT 358 help 359 Add a "nocache" read-write memory section that is configured to 360 not be cached. This memory section can be used to perform DMA 361 transfers when cache coherence issues are not optimal or can not 362 be solved using cache maintenance operations. 363 364menu "Interrupt Configuration" 365 366config DYNAMIC_INTERRUPTS 367 bool "Enable installation of IRQs at runtime" 368 help 369 Enable installation of interrupts at runtime, which will move some 370 interrupt-related data structures to RAM instead of ROM, and 371 on some architectures increase code size. 372 373config GEN_ISR_TABLES 374 bool "Use generated IRQ tables" 375 help 376 This option controls whether a platform uses the gen_isr_tables 377 script to generate its interrupt tables. This mechanism will create 378 an appropriate hardware vector table and/or software IRQ table. 379 380config GEN_IRQ_VECTOR_TABLE 381 bool "Generate an interrupt vector table" 382 default y 383 depends on GEN_ISR_TABLES 384 help 385 This option controls whether a platform using gen_isr_tables 386 needs an interrupt vector table created. Only disable this if the 387 platform does not use a vector table at all, or requires the vector 388 table to be in a format that is not an array of function pointers 389 indexed by IRQ line. In the latter case, the vector table must be 390 supplied by the application or architecture code. 391 392config GEN_SW_ISR_TABLE 393 bool "Generate a software ISR table" 394 default y 395 depends on GEN_ISR_TABLES 396 help 397 This option controls whether a platform using gen_isr_tables 398 needs a software ISR table table created. This is an array of struct 399 _isr_table_entry containing the interrupt service routine and supplied 400 parameter. 401 402config ARCH_SW_ISR_TABLE_ALIGN 403 int "Alignment size of a software ISR table" 404 default 0 405 depends on GEN_SW_ISR_TABLE 406 help 407 This option controls alignment size of generated 408 _sw_isr_table. Some architecture needs a software ISR table 409 to be aligned to architecture specific size. The default 410 size is 0 for no alignment. 411 412config GEN_IRQ_START_VECTOR 413 int 414 default 0 415 depends on GEN_ISR_TABLES 416 help 417 On some architectures, part of the vector table may be reserved for 418 system exceptions and is declared separately from the tables 419 created by gen_isr_tables.py. When creating these tables, this value 420 will be subtracted from CONFIG_NUM_IRQS to properly size them. 421 This is a hidden option which needs to be set per architecture and 422 left alone. 423 424config IRQ_OFFLOAD 425 bool "Enable IRQ offload" 426 depends on TEST 427 help 428 Enable irq_offload() API which allows functions to be synchronously 429 run in interrupt context. Only useful for test cases that need 430 to validate the correctness of kernel objects in IRQ context. 431 432 433config EXTRA_EXCEPTION_INFO 434 bool "Collect extra exception info" 435 depends on ARCH_HAS_EXTRA_EXCEPTION_INFO 436 help 437 This option enables the collection of extra information, such as 438 register state, when a fault occurs. This information can be useful 439 to collect for post-mortem analysis and debug of issues. 440 441endmenu # Interrupt configuration 442 443config INIT_ARCH_HW_AT_BOOT 444 bool "Initialize internal architecture state at boot" 445 depends on ARCH_SUPPORTS_ARCH_HW_INIT 446 help 447 This option instructs Zephyr to force the initialization 448 of the internal architectural state (for example ARCH-level 449 HW registers and system control blocks) during boot to 450 the reset values as specified by the corresponding 451 architecture manual. The option is useful when the Zephyr 452 firmware image is chain-loaded, for example, by a debugger 453 or a bootloader, and we need to guarantee that the internal 454 states of the architecture core blocks are restored to the 455 reset values (as specified by the architecture). 456 457 Note: the functionality is architecture-specific. For the 458 implementation details refer to each architecture where 459 this feature is supported. 460 461endmenu 462 463# 464# Architecture Capabilities 465# 466 467config ARCH_HAS_SINGLE_THREAD_SUPPORT 468 bool 469 470config ARCH_HAS_TIMING_FUNCTIONS 471 bool 472 473config ARCH_HAS_TRUSTED_EXECUTION 474 bool 475 476config ARCH_HAS_STACK_PROTECTION 477 bool 478 479config ARCH_HAS_USERSPACE 480 bool 481 482config ARCH_HAS_EXECUTABLE_PAGE_BIT 483 bool 484 485config ARCH_HAS_NOCACHE_MEMORY_SUPPORT 486 bool 487 488config ARCH_HAS_RAMFUNC_SUPPORT 489 bool 490 491config ARCH_HAS_NESTED_EXCEPTION_DETECTION 492 bool 493 494config ARCH_SUPPORTS_COREDUMP 495 bool 496 497config ARCH_SUPPORTS_ARCH_HW_INIT 498 bool 499 500config ARCH_HAS_EXTRA_EXCEPTION_INFO 501 bool 502 503config ARCH_HAS_GDBSTUB 504 bool 505 506config ARCH_HAS_COHERENCE 507 bool 508 help 509 When selected, the architecture supports the 510 arch_mem_coherent() API and can link into incoherent/cached 511 memory using the ".cached" linker section. 512 513config ARCH_HAS_THREAD_LOCAL_STORAGE 514 bool 515 516# 517# Other architecture related options 518# 519 520config ARCH_HAS_THREAD_ABORT 521 bool 522 523# 524# Hidden CPU family configs 525# 526 527config CPU_HAS_TEE 528 bool 529 help 530 This option is enabled when the CPU has support for Trusted 531 Execution Environment (e.g. when it has a security attribution 532 unit). 533 534config CPU_HAS_DCLS 535 bool 536 help 537 This option is enabled when the processor hardware is configured in 538 Dual-redundant Core Lock-step (DCLS) topology. 539 540config CPU_HAS_FPU 541 bool 542 help 543 This option is enabled when the CPU has hardware floating point 544 unit. 545 546config CPU_HAS_FPU_DOUBLE_PRECISION 547 bool 548 select CPU_HAS_FPU 549 help 550 When enabled, this indicates that the CPU has a double floating point 551 precision unit. 552 553config CPU_HAS_MPU 554 bool 555 help 556 This option is enabled when the CPU has a Memory Protection Unit (MPU). 557 558config CPU_HAS_MMU 559 bool 560 help 561 This hidden option is selected when the CPU has a Memory Management Unit 562 (MMU). 563 564config ARCH_HAS_DEMAND_PAGING 565 bool 566 help 567 This hidden configuration should be selected by the architecture if 568 demand paging is supported. 569 570config ARCH_HAS_RESERVED_PAGE_FRAMES 571 bool 572 help 573 This hidden configuration should be selected by the architecture if 574 certain RAM page frames need to be marked as reserved and never used for 575 memory mappings. The architecture will need to implement 576 arch_reserved_pages_update(). 577 578config ARCH_MAPS_ALL_RAM 579 bool 580 help 581 This hidden option is selected by the architecture to inform the kernel 582 that all RAM is mapped at boot, and not just the bounds of the Zephyr image. 583 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL 584 pointer dereferences. With this enabled, the kernel will not assume that 585 virtual memory addresses past the kernel image are available for mappings, 586 but instead takes into account an entire RAM mapping instead. 587 588 This is typically set by architectures which need direct access to all memory. 589 It is the architecture's responsibility to mark reserved memory regions 590 as such in arch_reserved_pages_update(). 591 592 Although the kernel will not disturb this RAM mapping by re-mapping the associated 593 virtual addresses elsewhere, this is limited to only management of the 594 virtual address space. The kernel's page frame ontology will not consider 595 this mapping at all; non-kernel pages will be considered free (unless marked 596 as reserved) and Z_PAGE_FRAME_MAPPED will not be set. 597 598menuconfig MMU 599 bool "Enable MMU features" 600 depends on CPU_HAS_MMU 601 help 602 This option is enabled when the CPU's memory management unit is active 603 and the arch_mem_map() API is available. 604 605if MMU 606config MMU_PAGE_SIZE 607 hex "Size of smallest granularity MMU page" 608 default 0x1000 609 help 610 Size of memory pages. Varies per MMU but 4K is common. For MMUs that 611 support multiple page sizes, put the smallest one here. 612 613config KERNEL_VM_BASE 614 hex "Virtual address space base address" 615 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 616 help 617 Define the base of the kernel's address space. 618 619 By default, this is the same as the DT_CHOSEN_Z_SRAM physical base SRAM 620 address from DTS, in which case RAM will be identity-mapped. Some 621 architectures may require RAM to be mapped in this way; they may have 622 just one RAM region and doing this makes linking much simpler, as 623 at least when the kernel boots all virtual RAM addresses are the same 624 as their physical address (demand paging at runtime may later modify 625 this for non-pinned page frames). 626 627 Otherwise, if RAM isn't identity-mapped: 628 1. It is the architecture's responsibility to transition the 629 instruction pointer to virtual addresses at early boot before 630 entering the kernel at z_cstart(). 631 2. The underlying architecture may impose constraints on the bounds of 632 the kernel's address space, such as not overlapping physical RAM 633 regions if RAM is not identity-mapped, or the virtual and physical 634 base addresses being aligned to some common value (which allows 635 double-linking of paging structures to make the instruction pointer 636 transition simpler). 637 638 Zephyr does not implement a split address space and if multiple 639 page tables are in use, they all have the same virtual-to-physical 640 mappings (with potentially different permissions). 641 642config KERNEL_VM_OFFSET 643 hex "Kernel offset within address space" 644 default 0 645 help 646 Offset that the kernel image begins within its address space, 647 if this is not the same offset from the beginning of RAM. 648 649 Some care may need to be taken in selecting this value. In certain 650 build-time cases, or when a physical address cannot be looked up 651 in page tables, the equation: 652 653 virt = phys + ((KERNEL_VM_BASE + KERNEL_VM_OFFSET) - 654 (SRAM_BASE_ADDRESS + SRAM_OFFSET)) 655 656 Will be used to convert between physical and virtual addresses for 657 memory that is mapped at boot. 658 659 This uncommon and is only necessary if the beginning of VM and 660 physical memory have dissimilar alignment. 661 662config KERNEL_VM_SIZE 663 hex "Size of kernel address space in bytes" 664 default 0x800000 665 help 666 Size of the kernel's address space. Constraining this helps control 667 how much total memory can be used for page tables. 668 669 The difference between KERNEL_VM_BASE and KERNEL_VM_SIZE indicates the 670 size of the virtual region for runtime memory mappings. This is needed 671 for mapping driver MMIO regions, as well as special RAM mapping use-cases 672 such as VSDO pages, memory mapped thread stacks, and anonymous memory 673 mappings. The kernel itself will be mapped in here as well at boot. 674 675 Systems with very large amounts of memory (such as 512M or more) 676 will want to use a 64-bit build of Zephyr, there are no plans to 677 implement a notion of "high" memory in Zephyr to work around physical 678 RAM size larger than the defined bounds of the virtual address space. 679 680menuconfig DEMAND_PAGING 681 bool "Enable demand paging [EXPERIMENTAL]" 682 depends on ARCH_HAS_DEMAND_PAGING 683 help 684 Enable demand paging. Requires architecture support in how the kernel 685 is linked and the implementation of an eviction algorithm and a 686 backing store for evicted pages. 687 688if DEMAND_PAGING 689config DEMAND_PAGING_ALLOW_IRQ 690 bool "Allow interrupts during page-ins/outs" 691 help 692 Allow interrupts to be serviced while pages are being evicted or 693 retrieved from the backing store. This is much better for system 694 latency, but any code running in interrupt context that page faults 695 will cause a kernel panic. Such code must work with exclusively pinned 696 code and data pages. 697 698 The scheduler is still disabled during this operation. 699 700 If this option is disabled, the page fault servicing logic 701 runs with interrupts disabled for the entire operation. However, 702 ISRs may also page fault. 703 704config DEMAND_PAGING_PAGE_FRAMES_RESERVE 705 int "Number of page frames reserved for paging" 706 default 32 if !LINKER_GENERIC_SECTIONS_PRESENT_AT_BOOT 707 default 0 708 help 709 This sets the number of page frames that will be reserved for 710 paging that do not count towards free memory. This is to 711 ensure that there are some page frames available for paging 712 code and data. Otherwise, it would be possible to exhaust 713 all page frames via anonymous memory mappings. 714 715config DEMAND_PAGING_STATS 716 bool "Gather Demand Paging Statistics" 717 help 718 This enables gathering various statistics related to demand paging, 719 e.g. number of pagefaults. This is useful for tuning eviction 720 algorithms and optimizing backing store. 721 722 Should say N in production system as this is not without cost. 723 724config DEMAND_PAGING_STATS_USING_TIMING_FUNCTIONS 725 bool "Use Timing Functions to Gather Demand Paging Statistics" 726 select TIMING_FUNCTIONS_NEED_AT_BOOT 727 help 728 Use timing functions to gather various demand paging statistics. 729 730config DEMAND_PAGING_THREAD_STATS 731 bool "Gather per Thread Demand Paging Statistics" 732 depends on DEMAND_PAGING_STATS 733 help 734 This enables gathering per thread statistics related to demand 735 paging. 736 737 Should say N in production system as this is not without cost. 738 739config DEMAND_PAGING_TIMING_HISTOGRAM 740 bool "Gather Demand Paging Execution Timing Histogram" 741 depends on DEMAND_PAGING_STATS 742 help 743 This gathers the histogram of execution time on page eviction 744 selection, and backing store page in and page out. 745 746 Should say N in production system as this is not without cost. 747 748config DEMAND_PAGING_TIMING_HISTOGRAM_NUM_BINS 749 int "Number of bins (buckets) in Demand Paging Timing Histogrm" 750 depends on DEMAND_PAGING_TIMING_HISTOGRAM 751 default 10 752 help 753 Defines the number of bins (buckets) in the histogram used for 754 gathering execution timing information for demand paging. 755 756 This requires k_mem_paging_eviction_histogram_bounds[] and 757 k_mem_paging_backing_store_histogram_bounds[] to define 758 the upper bounds for each bin. See kernel/statistics.c for 759 information. 760 761endif # DEMAND_PAGING 762endif # MMU 763 764menuconfig MPU 765 bool "Enable MPU features" 766 depends on CPU_HAS_MPU 767 help 768 This option, when enabled, indicates to the core kernel that an MPU 769 is enabled. 770 771if MPU 772config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT 773 bool 774 help 775 This option is enabled when the MPU requires a power of two alignment 776 and size for MPU regions. 777 778config MPU_REQUIRES_NON_OVERLAPPING_REGIONS 779 bool 780 help 781 This option is enabled when the MPU requires the active (i.e. enabled) 782 MPU regions to be non-overlapping with each other. 783 784config MPU_GAP_FILLING 785 bool "Force MPU to be filling in background memory regions" 786 depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS 787 default y if !USERSPACE 788 help 789 This Kconfig option instructs the MPU driver to enforce 790 a full kernel SRAM partitioning, when it programs the 791 dynamic MPU regions (user thread stack, PRIV stack guard 792 and application memory domains) during context-switch. We 793 allow this to be a configurable option, in order to be able 794 to switch the option off and have an increased number of MPU 795 regions available for application memory domain programming. 796 797 Notes: 798 An increased number of MPU regions should only be required, 799 when building with USERSPACE support. As a result, when we 800 build without USERSPACE support, gap filling should always 801 be required. 802 803 When the option is switched off, access to memory areas not 804 covered by explicit MPU regions is restricted to privileged 805 code on an ARCH-specific basis. Refer to ARCH-specific 806 documentation for more information on how this option is 807 used. 808 809endif # MPU 810 811config SRAM_REGION_PERMISSIONS 812 bool "Assign appropriate permissions to kernel areas in SRAM" 813 depends on MMU || MPU 814 default y 815 help 816 This option indicates that memory protection hardware 817 is present, enabled, and regions have been configured at boot for memory 818 ranges within the kernel image. 819 820 If this option is turned on, certain areas of the kernel image will 821 have the following access policies applied for all threads, including 822 supervisor threads: 823 824 1) All program text will be have read-only, execute memory permission 825 2) All read-only data will have read-only permission, and execution 826 disabled if the hardware supports it. 827 3) All other RAM addresses will have read-write permission, and 828 execution disabled if the hardware supports it. 829 830 Options such as USERSPACE or HW_STACK_PROTECTION may additionally 831 impose additional policies on the memory map, which may be global 832 or local to the current running thread. 833 834 This option may consume additional memory to satisfy memory protection 835 hardware alignment constraints. 836 837 If this option is disabled, the entire kernel will have default memory 838 access permissions set, typically read/write/execute. It may be desirable 839 to turn this off on MMU systems which are using the MMU for demand 840 paging, do not need memory protection, and would rather not use up 841 RAM for the alignment between regions. 842 843menu "Floating Point Options" 844 845config FPU 846 bool "Enable floating point unit (FPU)" 847 depends on CPU_HAS_FPU 848 help 849 This option enables the hardware Floating Point Unit (FPU), in order to 850 support using the floating point registers and instructions. 851 852 When this option is enabled, by default, threads may use the floating 853 point registers only in an exclusive manner, and this usually means that 854 only one thread may perform floating point operations. 855 856 If it is necessary for multiple threads to perform concurrent floating 857 point operations, the "FPU register sharing" option must be enabled to 858 preserve the floating point registers across context switches. 859 860 Note that this option cannot be selected for the platforms that do not 861 include a hardware floating point unit; the floating point support for 862 those platforms is dependent on the availability of the toolchain- 863 provided software floating point library. 864 865config FPU_SHARING 866 bool "FPU register sharing" 867 depends on FPU && MULTITHREADING 868 help 869 This option enables preservation of the hardware floating point registers 870 across context switches to allow multiple threads to perform concurrent 871 floating point operations. 872 873 Note that some compiler configurations may activate a floating point 874 context by generating FP instructions for any thread, and that 875 context must be preserved when switching such threads in and out. 876 The developers can still disable the FP sharing mode in their 877 application projects, and switch to Unshared FP registers mode, 878 if it is guaranteed that the image code does not generate FP 879 instructions outside the single thread context that is allowed 880 to do so. 881 882endmenu 883 884menu "Cache Options" 885 886config CACHE_MANAGEMENT 887 bool "Enable cache management features" 888 help 889 This links in the cache management functions (for d-cache and i-cache 890 where possible). 891 892config DCACHE_LINE_SIZE_DETECT 893 bool "Detect d-cache line size at runtime" 894 depends on CACHE_MANAGEMENT 895 help 896 This option enables querying some architecture-specific hardware for 897 finding the d-cache line size at the expense of taking more memory and 898 code and a slightly increased boot time. 899 900 If the CPU's d-cache line size is known in advance, disable this option and 901 manually enter the value for DCACHE_LINE_SIZE or set it in the DT 902 using the 'd-cache-line-size' property. 903 904config DCACHE_LINE_SIZE 905 int "d-cache line size" if !DCACHE_LINE_SIZE_DETECT 906 depends on CACHE_MANAGEMENT 907 default 0 908 help 909 Size in bytes of a CPU d-cache line. If this is set to 0 the value is 910 obtained from the 'd-cache-line-size' DT property instead if present. 911 912 913 Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. 914 915config ICACHE_LINE_SIZE_DETECT 916 bool "Detect i-cache line size at runtime" 917 depends on CACHE_MANAGEMENT 918 help 919 This option enables querying some architecture-specific hardware for 920 finding the i-cache line size at the expense of taking more memory and 921 code and a slightly increased boot time. 922 923 If the CPU's i-cache line size is known in advance, disable this option and 924 manually enter the value for ICACHE_LINE_SIZE or set it in the DT 925 using the 'i-cache-line-size' property. 926 927config ICACHE_LINE_SIZE 928 int "i-cache line size" if !ICACHE_LINE_SIZE_DETECT 929 depends on CACHE_MANAGEMENT 930 default 0 931 help 932 Size in bytes of a CPU i-cache line. If this is set to 0 the value is 933 obtained from the 'i-cache-line-size' DT property instead if present. 934 935 Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. 936 937choice CACHE_TYPE 938 prompt "Cache type" 939 depends on CACHE_MANAGEMENT 940 default HAS_ARCH_CACHE 941 942config HAS_ARCH_CACHE 943 bool "Integrated cache controller" 944 help 945 "Integrade on-core cache controller" 946 947config HAS_EXTERNAL_CACHE 948 bool "External cache controller" 949 help 950 "External cache controller or cache management system" 951 952endchoice 953 954endmenu 955 956config ARCH 957 string 958 help 959 System architecture string. 960 961config SOC 962 string 963 help 964 SoC name which can be found under soc/<arch>/<soc name>. 965 This option holds the directory name used by the build system to locate 966 the correct linker and header files for the SoC. 967 968config SOC_SERIES 969 string 970 help 971 SoC series name which can be found under soc/<arch>/<family>/<series>. 972 This option holds the directory name used by the build system to locate 973 the correct linker and header files. 974 975config SOC_FAMILY 976 string 977 help 978 SoC family name which can be found under soc/<arch>/<family>. 979 This option holds the directory name used by the build system to locate 980 the correct linker and header files. 981 982config BOARD 983 string 984 help 985 This option holds the name of the board and is used to locate the files 986 related to the board in the source tree (under boards/). 987 The Board is the first location where we search for a linker.ld file, 988 if not found we look for the linker file in 989 soc/<arch>/<family>/<series> 990 991config TOOLCHAIN_HAS_BUILTIN_FFS 992 bool 993 default y if !(64BIT && RISCV) 994 help 995 Hidden option to signal that toolchain has __builtin_ffs*(). 996
