1# IA32-specific X86 subarchitecture options
2
3# Copyright (c) 2019 Intel Corp.
4# SPDX-License-Identifier: Apache-2.0
5
6if !X86_64
7
8config NESTED_INTERRUPTS
9	bool "Nested interrupts"
10	default y
11	help
12	  This option enables support for nested interrupts.
13
14menu "Memory Layout Options"
15
16config IDT_NUM_VECTORS
17	int "Number of IDT vectors"
18	default 256
19	range 32 256
20	help
21	  This option specifies the number of interrupt vector entries in the
22	  Interrupt Descriptor Table (IDT). By default all 256 vectors are
23	  supported in an IDT requiring 2048 bytes of memory.
24
25config SET_GDT
26	bool "Setup GDT as part of boot process"
27	default y
28	help
29	  This option sets up the GDT as part of the boot process. However,
30	  this may conflict with some security scenarios where the GDT is
31	  already appropriately set by an earlier bootloader stage, in which
32	  case this should be disabled. If disabled, the global _gdt pointer
33	  will not be available.
34
35config GDT_DYNAMIC
36	bool "Store GDT in RAM so that it can be modified"
37	depends on SET_GDT
38	help
39	  This option stores the GDT in RAM instead of ROM, so that it may
40	  be modified at runtime at the expense of some memory.
41
42config GDT_RESERVED_NUM_ENTRIES
43	int "Number of reserved GDT entry place holders"
44	depends on GDT_DYNAMIC
45	default 0
46	help
47	  This option defines the number of GDT entry place holders revserved
48	  that can be filled at runtime.
49
50endmenu
51
52menu "Processor Capabilities"
53
54config X86_ENABLE_TSS
55	bool
56	help
57	  This hidden option enables defining a Task State Segment (TSS) for
58	  kernel execution. This is needed to handle double-faults or
59	  do privilege elevation. It also defines a special TSS and handler
60	  for correctly handling double-fault exceptions, instead of just
61	  letting the system triple-fault and reset.
62
63config X86_STACK_PROTECTION
64	bool
65	default y if HW_STACK_PROTECTION
66	select THREAD_STACK_INFO
67	select SET_GDT
68	select GDT_DYNAMIC
69	select X86_ENABLE_TSS
70	help
71	  This option leverages the MMU to cause a system fatal error if the
72	  bounds of the current process stack are overflowed. This is done
73	  by preceding all stack areas with a 4K guard page.
74
75config X86_USERSPACE
76	bool
77	default y if USERSPACE
78	select THREAD_STACK_INFO
79	select SET_GDT
80	select GDT_DYNAMIC
81	select X86_ENABLE_TSS
82	help
83	  This option enables APIs to drop a thread's privileges down to ring 3,
84	  supporting user-level threads that are protected from each other and
85	  from crashing the kernel.
86
87config X86_PAE
88	bool "Use PAE page tables"
89	default y
90	depends on X86_MMU
91	help
92	  If enabled, use PAE-style page tables instead of 32-bit page tables.
93	  The advantage is support for the Execute Disable bit, at a cost of
94	  more memory for paging structures.
95
96menu "Architecture Floating Point Options"
97
98if CPU_HAS_FPU
99
100config SSE
101	bool "SSE registers"
102	depends on FPU
103	select X86_SSE
104	help
105	  This option is deprecated. Please use CONFIG_X86_SSE instead.
106
107config SSE_FP_MATH
108	bool "Compiler-generated SSEx instructions"
109	depends on X86_SSE
110	select X86_SSE_FP_MATH
111	help
112	  This option is deprecated. Please use CONFIG_X86_SSE_FP_MATH instead.
113
114config EAGER_FPU_SHARING
115	bool
116	depends on FPU
117	depends on USERSPACE
118	default y if !X86_NO_LAZY_FP
119	help
120	  This hidden option unconditionally saves/restores the FPU/SIMD
121	  register state on every context switch.
122
123	  Mitigates CVE-2018-3665, but incurs a performance hit.
124
125	  For vulnerable systems that process sensitive information in the
126	  FPU register set, should be used any time CONFIG_FPU is
127	  enabled, regardless if the FPU is used by one thread or multiple.
128
129config LAZY_FPU_SHARING
130	bool
131	depends on FPU
132	depends on !EAGER_FPU_SHARING
133	depends on FPU_SHARING
134	default y if X86_NO_LAZY_FP || !USERSPACE
135	help
136	  This hidden option allows multiple threads to use the floating point
137	  registers, using logic to lazily save/restore the floating point
138	  register state on context switch.
139
140	  On Intel Core processors, may be vulnerable to exploits which allows
141	  malware to read the contents of all floating point registers, see
142	  CVE-2018-3665.
143
144endif # CPU_HAS_FPU
145
146config X86_FP_USE_SOFT_FLOAT
147	bool
148	default y if !FPU
149	help
150	  Enable using software floating point operations.
151
152endmenu
153
154config X86_DYNAMIC_IRQ_STUBS
155	int "Number of dynamic interrupt stubs"
156	depends on DYNAMIC_INTERRUPTS
157	default 4
158	help
159	  Installing interrupt handlers with irq_connect_dynamic() requires
160	  some stub code to be generated at build time, one stub per dynamic
161	  interrupt.
162
163endmenu
164
165config X86_EXCEPTION_STACK_TRACE
166	bool
167	default y
168	depends on EXCEPTION_STACK_TRACE
169	help
170	  Internal config to enable runtime stack traces on fatal exceptions.
171
172config X86_USE_THREAD_LOCAL_STORAGE
173	bool
174	default y if THREAD_LOCAL_STORAGE
175	select SET_GDT
176	select GDT_DYNAMIC
177	help
178	  Internal config to enable thread local storage.
179
180config X86_MFENCE_INSTRUCTION_SUPPORTED
181	bool "X86 MFENCE instruction supported"
182	default y
183	depends on CACHE_MANAGEMENT
184	help
185	  Set n to disable the use of MFENCE instruction in arch_dcache_flush()
186	  for X86 CPUs have CLFLUSH instruction but no MFENCE
187
188config X86_RUNTIME_IRQ_STATS
189	bool
190	help
191	  Add irq runtime statistics to allow runtime profiling irq performance
192	  data with Host tools, enable this and implement platform dependent API
193	  runtime_irq_stats().
194
195endif # !X86_64
196