1# x86 general configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "X86 Architecture Options" 7 depends on X86 8 9config ARCH 10 default "x86" 11 12# 13# CPU Families - the SoC configuration should select the right one. 14# 15 16config CPU_ATOM 17 bool 18 select CPU_HAS_FPU 19 select ARCH_HAS_STACK_PROTECTION if X86_MMU 20 select ARCH_HAS_USERSPACE if X86_MMU 21 select X86_CPU_HAS_MMX 22 select X86_CPU_HAS_SSE 23 select X86_CPU_HAS_SSE2 24 select X86_CPU_HAS_SSE3 25 select CPU_HAS_DCACHE 26 help 27 This option signifies the use of a CPU from the Atom family. 28 29config CPU_APOLLO_LAKE 30 bool 31 select CPU_HAS_FPU 32 select ARCH_HAS_STACK_PROTECTION if X86_MMU 33 select ARCH_HAS_USERSPACE if X86_MMU 34 select X86_MMU 35 select X86_CPU_HAS_MMX 36 select X86_CPU_HAS_SSE 37 select X86_CPU_HAS_SSE2 38 select X86_CPU_HAS_SSE3 39 select X86_CPU_HAS_SSSE3 40 select X86_CPU_HAS_SSE41 41 select X86_CPU_HAS_SSE42 42 select CPU_HAS_DCACHE 43 help 44 This option signifies the use of a CPU from the Apollo Lake family. 45 46config CPU_LAKEMONT 47 bool 48 select CPU_HAS_FPU 49 select ARCH_HAS_STACK_PROTECTION if X86_MMU 50 select ARCH_HAS_USERSPACE if X86_MMU 51 select X86_CPU_HAS_MMX 52 select X86_CPU_HAS_SSE 53 select X86_CPU_HAS_SSE2 54 select X86_CPU_HAS_SSE3 55 select X86_CPU_HAS_SSSE3 56 select CPU_HAS_DCACHE 57 help 58 This option signifies the use of a CPU from the Lakemont family. 59 60# 61# Configuration common to both IA32 and Intel64 sub-architectures. 62# 63 64config X86_64 65 bool "Run in 64-bit mode" 66 select 64BIT 67 select USE_SWITCH 68 select USE_SWITCH_SUPPORTED 69 select SCHED_IPI_SUPPORTED 70 select X86_MMU 71 select X86_CPU_HAS_MMX 72 select X86_CPU_HAS_SSE 73 select X86_CPU_HAS_SSE2 74 select X86_MMX 75 select X86_SSE 76 select X86_SSE2 77 78menu "x86 Features" 79 80config X86_CPU_HAS_MMX 81 bool 82 83config X86_CPU_HAS_SSE 84 bool 85 86config X86_CPU_HAS_SSE2 87 bool 88 89config X86_CPU_HAS_SSE3 90 bool 91 92config X86_CPU_HAS_SSSE3 93 bool 94 95config X86_CPU_HAS_SSE41 96 bool 97 98config X86_CPU_HAS_SSE42 99 bool 100 101config X86_CPU_HAS_SSE4A 102 bool 103 104if FPU || X86_64 105 106config X86_MMX 107 bool "MMX Support" 108 depends on X86_CPU_HAS_MMX 109 help 110 This option enables MMX support, and the use of MMX registers 111 by threads. 112 113config X86_SSE 114 bool "SSE Support" 115 depends on X86_CPU_HAS_SSE 116 help 117 This option enables SSE support, and the use of SSE registers 118 by threads. 119 120config X86_SSE2 121 bool "SSE2 Support" 122 depends on X86_CPU_HAS_SSE2 123 select X86_SSE 124 help 125 This option enables SSE2 support. 126 127config X86_SSE3 128 bool "SSE3 Support" 129 depends on X86_CPU_HAS_SSE3 130 select X86_SSE 131 help 132 This option enables SSE3 support. 133 134config X86_SSSE3 135 bool "SSSE3 (Supplemental SSE3) Support" 136 depends on X86_CPU_HAS_SSSE3 137 select X86_SSE 138 help 139 This option enables Supplemental SSE3 support. 140 141config X86_SSE41 142 bool "SSE4.1 Support" 143 depends on X86_CPU_HAS_SSE41 144 select X86_SSE 145 help 146 This option enables SSE4.1 support. 147 148config X86_SSE42 149 bool "SSE4.2 Support" 150 depends on X86_CPU_HAS_SSE42 151 select X86_SSE 152 help 153 This option enables SSE4.2 support. 154 155config X86_SSE4A 156 bool "SSE4A Support" 157 depends on X86_CPU_HAS_SSE4A 158 select X86_SSE 159 help 160 This option enables SSE4A support. 161 162config X86_SSE_FP_MATH 163 bool "Compiler-generated SSEx instructions for floating point math" 164 depends on X86_SSE 165 help 166 This option allows the compiler to generate SSEx instructions for 167 performing floating point math. This can greatly improve performance 168 when exactly the same operations are to be performed on multiple 169 data objects; however, it can also significantly reduce performance 170 when preemptive task switches occur because of the larger register 171 set that must be saved and restored. 172 173 Disabling this option means that the compiler utilizes only the 174 x87 instruction set for floating point operations. 175 176endif # FPU || X86_64 177 178endmenu 179 180config SRAM_OFFSET 181 default 0x100000 if X86_PC_COMPATIBLE 182 help 183 A lot of x86 that resemble PCs have many reserved physical memory 184 regions within the first megabyte. Specify an offset from the 185 beginning of RAM to load the kernel in physical memory, avoiding these 186 regions. 187 188 Note that this does not include the "locore" which contains real mode 189 bootstrap code within the first 64K of physical memory. 190 191 This value normally need to be page-aligned. 192 193config KERNEL_VM_OFFSET 194 default 0x100000 if MMU 195 196config MAX_IRQ_LINES 197 int "Number of IRQ lines" 198 default 128 199 range 0 224 200 help 201 This option specifies the number of IRQ lines in the system. It 202 determines the size of the _irq_to_interrupt_vector_table, which 203 is used to track the association between vectors and IRQ numbers. 204 205config IRQ_OFFLOAD_VECTOR 206 int "IDT vector to use for IRQ offload" 207 default 33 208 range 32 255 209 depends on IRQ_OFFLOAD 210 211config PIC_DISABLE 212 bool "Disable PIC" 213 help 214 This option disables all interrupts on the legacy i8259 PICs at boot. 215 216choice 217 prompt "Reboot implementation" 218 depends on REBOOT 219 default REBOOT_RST_CNT 220 221 config REBOOT_RST_CNT 222 bool "Reboot via RST_CNT register" 223 help 224 Reboot via the RST_CNT register, going back to BIOS. 225endchoice 226 227config PCIE_MMIO_CFG 228 bool "Use MMIO PCI configuration space access" 229 select ACPI 230 help 231 Selects the use of the memory-mapped PCI Express Extended 232 Configuration Space instead of the traditional 0xCF8/0xCFC 233 IO Port registers. 234 235config KERNEL_VM_SIZE 236 default 0x40000000 if ACPI 237 238config X86_PC_COMPATIBLE 239 bool 240 default y 241 select ARCH_HAS_RESERVED_PAGE_FRAMES 242 select HAS_SRAM_OFFSET 243 help 244 Hidden option to signal building for PC-compatible platforms 245 with BIOS, ACPI, etc. 246 247config X86_MEMMAP 248 bool "Use memory map" 249 select ARCH_HAS_RESERVED_PAGE_FRAMES 250 help 251 Enable the use of memory map to identify regions of memory. 252 253 The memory map can be populated via Multiboot 254 (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or 255 can be manually defined via x86_memmap[]. 256 257config X86_MEMMAP_ENTRIES 258 int "Number of memory map entries" 259 depends on X86_MEMMAP 260 range 1 256 261 default 1 if !MULTIBOOT_MEMMAP 262 default 64 if MULTIBOOT_MEMMAP 263 help 264 Maximum number of memory regions to hold in the memory map. 265 266config MULTIBOOT 267 bool "Generate multiboot header" 268 depends on X86_PC_COMPATIBLE 269 default y 270 help 271 Embed a multiboot header in the output executable. This is used 272 by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe 273 to leave this option on if you're not sure. It only expands the 274 text segment by 12-16 bytes and is typically ignored if not needed. 275 276if MULTIBOOT 277 278config MULTIBOOT_INFO 279 bool "Preserve multiboot information structure" 280 help 281 Multiboot passes a pointer to an information structure to the 282 kernel entry point. Some drivers (e.g., the multiboot framebuffer 283 display driver) need to refer to information in this structure, 284 and so set this option to preserve the data in a permanent location. 285 286config MULTIBOOT_MEMMAP 287 bool "Use multiboot memory map if provided" 288 select MULTIBOOT_INFO 289 select X86_MEMMAP 290 help 291 Use the multiboot memory map if the loader provides one. 292 293endif # MULTIBOOT 294 295config X86_VERY_EARLY_CONSOLE 296 bool "Support very early boot printk" 297 depends on PRINTK 298 help 299 Non-emulated X86 devices often require special hardware to attach 300 a debugger, which may not be easily available. This option adds a 301 very minimal serial driver which gets initialized at the very 302 beginning of z_cstart(), via arch_kernel_init(). This driver enables 303 printk to emit messages to the 16550 UART port 0 instance in device 304 tree. This mini-driver assumes I/O to the UART is done via ports. 305 306config X86_MMU 307 bool "Memory Management Unit" 308 select MMU 309 help 310 This options enables the memory management unit present in x86 311 and creates a set of page tables at boot time that is runtime- 312 mutable. 313 314config X86_COMMON_PAGE_TABLE 315 bool "Use a single page table for all threads" 316 default n 317 depends on USERSPACE 318 depends on !SMP 319 depends on !X86_KPTI 320 help 321 If this option is enabled, userspace memory domains will not have their 322 own page tables. Instead, context switching operations will modify 323 page tables in place. This is much slower, but uses much less RAM 324 for page tables. 325 326config X86_MAX_ADDITIONAL_MEM_DOMAINS 327 int "Maximum number of memory domains" 328 default 3 329 depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE 330 help 331 The initial page tables at boot are pre-allocated, and used for the 332 default memory domain. Instantiation of additional memory domains 333 if common page tables are in use requires a pool of free pinned 334 memory pages for constructing page tables. 335 336 Zephyr test cases assume 3 additional domains can be instantiated. 337 338config X86_EXTRA_PAGE_TABLE_PAGES 339 int "Reserve extra pages in page table" 340 default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS) 341 default 0 342 depends on X86_MMU 343 help 344 The whole page table is pre-allocated at build time and is 345 dependent on the range of address space. This allows reserving 346 extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table 347 so that gen_mmu.py can make use of these extra pages. 348 349 Says 0 unless absolutely sure that this is necessary. 350 351config X86_NO_MELTDOWN 352 bool 353 help 354 This hidden option should be set on a per-SOC basis to indicate that 355 a particular SOC is not vulnerable to the Meltdown CPU vulnerability, 356 as described in CVE-2017-5754. 357 358config X86_NO_SPECTRE_V1 359 bool 360 help 361 This hidden option should be set on a per-SOC basis to indicate that 362 a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and 363 swapgs CPU vulnerabilities as described in CVE-2017-5753, 364 CVE-2018-3693, and CVE-2019-1125. 365 366config X86_NO_SPECTRE_V2 367 bool 368 help 369 This hidden option should be set on a per-SOC basis to indicate that 370 a particular SOC is not vulnerable to the Spectre V2 CPU 371 vulnerability, as described in CVE-2017-5715. 372 373config X86_NO_SPECTRE_V4 374 bool 375 help 376 This hidden option should be set on a per-SOC basis to indicate that 377 a particular SOC is not vulnerable to the Spectre V4 CPU 378 vulnerability, as described in CVE-2018-3639. 379 380config X86_NO_LAZY_FP 381 bool 382 help 383 This hidden option should be set on a per-SOC basis to indicate 384 that a particular SOC is not vulnerable to the Lazy FP CPU 385 vulnerability, as described in CVE-2018-3665. 386 387config X86_NO_SPECULATIVE_VULNERABILITIES 388 bool 389 select X86_NO_MELTDOWN 390 select X86_NO_SPECTRE_V1 391 select X86_NO_SPECTRE_V2 392 select X86_NO_SPECTRE_V4 393 select X86_NO_LAZY_FP 394 help 395 This hidden option should be set on a per-SOC basis to indicate that 396 a particular SOC does not perform any kind of speculative execution, 397 or is a newer chip which is immune to the class of vulnerabilities 398 which exploit speculative execution side channel attacks. 399 400config DISABLE_SSBD 401 bool "Disable Speculative Store Bypass" 402 depends on USERSPACE 403 default y if !X86_NO_SPECTRE_V4 404 help 405 This option will disable Speculative Store Bypass in order to 406 mitigate against certain kinds of side channel attacks. Quoting 407 the "Speculative Execution Side Channels" document, version 2.0: 408 409 When SSBD is set, loads will not execute speculatively 410 until the addresses of all older stores are known. This 411 ensure s that a load does not speculatively consume stale 412 data values due to bypassing an older store on the same 413 logical processor. 414 415 If enabled, this applies to all threads in the system. 416 417 Even if enabled, will have no effect on CPUs that do not 418 require this feature. 419 420config ENABLE_EXTENDED_IBRS 421 bool "Extended IBRS" 422 depends on USERSPACE 423 default y if !X86_NO_SPECTRE_V2 424 help 425 This option will enable the Extended Indirect Branch Restricted 426 Speculation 'always on' feature. This mitigates Indirect Branch 427 Control vulnerabilities (aka Spectre V2). 428 429config X86_BOUNDS_CHECK_BYPASS_MITIGATION 430 bool 431 depends on USERSPACE 432 default y if !X86_NO_SPECTRE_V1 433 select BOUNDS_CHECK_BYPASS_MITIGATION 434 help 435 Hidden config to select arch-independent option to enable 436 Spectre V1 mitigations by default if the CPU is not known 437 to be immune to it. 438 439config X86_KPTI 440 bool "Kernel page table isolation" 441 default y 442 depends on USERSPACE 443 depends on !X86_NO_MELTDOWN 444 help 445 Implements kernel page table isolation to mitigate Meltdown exploits 446 to read Kernel RAM. Incurs a significant performance cost for 447 user thread interrupts and system calls, and significant footprint 448 increase for additional page tables and trampoline stacks. 449 450config X86_EFI 451 bool "EFI" 452 default y 453 depends on BUILD_OUTPUT_EFI 454 help 455 Enable EFI support. This means you build your image with zefi 456 support. See arch/x86/zefi/README.txt for more information. 457 458config X86_EFI_CONSOLE 459 bool 460 depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE 461 select EFI_CONSOLE 462 default y if !UART_CONSOLE 463 help 464 This enables the use of the UEFI console device as the 465 Zephyr printk handler. It requires that no interferences 466 with hardware used by the firmware console (e.g. a UART or 467 framebuffer) happens from Zephyr code, and that all memory 468 used by the firmware environment and its page tables be 469 separate and preserved. In general this is safe to assume, 470 but no automatic checking exists at runtime to verify. 471 Likewise be sure to disable any other console/printk 472 drivers! 473 474source "arch/x86/core/Kconfig.ia32" 475source "arch/x86/core/Kconfig.intel64" 476 477endmenu 478
