1# Copyright (c) 2019 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4menuconfig LOAPIC
5	bool "LOAPIC"
6	depends on X86
7	help
8	  This option selects local APIC as the interrupt controller.
9
10if LOAPIC
11
12config X2APIC
13	bool "Access local APIC in x2APIC mode"
14	help
15	  If your local APIC supports x2APIC mode, turn this on.
16
17config LOAPIC_SPURIOUS_VECTOR
18	bool "Handle LOAPIC spurious interrupts"
19	help
20	  A special situation may occur when a processor raises its task
21	  priority to be greater than or equal to the level of the
22	  interrupt for which the processor INTR signal is currently being
23	  asserted. If at the time the INTA cycle is issued, the
24	  interrupt that was to be dispensed has become masked (programmed
25	  by software), the local APIC will deliver a spurious-interrupt
26	  vector. Dispensing the spurious-interrupt vector does not affect
27	  the ISR, so the handler for this vector should return without an EOI.
28	  From x86 manual Volume 3 Section 10.9.
29
30config LOAPIC_SPURIOUS_VECTOR_ID
31	int "LOAPIC spurious vector ID"
32	default -1
33	depends on LOAPIC_SPURIOUS_VECTOR
34	help
35	  IDT vector to use for spurious LOAPIC interrupts. Note that some
36	  arches (P6, Pentium) ignore the low 4 bits and fix them at 0xF.
37	  If this value is left at -1 the last entry in the IDT will be used.
38
39config IOAPIC
40	bool "IO-APIC"
41	default y
42	depends on DT_HAS_INTEL_IOAPIC_ENABLED
43	help
44	  This option signifies that the target has an IO-APIC device. This
45	  capability allows IO-APIC-dependent code to be included.
46
47config IOAPIC_MASK_RTE
48	bool "Mask out RTE entries on boot"
49	default y
50	depends on IOAPIC
51	help
52	  At boot, mask all IOAPIC RTEs if they may be in an undefined state.
53	  You don't need this if the RTEs are either all guaranteed to be masked
54	  when the OS starts up, or a previous boot stage has done some IOAPIC
55	  configuration that needs to be preserved.
56
57endif # LOAPIC
58