1 /*
2  *  Copyright 2021-2022 NXP
3  *  All rights reserved.
4  *
5  *  SPDX-License-Identifier: BSD-3-Clause
6  */
7 
8 /*
9  * Supported Wi-Fi boards (modules):
10  *     WIFI_88W8801_BOARD_AW_NM191_USD
11  *     WIFI_88W8801_BOARD_AW_NM191MA
12  *     WIFI_IW416_BOARD_AW_AM457_USD
13  *     WIFI_IW416_BOARD_AW_AM457MA
14  *     WIFI_IW416_BOARD_AW_AM510_USD
15  *     WIFI_IW416_BOARD_AW_AM510MA
16  *     WIFI_88W8987_BOARD_AW_CM358_USD
17  *     WIFI_88W8987_BOARD_AW_CM358MA
18  *     WIFI_88W8801_BOARD_MURATA_2DS_USD
19  *     WIFI_88W8801_BOARD_MURATA_2DS_M2
20  *     WIFI_IW416_BOARD_MURATA_1XK_USD
21  *     WIFI_IW416_BOARD_MURATA_1XK_M2
22  *     WIFI_88W8987_BOARD_MURATA_1ZM_USD
23  *     WIFI_88W8987_BOARD_MURATA_1ZM_M2
24  *     WIFI_BOARD_RW610
25  *     WIFI_IW61x_BOARD_RD_USD
26  */
27 #ifndef NOT_DEFINE_DEFAULT_WIFI_MODULE
28 #define WIFI_IW416_BOARD_AW_AM510_USD
29 #endif
30 
31 /* Wi-Fi boards configuration list */
32 
33 /* AzureWave AW-NM191-uSD */
34 #if defined(WIFI_88W8801_BOARD_AW_NM191_USD)
35 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
36 #define SD8801
37 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
38 #define WIFI_BT_USE_USD_INTERFACE
39 #define WLAN_ED_MAC_CTRL                        \
40     {                                           \
41         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \
42     }
43 
44 /* AzureWave AW-NM191MA */
45 #elif defined(WIFI_88W8801_BOARD_AW_NM191MA)
46 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
47 #define SD8801
48 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
49 #define WIFI_BT_USE_M2_INTERFACE
50 #define WLAN_ED_MAC_CTRL                        \
51     {                                           \
52         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x1B \
53     }
54 
55 /* AzureWave AW-AM457-uSD */
56 #elif defined(WIFI_IW416_BOARD_AW_AM457_USD)
57 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
58 #define SD8978
59 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
60 #define WIFI_BT_USE_USD_INTERFACE
61 #define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h"
62 #define WLAN_ED_MAC_CTRL                                                               \
63     {                                                                                  \
64         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
65     }
66 
67 /* AzureWave AW-AM457MA */
68 #elif defined(WIFI_IW416_BOARD_AW_AM457MA)
69 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
70 #define SD8978
71 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
72 #define WIFI_BT_USE_M2_INTERFACE
73 #define OVERRIDE_CALIBRATION_DATA "WIFI_IW416_BOARD_AW_AM457_CAL_DATA_EXT.h"
74 #define WLAN_ED_MAC_CTRL                                                               \
75     {                                                                                  \
76         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
77     }
78 
79 /* AzureWave AW-AM510-uSD */
80 #elif defined(WIFI_IW416_BOARD_AW_AM510_USD)
81 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
82 #define SD8978
83 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
84 #define WIFI_BT_USE_USD_INTERFACE
85 #define WLAN_ED_MAC_CTRL                                                               \
86     {                                                                                  \
87         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
88     }
89 
90 /* AzureWave AW-AM510MA */
91 #elif defined(WIFI_IW416_BOARD_AW_AM510MA)
92 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
93 #define SD8978
94 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
95 #define WIFI_BT_USE_M2_INTERFACE
96 #define WLAN_ED_MAC_CTRL                                                               \
97     {                                                                                  \
98         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
99     }
100 
101 /* AzureWave AW-CM358-uSD */
102 #elif defined(WIFI_88W8987_BOARD_AW_CM358_USD)
103 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
104 #define SD8987
105 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
106 #define SD_TIMING_MAX kSD_TimingDDR50Mode
107 #define WIFI_BT_USE_USD_INTERFACE
108 #define WLAN_ED_MAC_CTRL                                                               \
109     {                                                                                  \
110         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
111     }
112 
113 /* AzureWave AW-CM358MA */
114 #elif defined(WIFI_88W8987_BOARD_AW_CM358MA)
115 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
116 #define SD8987
117 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
118 #define SD_TIMING_MAX kSD_TimingDDR50Mode
119 #define WIFI_BT_USE_M2_INTERFACE
120 #define WLAN_ED_MAC_CTRL                                                               \
121     {                                                                                  \
122         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x9, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0xC \
123     }
124 
125 /* Murata 2DS + Murata uSD-M.2 adapter */
126 #elif defined(WIFI_88W8801_BOARD_MURATA_2DS_USD)
127 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h"
128 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h"
129 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h"
130 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h"
131 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h"
132 #define SD8801
133 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
134 #define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode
135 #define WIFI_BT_USE_USD_INTERFACE
136 #define WLAN_ED_MAC_CTRL                        \
137     {                                           \
138         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \
139     }
140 
141 /* Murata 2DS */
142 #elif defined(WIFI_88W8801_BOARD_MURATA_2DS_M2)
143 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_CA.h"
144 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_EU.h"
145 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_JP.h"
146 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_US.h"
147 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_2DS_WW.h"
148 #define SD8801
149 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
150 #define SD_TIMING_MAX kSD_TimingSDR25HighSpeedMode
151 #define WIFI_BT_USE_M2_INTERFACE
152 #define WLAN_ED_MAC_CTRL                        \
153     {                                           \
154         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0E \
155     }
156 
157 /* Murata 1XK + Murata uSD-M.2 adapter */
158 #elif defined(WIFI_IW416_BOARD_MURATA_1XK_USD)
159 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h"
160 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h"
161 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h"
162 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h"
163 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h"
164 #define SD8978
165 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
166 #define SD_TIMING_MAX kSD_TimingDDR50Mode
167 #define WIFI_BT_USE_USD_INTERFACE
168 #define WLAN_ED_MAC_CTRL                                                               \
169     {                                                                                  \
170         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \
171     }
172 
173 /* Murata 1XK */
174 #elif defined(WIFI_IW416_BOARD_MURATA_1XK_M2)
175 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_CA.h"
176 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_EU.h"
177 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_JP.h"
178 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_US.h"
179 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1XK_WW.h"
180 #define SD8978
181 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
182 #define SD_TIMING_MAX kSD_TimingDDR50Mode
183 #define WIFI_BT_USE_M2_INTERFACE
184 #define WLAN_ED_MAC_CTRL                                                               \
185     {                                                                                  \
186         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x0, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \
187     }
188 
189 /* Murata 1ZM + Murata uSD-M.2 adapter */
190 #elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_USD)
191 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h"
192 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h"
193 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h"
194 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h"
195 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h"
196 #define SD8987
197 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
198 #define SD_TIMING_MAX kSD_TimingDDR50Mode
199 #define WIFI_BT_USE_USD_INTERFACE
200 #define WLAN_ED_MAC_CTRL                                                               \
201     {                                                                                  \
202         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \
203     }
204 
205 /* Murata 1ZM */
206 #elif defined(WIFI_88W8987_BOARD_MURATA_1ZM_M2)
207 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_CA.h"
208 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_EU.h"
209 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_JP.h"
210 // #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_US.h"
211 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_murata_1ZM_WW.h"
212 #define SD8987
213 #define SDMMCHOST_OPERATION_VOLTAGE_1V8
214 #define SD_TIMING_MAX kSD_TimingDDR50Mode
215 #define WIFI_BT_USE_M2_INTERFACE
216 #define WLAN_ED_MAC_CTRL                                                               \
217     {                                                                                  \
218         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \
219     }
220 #elif defined(WIFI_BOARD_RW610)
221 #define RW610
222 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW_rw610.h"
223 
224 /* USD Firecrest module */
225 #elif defined(WIFI_IW61x_BOARD_RD_USD)
226 #define WIFI_BT_TX_PWR_LIMITS "wlan_txpwrlimit_cfg_WW.h"
227 #define IW61x
228 #define SDMMCHOST_OPERATION_VOLTAGE_3V3
229 #define CONFIG_WIFI_FEATURES 1
230 #define ENABLE_HOST_SLEEP    1
231 #define ENABLE_OFFLOAD       1
232 #define WLAN_ED_MAC_CTRL                                                               \
233     {                                                                                  \
234         .ed_ctrl_2g = 0x1, .ed_offset_2g = 0x6, .ed_ctrl_5g = 0x1, .ed_offset_5g = 0x6 \
235     }
236 #else
237 #error "Please define macro related to wifi board"
238 #endif
239 
240 #include "wifi_config.h"
241