1# General architecture configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2015 Intel Corporation 5# Copyright (c) 2016 Cadence Design Systems, Inc. 6# SPDX-License-Identifier: Apache-2.0 7 8# Include these first so that any properties (e.g. defaults) below can be 9# overridden (by defining symbols in multiple locations) 10 11# Note: $ARCH might be a glob pattern 12source "$(ARCH_DIR)/$(ARCH)/Kconfig" 13 14# Architecture symbols 15# 16# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that, 17# by SOC_*. 18 19config ARC 20 bool 21 select ARCH_IS_SET 22 imply XIP 23 select ARCH_HAS_THREAD_LOCAL_STORAGE 24 select ARCH_SUPPORTS_ROM_START 25 help 26 ARC architecture 27 28config ARM 29 bool 30 select ARCH_IS_SET 31 select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M 32 # FIXME: current state of the code for all ARM requires this, but 33 # is really only necessary for Cortex-M with ARM MPU! 34 select GEN_PRIV_STACKS 35 select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A 36 select BARRIER_OPERATIONS_ARCH 37 help 38 ARM architecture 39 40config ARM64 41 bool 42 select ARCH_IS_SET 43 select 64BIT 44 select ARCH_SUPPORTS_COREDUMP 45 select HAS_ARM_SMCCC 46 select ARCH_HAS_THREAD_LOCAL_STORAGE 47 select USE_SWITCH 48 select USE_SWITCH_SUPPORTED 49 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 50 select BARRIER_OPERATIONS_ARCH 51 help 52 ARM64 (AArch64) architecture 53 54config MIPS 55 bool 56 select ARCH_IS_SET 57 select ATOMIC_OPERATIONS_C 58 help 59 MIPS architecture 60 61config SPARC 62 bool 63 select ARCH_IS_SET 64 select USE_SWITCH 65 select USE_SWITCH_SUPPORTED 66 select BIG_ENDIAN 67 select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA 68 select ATOMIC_OPERATIONS_C if !SPARC_CASA 69 select ARCH_HAS_THREAD_LOCAL_STORAGE 70 select ARCH_HAS_EXTRA_EXCEPTION_INFO 71 help 72 SPARC architecture 73 74config X86 75 bool 76 select ARCH_IS_SET 77 select ATOMIC_OPERATIONS_BUILTIN 78 select ARCH_SUPPORTS_COREDUMP 79 select ARCH_SUPPORTS_ROM_START if !X86_64 80 select CPU_HAS_MMU 81 select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE 82 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 83 select ARCH_HAS_GDBSTUB if !X86_64 84 select ARCH_HAS_TIMING_FUNCTIONS 85 select ARCH_HAS_THREAD_LOCAL_STORAGE 86 select ARCH_HAS_DEMAND_PAGING 87 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 88 select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ 89 && !BOARD_HAS_TIMING_FUNCTIONS \ 90 && !SOC_HAS_TIMING_FUNCTIONS 91 select ARCH_HAS_STACK_CANARIES_TLS 92 help 93 x86 architecture 94 95config NIOS2 96 bool 97 select ARCH_IS_SET 98 select ATOMIC_OPERATIONS_C 99 imply XIP 100 select ARCH_HAS_TIMING_FUNCTIONS 101 help 102 Nios II Gen 2 architecture 103 104config RISCV 105 bool 106 select ARCH_IS_SET 107 select ARCH_SUPPORTS_COREDUMP 108 select ARCH_SUPPORTS_ROM_START if !SOC_SERIES_ESP32C3 109 select ARCH_HAS_CODE_DATA_RELOCATION 110 select ARCH_HAS_THREAD_LOCAL_STORAGE 111 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 112 select USE_SWITCH_SUPPORTED 113 select USE_SWITCH 114 select SCHED_IPI_SUPPORTED if SMP 115 select BARRIER_OPERATIONS_BUILTIN 116 imply XIP 117 help 118 RISCV architecture 119 120config XTENSA 121 bool 122 select ARCH_IS_SET 123 select USE_SWITCH 124 select USE_SWITCH_SUPPORTED 125 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 126 select ARCH_HAS_CODE_DATA_RELOCATION 127 select ARCH_HAS_TIMING_FUNCTIONS 128 select ARCH_MEM_DOMAIN_DATA if USERSPACE 129 help 130 Xtensa architecture 131 132config ARCH_POSIX 133 bool 134 select ARCH_IS_SET 135 select ATOMIC_OPERATIONS_BUILTIN 136 select ARCH_HAS_CUSTOM_SWAP_TO_MAIN 137 select ARCH_HAS_CUSTOM_BUSY_WAIT 138 select ARCH_HAS_THREAD_ABORT 139 select NATIVE_BUILD 140 select HAS_COVERAGE_SUPPORT 141 select BARRIER_OPERATIONS_BUILTIN 142 # POSIX arch based targets get their memory cleared on entry by the host OS 143 select SKIP_BSS_CLEAR 144 help 145 POSIX (native) architecture 146 147config ARCH_IS_SET 148 bool 149 help 150 Helper symbol to detect SoCs forgetting to select one of the arch 151 symbols above. See the top-level CMakeLists.txt. 152 153menu "General Architecture Options" 154 155source "arch/common/Kconfig" 156 157module = ARCH 158module-str = arch 159source "subsys/logging/Kconfig.template.log_config" 160 161config BIG_ENDIAN 162 bool 163 help 164 This option tells the build system that the target system is big-endian. 165 Little-endian architecture is the default and should leave this option 166 unselected. This option is selected by arch/$ARCH/Kconfig, 167 soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid 168 modifying it. The option is used to select linker script OUTPUT_FORMAT 169 and command line option for gen_isr_tables.py. 170 171config LITTLE_ENDIAN 172 # Hidden Kconfig option representing the default little-endian architecture 173 # This is just the opposite of BIG_ENDIAN and is used for non-negative 174 # conditional compilation 175 bool 176 depends on !BIG_ENDIAN 177 default y 178 179config 64BIT 180 bool 181 help 182 This option tells the build system that the target system is 183 using a 64-bit address space, meaning that pointer and long types 184 are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, 185 soc/**/Kconfig, or boards/**/Kconfig and the user should generally 186 avoid modifying it. 187 188# Workaround for not being able to have commas in macro arguments 189DT_CHOSEN_Z_SRAM := zephyr,sram 190 191config SRAM_SIZE 192 int "SRAM Size in kB" 193 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) 194 help 195 The SRAM size in kB. The default value comes from /chosen/zephyr,sram in 196 devicetree. The user should generally avoid changing it via menuconfig or 197 in configuration files. 198 199config SRAM_BASE_ADDRESS 200 hex "SRAM Base Address" 201 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 202 help 203 The SRAM base address. The default value comes from from 204 /chosen/zephyr,sram in devicetree. The user should generally avoid 205 changing it via menuconfig or in configuration files. 206 207if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV 208 209# Workaround for not being able to have commas in macro arguments 210DT_CHOSEN_Z_FLASH := zephyr,flash 211 212config FLASH_SIZE 213 int "Flash Size in kB" 214 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM 215 help 216 This option specifies the size of the flash in kB. It is normally set by 217 the board's defconfig file and the user should generally avoid modifying 218 it via the menu configuration. 219 220config FLASH_BASE_ADDRESS 221 hex "Flash Base Address" 222 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM 223 help 224 This option specifies the base address of the flash on the board. It is 225 normally set by the board's defconfig file and the user should generally 226 avoid modifying it via the menu configuration. 227 228endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV 229 230if ARCH_HAS_TRUSTED_EXECUTION 231 232config TRUSTED_EXECUTION_SECURE 233 bool "Trusted Execution: Secure firmware image" 234 help 235 Select this option to enable building a Secure firmware 236 image for a platform that supports Trusted Execution. A 237 Secure firmware image will execute in Secure state. It may 238 allow the CPU to execute in Non-Secure (Normal) state. 239 Therefore, a Secure firmware image shall be able to 240 configure security attributions of CPU resources (memory 241 areas, peripherals, interrupts, etc.) as well as to handle 242 faults, related to security violations. It may optionally 243 allow certain functions to be called from the Non-Secure 244 (Normal) domain. 245 246config TRUSTED_EXECUTION_NONSECURE 247 depends on !TRUSTED_EXECUTION_SECURE 248 bool "Trusted Execution: Non-Secure firmware image" 249 help 250 Select this option to enable building a Non-Secure 251 firmware image for a platform that supports Trusted 252 Execution. A Non-Secure firmware image will execute 253 in Non-Secure (Normal) state. Therefore, it shall not 254 access CPU resources (memory areas, peripherals, 255 interrupts etc.) belonging to the Secure domain. 256 257endif # ARCH_HAS_TRUSTED_EXECUTION 258 259config HW_STACK_PROTECTION 260 bool "Hardware Stack Protection" 261 depends on ARCH_HAS_STACK_PROTECTION 262 help 263 Select this option to enable hardware-based platform features to 264 catch stack overflows when the system is running in privileged 265 mode. If CONFIG_USERSPACE is not enabled, the system is always 266 running in privileged mode. 267 268 Note that this does not necessarily prevent corruption and assertions 269 about the overall system state when a fault is triggered cannot be 270 made. 271 272config USERSPACE 273 bool "User mode threads" 274 depends on ARCH_HAS_USERSPACE 275 depends on RUNTIME_ERROR_CHECKS 276 depends on SRAM_REGION_PERMISSIONS 277 select THREAD_STACK_INFO 278 select LINKER_USE_NO_RELAX 279 help 280 When enabled, threads may be created or dropped down to user mode, 281 which has significantly restricted permissions and must interact 282 with the kernel via system calls. See Zephyr documentation for more 283 details about this feature. 284 285 If a user thread overflows its stack, this will be caught and the 286 kernel itself will be shielded from harm. Enabling this option 287 may or may not catch stack overflows when the system is in 288 privileged mode or handling a system call; to ensure these are always 289 caught, enable CONFIG_HW_STACK_PROTECTION. 290 291config PRIVILEGED_STACK_SIZE 292 int "Size of privileged stack" 293 default 2048 if EMUL 294 default 1024 295 depends on ARCH_HAS_USERSPACE 296 help 297 This option sets the privileged stack region size that will be used 298 in addition to the user mode thread stack. During normal execution, 299 this region will be inaccessible from user mode. During system calls, 300 this region will be utilized by the system call. This value must be 301 a multiple of the minimum stack alignment. 302 303config KOBJECT_TEXT_AREA 304 int "Size of kobject text area" 305 default 512 if COVERAGE_GCOV 306 default 512 if NO_OPTIMIZATIONS 307 default 512 if STACK_CANARIES && RISCV 308 default 256 309 depends on ARCH_HAS_USERSPACE 310 help 311 Size of kernel object text area. Used in linker script. 312 313config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 314 int "Reserve extra kobject data area (in percentage)" 315 default 100 316 depends on ARCH_HAS_USERSPACE 317 help 318 Multiplication factor used to calculate the size of placeholder to 319 reserve space for kobject metadata hash table. The hash table is 320 generated via gperf is highly dependent on the absolute addresses of 321 kobjects which might change between prebuilts. To reserve enough 322 space for the hash table during final linking passes to keep 323 kobjects in same place, the size of reserved space is calculated 324 from the first prebuilt plus additional space calculated with 325 this percentage (of the kobject data area in first prebuilt). 326 327config KOBJECT_RODATA_AREA_EXTRA_BYTES 328 int "Reserve extra bytes for kobject rodata area" 329 default 16 330 depends on ARCH_HAS_USERSPACE 331 help 332 Reserve a few more bytes for the RODATA region for kobject metadata. 333 This is to account for the uncertainty of tables generated by gperf. 334 335config GEN_PRIV_STACKS 336 bool 337 help 338 Selected if the architecture requires that privilege elevation stacks 339 be allocated in a separate memory area. This is typical of arches 340 whose MPUs require regions to be power-of-two aligned/sized. 341 342 FIXME: This should be removed and replaced with checks against 343 CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC 344 changes will be necessary for this. 345 346config STACK_GROWS_UP 347 bool "Stack grows towards higher memory addresses" 348 help 349 Select this option if the architecture has upward growing thread 350 stacks. This is not common. 351 352config NO_UNUSED_STACK_INSPECTION 353 bool 354 help 355 Selected if the architecture will generate a fault if unused stack 356 memory is examined, which is the region between the current stack 357 pointer and the deepest available address in the current stack 358 region. 359 360config MAX_THREAD_BYTES 361 int "Bytes to use when tracking object thread permissions" 362 default 2 363 depends on USERSPACE 364 help 365 Every kernel object will have an associated bitfield to store 366 thread permissions for that object. This controls the size of the 367 bitfield (in bytes) and imposes a limit on how many threads can 368 be created in the system. 369 370config DYNAMIC_OBJECTS 371 bool "Allow kernel objects to be allocated at runtime" 372 depends on USERSPACE 373 help 374 Enabling this option allows for kernel objects to be requested from 375 the calling thread's resource pool, at a slight cost in performance 376 due to the supplemental run-time tables required to validate such 377 objects. 378 379 Objects allocated in this way can be freed with a supervisor-only 380 API call, or when the number of references to that object drops to 381 zero. 382 383config NOCACHE_MEMORY 384 bool "Support for uncached memory" 385 depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT 386 help 387 Add a "nocache" read-write memory section that is configured to 388 not be cached. This memory section can be used to perform DMA 389 transfers when cache coherence issues are not optimal or can not 390 be solved using cache maintenance operations. 391 392menu "Interrupt Configuration" 393 394config ISR_TABLES_LOCAL_DECLARATION_SUPPORTED 395 bool 396 default y 397 # Userspace is currently not supported 398 depends on !USERSPACE 399 # List of currently supported architectures 400 depends on ARM || ARM64 401 # List of currently supported toolchains 402 depends on "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "zephyr" || "$(ZEPHYR_TOOLCHAIN_VARIANT)" = "gnuarmemb" 403 404config ISR_TABLES_LOCAL_DECLARATION 405 bool "ISR tables created locally and placed by linker [EXPERIMENTAL]" 406 depends on ISR_TABLES_LOCAL_DECLARATION_SUPPORTED 407 select EXPERIMENTAL 408 help 409 Enable new scheme of interrupt tables generation. 410 This is totally different generator that would create tables entries locally 411 where the IRQ_CONNECT macro is called and then use the linker script to position it 412 in the right place in memory. 413 The most important advantage of such approach is that the generated interrupt tables 414 are LTO compatible. 415 The drawback is that the support on the architecture port is required. 416 417config DYNAMIC_INTERRUPTS 418 bool "Installation of IRQs at runtime" 419 help 420 Enable installation of interrupts at runtime, which will move some 421 interrupt-related data structures to RAM instead of ROM, and 422 on some architectures increase code size. 423 424config SHARED_INTERRUPTS 425 bool "Set this to enable support for shared interrupts" 426 depends on GEN_SW_ISR_TABLE 427 select EXPERIMENTAL 428 help 429 Set this to enable support for shared interrupts. Use this with 430 caution as enabling this will increase the image size by a 431 non-negligible amount. 432 433config SHARED_IRQ_MAX_NUM_CLIENTS 434 int "Maximum number of clients allowed per shared interrupt" 435 default 2 436 depends on SHARED_INTERRUPTS 437 help 438 This option controls the maximum number of clients allowed 439 per shared interrupt. Set this according to your needs. 440 441config GEN_ISR_TABLES 442 bool "Use generated IRQ tables" 443 help 444 This option controls whether a platform uses the gen_isr_tables 445 script to generate its interrupt tables. This mechanism will create 446 an appropriate hardware vector table and/or software IRQ table. 447 448config GEN_IRQ_VECTOR_TABLE 449 bool "Generate an interrupt vector table" 450 default y 451 depends on GEN_ISR_TABLES 452 help 453 This option controls whether a platform using gen_isr_tables 454 needs an interrupt vector table created. Only disable this if the 455 platform does not use a vector table at all, or requires the vector 456 table to be in a format that is not an array of function pointers 457 indexed by IRQ line. In the latter case, the vector table must be 458 supplied by the application or architecture code. 459 460config ARCH_IRQ_VECTOR_TABLE_ALIGN 461 int "Alignment size of the interrupt vector table" 462 default 4 463 depends on GEN_IRQ_VECTOR_TABLE 464 help 465 This option controls alignment size of generated 466 _irq_vector_table. Some architecture needs an IRQ vector table 467 to be aligned to architecture specific size. The default 468 size is 0 for no alignment. 469 470choice IRQ_VECTOR_TABLE_TYPE 471 prompt "IRQ vector table type" 472 depends on GEN_IRQ_VECTOR_TABLE 473 default IRQ_VECTOR_TABLE_JUMP_BY_CODE if (RISCV && !RISCV_HAS_CLIC) 474 default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 475 476config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 477 bool "Jump by address" 478 help 479 The IRQ vector table contains the address of the interrupt handler. 480 481config IRQ_VECTOR_TABLE_JUMP_BY_CODE 482 bool "Jump by code" 483 help 484 The IRQ vector table contains the opcode of a jump instruction to the 485 interrupt handler address. 486 487endchoice 488 489config GEN_SW_ISR_TABLE 490 bool "Generate a software ISR table" 491 default y 492 depends on GEN_ISR_TABLES 493 help 494 This option controls whether a platform using gen_isr_tables 495 needs a software ISR table table created. This is an array of struct 496 _isr_table_entry containing the interrupt service routine and supplied 497 parameter. 498 499config ARCH_SW_ISR_TABLE_ALIGN 500 int "Alignment size of a software ISR table" 501 default 64 if RISCV_HAS_CLIC 502 default 4 503 depends on GEN_SW_ISR_TABLE 504 help 505 This option controls alignment size of generated 506 _sw_isr_table. Some architecture needs a software ISR table 507 to be aligned to architecture specific size. The default 508 size is 4. 509 510config GEN_IRQ_START_VECTOR 511 int 512 default 0 513 depends on GEN_ISR_TABLES 514 help 515 On some architectures, part of the vector table may be reserved for 516 system exceptions and is declared separately from the tables 517 created by gen_isr_tables.py. When creating these tables, this value 518 will be subtracted from CONFIG_NUM_IRQS to properly size them. 519 This is a hidden option which needs to be set per architecture and 520 left alone. 521 522config IRQ_OFFLOAD 523 bool "IRQ offload" 524 depends on TEST 525 help 526 Enable irq_offload() API which allows functions to be synchronously 527 run in interrupt context. Only useful for test cases that need 528 to validate the correctness of kernel objects in IRQ context. 529 530config IRQ_OFFLOAD_NESTED 531 bool "irq_offload() supports nested IRQs" 532 depends on IRQ_OFFLOAD 533 help 534 When set by the arch layer, indicates that irq_offload() may 535 legally be called in interrupt context to cause a 536 synchronous nested interrupt on the current CPU. Not all 537 hardware is capable. 538 539config EXCEPTION_DEBUG 540 bool "Unhandled exception debugging" 541 default y 542 depends on PRINTK || LOG 543 help 544 Install handlers for various CPU exception/trap vectors to 545 make debugging them easier, at a small expense in code size. 546 This prints out the specific exception vector and any associated 547 error codes. 548 549config EXTRA_EXCEPTION_INFO 550 bool "Collect extra exception info" 551 depends on ARCH_HAS_EXTRA_EXCEPTION_INFO 552 help 553 This option enables the collection of extra information, such as 554 register state, when a fault occurs. This information can be useful 555 to collect for post-mortem analysis and debug of issues. 556 557config SIMPLIFIED_EXCEPTION_CODES 558 bool "Convert arch specific exception codes to K_ERR_CPU_EXCEPTION" 559 default y if ZTEST 560 help 561 The same piece of faulty code (NULL dereference, etc) can result in 562 a multitude of potential exception codes at the CPU level, depending 563 upon whether addresses exist, an MPU is configured, the particular 564 implementation of the CPU or any number of other reasons. Enabling 565 this option collapses all the architecture specific exception codes 566 down to the generic K_ERR_CPU_EXCEPTION, which makes testing code 567 much more portable. 568 569endmenu # Interrupt configuration 570 571config INIT_ARCH_HW_AT_BOOT 572 bool "Initialize internal architecture state at boot" 573 depends on ARCH_SUPPORTS_ARCH_HW_INIT 574 help 575 This option instructs Zephyr to force the initialization 576 of the internal architectural state (for example ARCH-level 577 HW registers and system control blocks) during boot to 578 the reset values as specified by the corresponding 579 architecture manual. The option is useful when the Zephyr 580 firmware image is chain-loaded, for example, by a debugger 581 or a bootloader, and we need to guarantee that the internal 582 states of the architecture core blocks are restored to the 583 reset values (as specified by the architecture). 584 585 Note: the functionality is architecture-specific. For the 586 implementation details refer to each architecture where 587 this feature is supported. 588 589endmenu 590 591# 592# Architecture Capabilities 593# 594 595config ARCH_HAS_SINGLE_THREAD_SUPPORT 596 bool 597 598config ARCH_HAS_TIMING_FUNCTIONS 599 bool 600 601config ARCH_HAS_TRUSTED_EXECUTION 602 bool 603 604config ARCH_HAS_STACK_PROTECTION 605 bool 606 607config ARCH_HAS_USERSPACE 608 bool 609 610config ARCH_HAS_EXECUTABLE_PAGE_BIT 611 bool 612 613config ARCH_HAS_NOCACHE_MEMORY_SUPPORT 614 bool 615 616config ARCH_HAS_RAMFUNC_SUPPORT 617 bool 618 619config ARCH_HAS_NESTED_EXCEPTION_DETECTION 620 bool 621 622config ARCH_SUPPORTS_COREDUMP 623 bool 624 625config ARCH_SUPPORTS_ARCH_HW_INIT 626 bool 627 628config ARCH_SUPPORTS_ROM_START 629 bool 630 631config ARCH_HAS_EXTRA_EXCEPTION_INFO 632 bool 633 634config ARCH_HAS_GDBSTUB 635 bool 636 637config ARCH_HAS_COHERENCE 638 bool 639 help 640 When selected, the architecture supports the 641 arch_mem_coherent() API and can link into incoherent/cached 642 memory using the ".cached" linker section. 643 644config ARCH_HAS_THREAD_LOCAL_STORAGE 645 bool 646 647config ARCH_HAS_SUSPEND_TO_RAM 648 bool 649 help 650 When selected, the architecture supports suspend-to-RAM (S2RAM). 651 652config ARCH_HAS_STACK_CANARIES_TLS 653 bool 654 655# 656# Other architecture related options 657# 658 659config ARCH_HAS_THREAD_ABORT 660 bool 661 662config ARCH_HAS_CODE_DATA_RELOCATION 663 bool 664 help 665 When selected, the architecture/SoC implements support for 666 CODE_DATA_RELOCATION in its linker scripts. 667 668# 669# Hidden CPU family configs 670# 671 672config CPU_HAS_TEE 673 bool 674 help 675 This option is enabled when the CPU has support for Trusted 676 Execution Environment (e.g. when it has a security attribution 677 unit). 678 679config CPU_HAS_DCLS 680 bool 681 help 682 This option is enabled when the processor hardware has support for 683 Dual-redundant Core Lock-step (DCLS) topology. 684 685config CPU_HAS_FPU 686 bool 687 help 688 This option is enabled when the CPU has hardware floating point 689 unit. 690 691config CPU_HAS_DSP 692 bool 693 help 694 This option is enabled when the CPU has hardware DSP unit. 695 696config CPU_HAS_FPU_DOUBLE_PRECISION 697 bool 698 select CPU_HAS_FPU 699 help 700 When enabled, this indicates that the CPU has a double floating point 701 precision unit. 702 703config CPU_HAS_MPU 704 bool 705 help 706 This option is enabled when the CPU has a Memory Protection Unit (MPU). 707 708config CPU_HAS_MMU 709 bool 710 help 711 This hidden option is selected when the CPU has a Memory Management Unit 712 (MMU). 713 714config ARCH_HAS_DEMAND_PAGING 715 bool 716 help 717 This hidden configuration should be selected by the architecture if 718 demand paging is supported. 719 720config ARCH_HAS_RESERVED_PAGE_FRAMES 721 bool 722 help 723 This hidden configuration should be selected by the architecture if 724 certain RAM page frames need to be marked as reserved and never used for 725 memory mappings. The architecture will need to implement 726 arch_reserved_pages_update(). 727 728config CPU_HAS_DCACHE 729 bool 730 help 731 This hidden configuration should be selected when the CPU has a d-cache. 732 733config CPU_CACHE_INCOHERENT 734 bool 735 help 736 This hidden configuration should be selected when the CPU has 737 incoherent cache. This applies to intra-CPU multiprocessing 738 incoherence and makes only sense when MP_NUM_CPUS > 1. 739 740config CPU_HAS_ICACHE 741 bool 742 help 743 This hidden configuration should be selected when the CPU has an i-cache. 744 745config ARCH_MAPS_ALL_RAM 746 bool 747 help 748 This hidden option is selected by the architecture to inform the kernel 749 that all RAM is mapped at boot, and not just the bounds of the Zephyr image. 750 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL 751 pointer dereferences. With this enabled, the kernel will not assume that 752 virtual memory addresses past the kernel image are available for mappings, 753 but instead takes into account an entire RAM mapping instead. 754 755 This is typically set by architectures which need direct access to all memory. 756 It is the architecture's responsibility to mark reserved memory regions 757 as such in arch_reserved_pages_update(). 758 759 Although the kernel will not disturb this RAM mapping by re-mapping the associated 760 virtual addresses elsewhere, this is limited to only management of the 761 virtual address space. The kernel's page frame ontology will not consider 762 this mapping at all; non-kernel pages will be considered free (unless marked 763 as reserved) and Z_PAGE_FRAME_MAPPED will not be set. 764 765config DCLS 766 bool "Processor is configured in DCLS mode" 767 depends on CPU_HAS_DCLS 768 default y 769 help 770 This option is enabled when the processor hardware is configured in 771 Dual-redundant Core Lock-step (DCLS) topology. For the processor that 772 supports DCLS, but is configured in split-lock mode (by default or 773 changed at flash time), this option should be disabled. 774 775menuconfig MPU 776 bool "MPU features" 777 depends on CPU_HAS_MPU 778 help 779 This option, when enabled, indicates to the core kernel that an MPU 780 is enabled. 781 782if MPU 783module = MPU 784module-str = mpu 785source "subsys/logging/Kconfig.template.log_config" 786 787config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT 788 bool 789 help 790 This option is enabled when the MPU requires a power of two alignment 791 and size for MPU regions. 792 793config MPU_REQUIRES_NON_OVERLAPPING_REGIONS 794 bool 795 help 796 This option is enabled when the MPU requires the active (i.e. enabled) 797 MPU regions to be non-overlapping with each other. 798 799config MPU_GAP_FILLING 800 bool "Force MPU to be filling in background memory regions" 801 depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS 802 default y if !USERSPACE 803 help 804 This Kconfig option instructs the MPU driver to enforce 805 a full kernel SRAM partitioning, when it programs the 806 dynamic MPU regions (user thread stack, PRIV stack guard 807 and application memory domains) during context-switch. We 808 allow this to be a configurable option, in order to be able 809 to switch the option off and have an increased number of MPU 810 regions available for application memory domain programming. 811 812 Notes: 813 An increased number of MPU regions should only be required, 814 when building with USERSPACE support. As a result, when we 815 build without USERSPACE support, gap filling should always 816 be required. 817 818 When the option is switched off, access to memory areas not 819 covered by explicit MPU regions is restricted to privileged 820 code on an ARCH-specific basis. Refer to ARCH-specific 821 documentation for more information on how this option is 822 used. 823 824endif # MPU 825 826config SRAM_REGION_PERMISSIONS 827 bool "Assign appropriate permissions to kernel areas in SRAM" 828 depends on MMU || MPU 829 default y 830 help 831 This option indicates that memory protection hardware 832 is present, enabled, and regions have been configured at boot for memory 833 ranges within the kernel image. 834 835 If this option is turned on, certain areas of the kernel image will 836 have the following access policies applied for all threads, including 837 supervisor threads: 838 839 1) All program text will be have read-only, execute memory permission 840 2) All read-only data will have read-only permission, and execution 841 disabled if the hardware supports it. 842 3) All other RAM addresses will have read-write permission, and 843 execution disabled if the hardware supports it. 844 845 Options such as USERSPACE or HW_STACK_PROTECTION may additionally 846 impose additional policies on the memory map, which may be global 847 or local to the current running thread. 848 849 This option may consume additional memory to satisfy memory protection 850 hardware alignment constraints. 851 852 If this option is disabled, the entire kernel will have default memory 853 access permissions set, typically read/write/execute. It may be desirable 854 to turn this off on MMU systems which are using the MMU for demand 855 paging, do not need memory protection, and would rather not use up 856 RAM for the alignment between regions. 857 858config CODE_DATA_RELOCATION 859 bool "Support code/data section relocation" 860 depends on ARCH_HAS_CODE_DATA_RELOCATION 861 help 862 Enable support for relocating .text, data and .bss sections from specified 863 files and placing them in a chosen memory region. Files to relocate and 864 the target regions should be specified in CMakeLists.txt using 865 zephyr_code_relocate(). 866 867menu "DSP Options" 868 869config DSP_SHARING 870 bool "DSP register sharing" 871 depends on CPU_HAS_DSP 872 help 873 This option enables preservation of the hardware DSP registers 874 across context switches to allow multiple threads to perform concurrent 875 DSP operations. 876endmenu 877 878menu "Floating Point Options" 879 880config FPU 881 bool "Floating point unit (FPU)" 882 depends on CPU_HAS_FPU 883 help 884 This option enables the hardware Floating Point Unit (FPU), in order to 885 support using the floating point registers and instructions. 886 887 When this option is enabled, by default, threads may use the floating 888 point registers only in an exclusive manner, and this usually means that 889 only one thread may perform floating point operations. 890 891 If it is necessary for multiple threads to perform concurrent floating 892 point operations, the "FPU register sharing" option must be enabled to 893 preserve the floating point registers across context switches. 894 895 Note that this option cannot be selected for the platforms that do not 896 include a hardware floating point unit; the floating point support for 897 those platforms is dependent on the availability of the toolchain- 898 provided software floating point library. 899 900config FPU_SHARING 901 bool "FPU register sharing" 902 depends on FPU && MULTITHREADING 903 help 904 This option enables preservation of the hardware floating point registers 905 across context switches to allow multiple threads to perform concurrent 906 floating point operations. 907 908 Note that some compiler configurations may activate a floating point 909 context by generating FP instructions for any thread, and that 910 context must be preserved when switching such threads in and out. 911 The developers can still disable the FP sharing mode in their 912 application projects, and switch to Unshared FP registers mode, 913 if it is guaranteed that the image code does not generate FP 914 instructions outside the single thread context that is allowed 915 to do so. 916 917endmenu 918 919menu "Cache Options" 920 921config DCACHE 922 bool "Data cache (d-cache) support" 923 depends on CPU_HAS_DCACHE 924 default y 925 help 926 This option enables the support for the data cache (d-cache). 927 928config ICACHE 929 bool "Instruction cache (i-cache) support" 930 depends on CPU_HAS_ICACHE 931 default y 932 help 933 This option enables the support for the instruction cache (i-cache). 934 935config CACHE_DOUBLEMAP 936 bool "Cache double-mapping support" 937 depends on CPU_CACHE_INCOHERENT 938 default y 939 help 940 Double-mapping behavior where a pointer can be cheaply converted to 941 point to the same cached/uncached memory at different locations. 942 943 This applies to intra-CPU multiprocessing incoherence and makes only 944 sense when MP_NUM_CPUS > 1. 945 946config CACHE_MANAGEMENT 947 bool "Cache management features" 948 depends on DCACHE || ICACHE 949 help 950 This option enables the cache management functions backed by arch or 951 driver code. 952 953config DCACHE_LINE_SIZE_DETECT 954 bool "Detect d-cache line size at runtime" 955 depends on CACHE_MANAGEMENT && DCACHE 956 help 957 This option enables querying some architecture-specific hardware for 958 finding the d-cache line size at the expense of taking more memory and 959 code and a slightly increased boot time. 960 961 If the CPU's d-cache line size is known in advance, disable this option and 962 manually enter the value for DCACHE_LINE_SIZE or set it in the DT 963 using the 'd-cache-line-size' property. 964 965config DCACHE_LINE_SIZE 966 int "d-cache line size" 967 depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT 968 default 0 969 help 970 Size in bytes of a CPU d-cache line. If this is set to 0 the value is 971 obtained from the 'd-cache-line-size' DT property instead if present. 972 973 974 Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. 975 976config ICACHE_LINE_SIZE_DETECT 977 bool "Detect i-cache line size at runtime" 978 depends on CACHE_MANAGEMENT && ICACHE 979 help 980 This option enables querying some architecture-specific hardware for 981 finding the i-cache line size at the expense of taking more memory and 982 code and a slightly increased boot time. 983 984 If the CPU's i-cache line size is known in advance, disable this option and 985 manually enter the value for ICACHE_LINE_SIZE or set it in the DT 986 using the 'i-cache-line-size' property. 987 988config ICACHE_LINE_SIZE 989 int "i-cache line size" 990 depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT 991 default 0 992 help 993 Size in bytes of a CPU i-cache line. If this is set to 0 the value is 994 obtained from the 'i-cache-line-size' DT property instead if present. 995 996 Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. 997 998choice CACHE_TYPE 999 prompt "Cache type" 1000 depends on CACHE_MANAGEMENT 1001 default ARCH_CACHE 1002 1003config ARCH_CACHE 1004 bool "Integrated cache controller" 1005 help 1006 Integrated on-core cache controller 1007 1008config EXTERNAL_CACHE 1009 bool "External cache controller" 1010 help 1011 External cache controller 1012 1013endchoice 1014 1015endmenu 1016 1017config ARCH 1018 string 1019 help 1020 System architecture string. 1021 1022config SOC 1023 string 1024 help 1025 SoC name which can be found under soc/<arch>/<soc name>. 1026 This option holds the directory name used by the build system to locate 1027 the correct linker and header files for the SoC. 1028 1029config SOC_SERIES 1030 string 1031 help 1032 SoC series name which can be found under soc/<arch>/<family>/<series>. 1033 This option holds the directory name used by the build system to locate 1034 the correct linker and header files. 1035 1036config SOC_FAMILY 1037 string 1038 help 1039 SoC family name which can be found under soc/<arch>/<family>. 1040 This option holds the directory name used by the build system to locate 1041 the correct linker and header files. 1042 1043config TOOLCHAIN_HAS_BUILTIN_FFS 1044 bool 1045 default y if !(64BIT && RISCV) 1046 help 1047 Hidden option to signal that toolchain has __builtin_ffs*(). 1048 1049config ARCH_CPU_IDLE_CUSTOM 1050 bool "Custom arch_cpu_idle implementation" 1051 default n 1052 help 1053 This options allows applications to override the default arch idle implementation with 1054 a custom one. 1055
