1menu "Driver configurations" 2 3 menu "ADC configuration" 4 5 config ADC_FORCE_XPD_FSM 6 bool "Use the FSM to control ADC power" 7 default n 8 help 9 ADC power can be controlled by the FSM instead of software. This allows the ADC to 10 be shut off when it is not working leading to lower power consumption. However 11 using the FSM control ADC power will increase the noise of ADC. 12 13 config ADC_DISABLE_DAC 14 bool "Disable DAC when ADC2 is used on GPIO 25 and 26" 15 default y 16 help 17 If this is set, the ADC2 driver will disable the output of the DAC corresponding to the specified 18 channel. This is the default value. 19 20 For testing, disable this option so that we can measure the output of DAC by internal ADC. 21 22 endmenu # ADC Configuration 23 24 menu "MCPWM configuration" 25 26 config MCPWM_ISR_IN_IRAM 27 bool "Place MCPWM ISR function into IRAM" 28 default n 29 help 30 If this option is not selected, the MCPWM interrupt will be deferred when the Cache 31 is in a disabled state (e.g. Flash write/erase operation). 32 33 Note that if this option is selected, all user registered ISR callbacks should never 34 try to use cache as well. (with IRAM_ATTR) 35 36 endmenu # MCPWM Configuration 37 38 menu "SPI configuration" 39 40 config SPI_MASTER_IN_IRAM 41 bool "Place transmitting functions of SPI master into IRAM" 42 default n 43 select SPI_MASTER_ISR_IN_IRAM 44 help 45 Normally only the ISR of SPI master is placed in the IRAM, so that it 46 can work without the flash when interrupt is triggered. 47 For other functions, there's some possibility that the flash cache 48 miss when running inside and out of SPI functions, which may increase 49 the interval of SPI transactions. 50 Enable this to put ``queue_trans``, ``get_trans_result`` and 51 ``transmit`` functions into the IRAM to avoid possible cache miss. 52 53 During unit test, this is enabled to measure the ideal case of api. 54 55 config SPI_MASTER_ISR_IN_IRAM 56 bool "Place SPI master ISR function into IRAM" 57 default y 58 help 59 Place the SPI master ISR in to IRAM to avoid possible cache miss. 60 61 Also you can forbid the ISR being disabled during flash writing 62 access, by add ESP_INTR_FLAG_IRAM when initializing the driver. 63 64 config SPI_SLAVE_IN_IRAM 65 bool "Place transmitting functions of SPI slave into IRAM" 66 default n 67 select SPI_SLAVE_ISR_IN_IRAM 68 help 69 Normally only the ISR of SPI slave is placed in the IRAM, so that it 70 can work without the flash when interrupt is triggered. 71 For other functions, there's some possibility that the flash cache 72 miss when running inside and out of SPI functions, which may increase 73 the interval of SPI transactions. 74 Enable this to put ``queue_trans``, ``get_trans_result`` and 75 ``transmit`` functions into the IRAM to avoid possible cache miss. 76 77 config SPI_SLAVE_ISR_IN_IRAM 78 bool "Place SPI slave ISR function into IRAM" 79 default y 80 help 81 Place the SPI slave ISR in to IRAM to avoid possible cache miss. 82 83 Also you can forbid the ISR being disabled during flash writing 84 access, by add ESP_INTR_FLAG_IRAM when initializing the driver. 85 86 endmenu # SPI Configuration 87 88 menu "TWAI configuration" 89 90 config TWAI_ISR_IN_IRAM 91 bool "Place TWAI ISR function into IRAM" 92 default n 93 help 94 Place the TWAI ISR in to IRAM. This will allow the ISR to avoid 95 cache misses, and also be able to run whilst the cache is disabled 96 (such as when writing to SPI Flash). 97 Note that if this option is enabled: 98 - Users should also set the ESP_INTR_FLAG_IRAM in the driver 99 configuration structure when installing the driver (see docs for 100 specifics). 101 - Alert logging (i.e., setting of the TWAI_ALERT_AND_LOG flag) 102 will have no effect. 103 104 config TWAI_ERRATA_FIX_BUS_OFF_REC 105 bool "Add SW workaround for REC change during bus-off" 106 depends on IDF_TARGET_ESP32 107 default n 108 help 109 When the bus-off condition is reached, the REC should be reset to 0 and frozen (via LOM) by the 110 driver's ISR. However on the ESP32, there is an edge case where the REC will increase before the 111 driver's ISR can respond in time (e.g., due to the rapid occurrence of bus errors), thus causing the 112 REC to be non-zero after bus-off. A non-zero REC can prevent bus-off recovery as the bus-off recovery 113 condition is that both TEC and REC become 0. Enabling this option will add a workaround in the driver 114 to forcibly reset REC to zero on reaching bus-off. 115 116 config TWAI_ERRATA_FIX_TX_INTR_LOST 117 bool "Add SW workaround for TX interrupt lost errata" 118 depends on IDF_TARGET_ESP32 119 default n 120 help 121 On the ESP32, when a transmit interrupt occurs, and interrupt register is read on the same APB clock 122 cycle, the transmit interrupt could be lost. Enabling this option will add a workaround that checks the 123 transmit buffer status bit to recover any lost transmit interrupt. 124 125 config TWAI_ERRATA_FIX_RX_FRAME_INVALID 126 bool "Add SW workaround for invalid RX frame errata" 127 depends on IDF_TARGET_ESP32 128 default n 129 help 130 On the ESP32, when receiving a data or remote frame, if a bus error occurs in the data or CRC field, 131 the data of the next received frame could be invalid. Enabling this option will add a workaround that 132 will reset the peripheral on detection of this errata condition. Note that if a frame is transmitted on 133 the bus whilst the reset is ongoing, the message will not be receive by the peripheral sent on the bus 134 during the reset, the message will be lost. 135 136 config TWAI_ERRATA_FIX_RX_FIFO_CORRUPT 137 bool "Add SW workaround for RX FIFO corruption errata" 138 depends on IDF_TARGET_ESP32 139 default n 140 help 141 On the ESP32, when the RX FIFO overruns and the RX message counter maxes out at 64 messages, the entire 142 RX FIFO is no longer recoverable. Enabling this option will add a workaround that resets the peripheral 143 on detection of this errata condition. Note that if a frame is being sent on the bus during the reset 144 bus during the reset, the message will be lost. 145 146 endmenu # TWAI Configuration 147 148 menu "UART configuration" 149 150 config UART_ISR_IN_IRAM 151 bool "Place UART ISR function into IRAM" 152 default n 153 help 154 If this option is not selected, UART interrupt will be disabled for a long time and 155 may cause data lost when doing spi flash operation. 156 157 endmenu # UART Configuration 158 159 menu "RTCIO configuration" 160 visible if IDF_TARGET_ESP32 161 162 config RTCIO_SUPPORT_RTC_GPIO_DESC 163 bool "Support array `rtc_gpio_desc` for ESP32" 164 depends on IDF_TARGET_ESP32 165 default n 166 help 167 The the array `rtc_gpio_desc` will don't compile by default. 168 If this option is selected, the array `rtc_gpio_desc` can be compile. 169 If user use this array, please enable this configuration. 170 171 endmenu # RTCIO Configuration 172 173 menu "GPIO Configuration" 174 visible if IDF_TARGET_ESP32 175 176 config GPIO_ESP32_SUPPORT_SWITCH_SLP_PULL 177 bool "Support light sleep GPIO pullup/pulldown configuration for ESP32" 178 depends on IDF_TARGET_ESP32 179 help 180 This option is intended to fix the bug that ESP32 is not able to switch to configured 181 pullup/pulldown mode in sleep. 182 If this option is selected, chip will automatically emulate the behaviour of switching, 183 and about 450B of source codes would be placed into IRAM. 184 185 endmenu # GPIO Configuration 186 187 menu "GDMA Configuration" 188 config GDMA_CTRL_FUNC_IN_IRAM 189 bool "Place GDMA control functions into IRAM" 190 default n 191 help 192 Place GDMA control functions (like start/stop/append/reset) into IRAM, 193 so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. 194 Enabling this option can improve driver performance as well. 195 196 config GDMA_ISR_IRAM_SAFE 197 bool "GDMA ISR IRAM-Safe" 198 default n 199 help 200 This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash 201 cache misses, and also be able to run whilst the cache is disabled. 202 (e.g. SPI Flash write). 203 endmenu # GDMA Configuration 204 205endmenu # Driver configurations 206
