1# Nuvoton Cortex-M4 Embedded Controller
2
3# Copyright (c) 2020 Nuvoton Technology Corporation.
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_FAMILY_NPCX
7	bool
8
9if SOC_FAMILY_NPCX
10config SOC_FAMILY
11	string
12	default "nuvoton_npcx"
13
14menuconfig NPCX_HEADER
15	bool "Enable the output binary with NPCX binary header"
16	help
17	  On NPCX series chip, the NPCX ROM code loads firmware image from flash
18	  to RAM by the firmware binary header setting. Enable this to invoke
19	  the 'ecst' which generates the NPCX firmware header.
20
21if NPCX_HEADER
22
23config NPCX_IMAGE_OUTPUT_BIN
24	bool "Build npcx binary in BIN format"
25	default y
26	help
27	  Build a "raw" binary zephyr/zephyr.npcx.bin in the build directory.
28	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
29
30config NPCX_IMAGE_OUTPUT_HEX
31	bool "Build npcx binary in HEX format"
32	depends on NPCX_IMAGE_OUTPUT_BIN
33	help
34	  Build an HEX binary zephyr/zephyr.npcx.hex in the build directory.
35	  This is generated from the npcx BIN image.
36	  The name of this file can be customized with CONFIG_KERNEL_BIN_NAME.
37
38config NPCX_HEADER_CHIP
39	string
40	default "npcx7m6" if SOC_NPCX7M6FB || SOC_NPCX7M6FC
41	default "npcx7m7" if SOC_NPCX7M7FC
42	default "npcx9m3" if SOC_NPCX9M3F
43	default "npcx9m6" if SOC_NPCX9M6F
44
45choice NPCX_HEADER_SPI_MAX_CLOCK_CHOICE
46	prompt "Clock rate to use for SPI flash"
47	default NPCX_HEADER_SPI_MAX_CLOCK_20
48	help
49	  This selects the max clock rate that will be used for loading firmware
50	  binary from flash to RAM.
51
52config NPCX_HEADER_SPI_MAX_CLOCK_20
53	bool "SPI flash max clock rate of 20 MHz"
54
55config NPCX_HEADER_SPI_MAX_CLOCK_25
56	bool "SPI flash max clock rate of 25 MHz"
57
58config NPCX_HEADER_SPI_MAX_CLOCK_33
59	bool "SPI flash max clock rate of 33 MHz"
60	depends on !SOC_SERIES_NPCX9
61
62config NPCX_HEADER_SPI_MAX_CLOCK_40
63	bool "SPI flash max clock rate of 40 MHz"
64
65config NPCX_HEADER_SPI_MAX_CLOCK_50
66	bool "SPI flash max clock rate of 50 MHz"
67endchoice
68
69config NPCX_HEADER_SPI_MAX_CLOCK
70	int
71	default 20 if NPCX_HEADER_SPI_MAX_CLOCK_20
72	default 25 if NPCX_HEADER_SPI_MAX_CLOCK_25
73	default 33 if NPCX_HEADER_SPI_MAX_CLOCK_33
74	default 40 if NPCX_HEADER_SPI_MAX_CLOCK_40
75	default 50 if NPCX_HEADER_SPI_MAX_CLOCK_50
76
77choice NPCX_HEADER_SPI_READ_MODE_CHOICE
78	prompt "Reading mode used by the SPI flash"
79	default NPCX_HEADER_SPI_READ_MODE_NORMAL
80	help
81	  This sets the reading mode that can be used by the SPI flash.
82	  Reading modes supported are normal, fast, dual, and quad.
83
84config NPCX_HEADER_SPI_READ_MODE_NORMAL
85	bool "SPI flash operates with normal reading mode"
86
87config NPCX_HEADER_SPI_READ_MODE_FAST
88	bool "SPI flash operates with fast reading mode"
89
90config NPCX_HEADER_SPI_READ_MODE_DUAL
91	bool "SPI flash operates with dual reading mode"
92
93config NPCX_HEADER_SPI_READ_MODE_QUAD
94	bool "SPI flash operates with quad reading mode"
95endchoice
96
97config NPCX_HEADER_SPI_READ_MODE
98	string
99	default "normal" if NPCX_HEADER_SPI_READ_MODE_NORMAL
100	default "fast" if NPCX_HEADER_SPI_READ_MODE_FAST
101	default "dual" if NPCX_HEADER_SPI_READ_MODE_DUAL
102	default "quad" if NPCX_HEADER_SPI_READ_MODE_QUAD
103
104choice NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_CHOICE
105	prompt "Core clock to SPI flash clock ratio"
106	default NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
107	help
108	  This sets the clock ratio (core clock / SPI clock)
109
110config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
111	bool "NPCX SPI clock ratio 1"
112	help
113	  The SPI flash clock has the same frequency as the core clock.
114
115config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
116	bool "NPCX SPI clock ratio 2"
117	help
118	  The core clock frequency is twice the flash clock frequency.
119endchoice
120
121config NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO
122	int
123	default 1 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_1
124	default 2 if NPCX_HEADER_CORE_CLOCK_SPI_CLOCK_RATIO_2
125
126config NPCX_HEADER_ENABLE_HEADER_CRC
127	bool "Enable header crc check"
128	help
129	  When enabled, the header will be verified at boot using a crc
130	  checksum.
131
132config NPCX_HEADER_ENABLE_FIRMWARE_CRC
133	bool "Enable firmware image crc check"
134	help
135	  When enabled, the firmware image will be verified at boot using a
136	  crc checksum.
137
138choice NPCX_HEADER_FLASH_SIZE_CHOICE
139	prompt "Flash size"
140	default NPCX_HEADER_FLASH_SIZE_0P5M_1M if SOC_SERIES_NPCX7 || \
141						  SOC_SERIES_NPCX9
142	default NPCX_HEADER_FLASH_SIZE_16M
143	help
144	  This sets the SPI flash size.
145
146config NPCX_HEADER_FLASH_SIZE_0P5M_1M
147	bool "SPI flash size 0.5M or 1M Bytes"
148	help
149	  The SPI flash size is 0.5M or 1M Bytes.
150
151config NPCX_HEADER_FLASH_SIZE_2M
152	bool "SPI flash size 2M Bytes"
153	help
154	  The SPI flash size is 2M Bytes.
155
156config NPCX_HEADER_FLASH_SIZE_4M
157	bool "SPI flash size 4M Bytes"
158	help
159	  The SPI flash size is 4M Bytes.
160
161config NPCX_HEADER_FLASH_SIZE_8M
162	bool "SPI flash size 8M Bytes"
163	help
164	  The SPI flash size is 8M Bytes.
165
166config NPCX_HEADER_FLASH_SIZE_16M
167	bool "SPI flash size 16M Bytes"
168	help
169	  The SPI flash size is 16M Bytes.
170endchoice
171
172config NPCX_HEADER_FLASH_SIZE
173	int
174	default 1 if NPCX_HEADER_FLASH_SIZE_0P5M_1M
175	default 2 if NPCX_HEADER_FLASH_SIZE_2M
176	default 4 if NPCX_HEADER_FLASH_SIZE_4M
177	default 8 if NPCX_HEADER_FLASH_SIZE_8M
178	default 16 if NPCX_HEADER_FLASH_SIZE_16M
179
180endif # NPCX_HEADER
181
182# Select SoC Part No. and configuration options
183source "soc/arm/nuvoton_npcx/*/Kconfig.soc"
184
185config SOC_POWER_MANAGEMENT
186	bool "System Power Management in NPCX family"
187	depends on SOC_FAMILY_NPCX
188	help
189	  This option enables the board to implement SoC-specific power
190	  management policies whenever the kernel becomes idle. The power
191	  management subsystem will restore to the active state until an
192	  wake-up event is received no matter the system timer is expired or
193	  the other signals occurred such as GPIO, host access, and so on.
194
195config SOC_POWER_MANAGEMENT_TRACE
196	bool "Trace System Power Management in NPCX family"
197	depends on SOC_POWER_MANAGEMENT
198	help
199	  Internal config to enable runtime power management traces.
200
201endif # SOC_FAMILY_NPCX
202