1# Atmel SAM V71 MCU series
2
3# Copyright (c) 2019 Gerson Fernando Budke
4# Copyright (c) 2016 Piotr Mienkowski
5# SPDX-License-Identifier: Apache-2.0
6
7choice
8	prompt "Atmel SAMV71 MCU Selection"
9	depends on SOC_SERIES_SAMV71
10
11	config SOC_PART_NUMBER_SAMV71Q21
12		bool "SAMV71Q21"
13
14	config SOC_PART_NUMBER_SAMV71Q20
15		bool "SAMV71Q20"
16
17	config SOC_PART_NUMBER_SAMV71Q19
18		bool "SAMV71Q19"
19
20	config SOC_PART_NUMBER_SAMV71N21
21		bool "SAMV71N21"
22
23	config SOC_PART_NUMBER_SAMV71N20
24		bool "SAMV71N20"
25
26	config SOC_PART_NUMBER_SAMV71N19
27		bool "SAMV71N19"
28
29	config SOC_PART_NUMBER_SAMV71J21
30		bool "SAMV71J21"
31
32	config SOC_PART_NUMBER_SAMV71J20
33		bool "SAMV71J20"
34
35	config SOC_PART_NUMBER_SAMV71J19
36		bool "SAMV71J19"
37
38	config SOC_PART_NUMBER_SAMV71Q21B
39		bool "SAMV71Q21B"
40		select SOC_ATMEL_SAMV71_REVB
41
42	config SOC_PART_NUMBER_SAMV71Q20B
43		bool "SAMV71Q20B"
44		select SOC_ATMEL_SAMV71_REVB
45
46	config SOC_PART_NUMBER_SAMV71Q19B
47		bool "SAMV71Q19B"
48		select SOC_ATMEL_SAMV71_REVB
49
50	config SOC_PART_NUMBER_SAMV71N21B
51		bool "SAMV71N21B"
52		select SOC_ATMEL_SAMV71_REVB
53
54	config SOC_PART_NUMBER_SAMV71N20B
55		bool "SAMV71N20B"
56		select SOC_ATMEL_SAMV71_REVB
57
58	config SOC_PART_NUMBER_SAMV71N19B
59		bool "SAMV71N19B"
60		select SOC_ATMEL_SAMV71_REVB
61
62	config SOC_PART_NUMBER_SAMV71J21B
63		bool "SAMV71J21B"
64		select SOC_ATMEL_SAMV71_REVB
65
66	config SOC_PART_NUMBER_SAMV71J20B
67		bool "SAMV71J20B"
68		select SOC_ATMEL_SAMV71_REVB
69
70	config SOC_PART_NUMBER_SAMV71J19B
71		bool "SAMV71J19B"
72		select SOC_ATMEL_SAMV71_REVB
73endchoice
74
75if SOC_SERIES_SAMV71
76
77config SOC_ATMEL_SAMV71_REVB
78	bool
79
80config SOC_ATMEL_SAMV71_EXT_SLCK
81	bool "Use external crystal oscillator for slow clock"
82	help
83	  Say y if you want to use external 32 kHz crystal
84	  oscillator to drive the slow clock. Note that this
85	  adds a few seconds to boot time, as the crystal
86	  needs to stabilize after power-up.
87
88	  Says n if you do not need accurate and precise timers.
89	  The slow clock will be driven by the internal fast
90	  RC oscillator running at 32 kHz.
91
92config SOC_ATMEL_SAMV71_EXT_MAINCK
93	bool "Use external crystal oscillator for main clock"
94	help
95	  The main clock is being used to drive the PLL, and
96	  thus driving the processor clock.
97
98	  Say y if you want to use external crystal oscillator
99	  to drive the main clock. Note that this adds about
100	  a second to boot time, as the crystal needs to
101	  stabilize after power-up.
102
103	  The crystal used here can be from 3 to 20 MHz.
104
105	  Says n here will use the internal fast RC oscillator
106	  running at 12 MHz.
107
108config SOC_ATMEL_SAMV71_MDIV
109	int "MDIV"
110	default 2
111	range 1 4
112	help
113	  This divisor defines a ratio between processor clock (HCLK)
114	  and master clock (MCK):
115	  MCK = HCLK / MDIV
116
117config SOC_ATMEL_SAMV71_PLLA_MULA
118	int "PLL MULA"
119	default 24
120	range 1 62
121	help
122	  This is the multiplier MULA used by the PLL.
123	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
124
125	  Board config file can override this settings
126	  for a particular board.
127
128	  Setting MULA=0 would disable PLL at boot, this is currently
129	  not supported.
130
131	  With default of MULA == 24, and DIVA == 1,
132	  PLL is running at 25 times the main clock frequency.
133
134config SOC_ATMEL_SAMV71_PLLA_DIVA
135	int "PLL DIVA"
136	default 1
137	range 1 255
138	help
139	  This is the divider DIVA used by the PLL.
140	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
141
142	  Board config file can override this settings
143	  for a particular board.
144
145	  Setting DIVA=0 would disable PLL at boot, this is currently
146	  not supported.
147
148	  With default of MULA == 24, and DIVA == 1,
149	  PLL is running at 25 times the main clock frequency.
150
151config SOC_ATMEL_SAMV71_WAIT_MODE
152	bool "Go to Wait mode instead of Sleep mode"
153	depends on SOC_ATMEL_SAMV71_EXT_MAINCK
154	default y if DEBUG
155	help
156	  For JTAG debugging CPU clock (HCLK) should not stop. In order
157	  to achieve this, make CPU go to Wait mode instead of Sleep
158	  mode while using external crystal oscillator for main clock.
159
160config SOC_ATMEL_SAMV71_DISABLE_ERASE_PIN
161	bool "Disable ERASE pin"
162	help
163	  At reset ERASE pin is configured in System IO mode. Asserting the ERASE
164	  pin at '1' will completely erase Flash memory. Setting this option will
165	  switch the pin to general IO mode giving control of the pin to the GPIO
166	  module.
167
168endif # SOC_SERIES_SAMV71
169