1# Atmel SAM3X MCU series
2
3# Copyright (c) 2017 Justin Watson
4# Copyright (c) 2016 Intel Corporation.
5# Copyright (c) 2014-2015 Wind River Systems, Inc.
6# SPDX-License-Identifier: Apache-2.0
7
8choice
9	prompt "Atmel SAM3X MCU Selection"
10	depends on SOC_SERIES_SAM3X
11
12	config SOC_PART_NUMBER_SAM3X4C
13		bool "SAM3X4C"
14	config SOC_PART_NUMBER_SAM3X4E
15		bool "SAM3X4E"
16	config SOC_PART_NUMBER_SAM3X8C
17		bool "SAM3X8C"
18	config SOC_PART_NUMBER_SAM3X8E
19		bool "SAM3X8E"
20	config SOC_PART_NUMBER_SAM3X8H
21		bool "SAM3X8H"
22endchoice
23
24if SOC_SERIES_SAM3X
25
26config SOC_ATMEL_SAM3X_EXT_SLCK
27	bool "Atmel SAM3 to use external crystal oscillator for slow clock"
28	help
29	  Says y if you want to use external 32 kHz crystal
30	  oscillator to drive the slow clock. Note that this
31	  adds a few seconds to boot time, as the crystal
32	  needs to stabilize after power-up.
33
34	  Says n if you do not need accurate and precise timers.
35	  The slow clock will be driven by the internal fast
36	  RC oscillator running at 32 kHz.
37
38config SOC_ATMEL_SAM3X_EXT_MAINCK
39	bool "Atmel SAM3 to use external crystal oscillator for main clock"
40	help
41	  The main clock is being used to drive the PLL, and
42	  thus driving the processor clock.
43
44	  Says y if you want to use external crystal oscillator
45	  to drive the main clock. Note that this adds about
46	  a second to boot time, as the crystal needs to
47	  stabilize after power-up.
48
49	  The crystal used here can be from 3 to 20 MHz.
50
51	  Says n here will use the internal fast RC oscillator
52	  running at 12 MHz.
53
54config SOC_ATMEL_SAM3X_PLLA_MULA
55	hex
56	default 0x06
57	help
58	  This is the multiplier (MULA) used by the PLL.
59	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
60
61	  Board config file can override this settings
62	  for a particular board.
63
64	  With default of MULA == 6, and DIVA == 1,
65	  PLL is running at 7 times of main clock.
66
67config SOC_ATMEL_SAM3X_PLLA_DIVA
68	hex
69	default 0x01
70	help
71	  This is the divider (DIVA) used by the PLL.
72	  The processor clock is (MAINCK * (MULA + 1) / DIVA).
73
74	  Board config file can override this settings
75	  for a particular board.
76
77	  With default of MULA == 6, and DIVA == 1,
78	  PLL is running at 7 times of main clock.
79
80config SOC_ATMEL_SAM3X_WAIT_MODE
81	bool "Atmel SAM3 goes to Wait mode instead of Sleep mode"
82	depends on SOC_ATMEL_SAM3X_EXT_MAINCK
83	default y if DEBUG
84	help
85	  For JTAG debugging CPU clock (HCLK) should not stop. In order
86	  to achieve this, make CPU go to Wait mode instead of Sleep
87	  mode while using external crystal oscillator for main clock.
88
89endif # SOC_SERIES_SAM3X
90