1# Nordic Semiconductor nRF53 MCU line 2 3# Copyright (c) 2019 Nordic Semiconductor ASA 4# SPDX-License-Identifier: Apache-2.0 5 6config SOC_NRF5340_CPUAPP 7 depends on SOC_SERIES_NRF53X 8 bool 9 select CPU_HAS_NRF_IDAU 10 select CPU_HAS_FPU 11 select ARMV8_M_DSP 12 select HAS_HW_NRF_CC312 13 select HAS_HW_NRF_COMP 14 select HAS_HW_NRF_CLOCK 15 select HAS_HW_NRF_DPPIC 16 select HAS_HW_NRF_EGU0 17 select HAS_HW_NRF_EGU1 18 select HAS_HW_NRF_EGU2 19 select HAS_HW_NRF_EGU3 20 select HAS_HW_NRF_EGU4 21 select HAS_HW_NRF_EGU5 22 select HAS_HW_NRF_GPIO0 23 select HAS_HW_NRF_GPIO1 24 select HAS_HW_NRF_GPIOTE 25 select HAS_HW_NRF_I2S 26 select HAS_HW_NRF_IPC 27 select HAS_HW_NRF_KMU 28 select HAS_HW_NRF_LPCOMP 29 select HAS_HW_NRF_NFCT 30 select HAS_HW_NRF_NVMC_PE 31 select HAS_HW_NRF_PDM 32 select HAS_HW_NRF_POWER 33 select HAS_HW_NRF_PWM0 34 select HAS_HW_NRF_PWM1 35 select HAS_HW_NRF_PWM2 36 select HAS_HW_NRF_PWM3 37 select HAS_HW_NRF_QDEC0 38 select HAS_HW_NRF_QDEC1 39 select HAS_HW_NRF_QSPI 40 select HAS_HW_NRF_RTC0 41 select HAS_HW_NRF_RTC1 42 select HAS_HW_NRF_SAADC 43 select HAS_HW_NRF_SPIM0 44 select HAS_HW_NRF_SPIM1 45 select HAS_HW_NRF_SPIM2 46 select HAS_HW_NRF_SPIM3 47 select HAS_HW_NRF_SPIM4 48 select HAS_HW_NRF_SPIS0 49 select HAS_HW_NRF_SPIS1 50 select HAS_HW_NRF_SPIS2 51 select HAS_HW_NRF_SPIS3 52 select HAS_HW_NRF_SPU 53 select HAS_HW_NRF_TIMER0 54 select HAS_HW_NRF_TIMER1 55 select HAS_HW_NRF_TIMER2 56 select HAS_HW_NRF_TWIM0 57 select HAS_HW_NRF_TWIM1 58 select HAS_HW_NRF_TWIM2 59 select HAS_HW_NRF_TWIM3 60 select HAS_HW_NRF_TWIS0 61 select HAS_HW_NRF_TWIS1 62 select HAS_HW_NRF_TWIS2 63 select HAS_HW_NRF_TWIS3 64 select HAS_HW_NRF_UARTE0 65 select HAS_HW_NRF_UARTE1 66 select HAS_HW_NRF_UARTE2 67 select HAS_HW_NRF_UARTE3 68 select HAS_HW_NRF_USBD 69 select HAS_HW_NRF_USBREG 70 select HAS_HW_NRF_WDT0 71 select HAS_HW_NRF_WDT1 72 73config SOC_NRF5340_CPUNET 74 depends on SOC_SERIES_NRF53X 75 bool 76 select HAS_HW_NRF_ACL 77 select HAS_HW_NRF_CLOCK 78 select HAS_HW_NRF_CCM 79 select HAS_HW_NRF_CCM_LFLEN_8BIT 80 select HAS_HW_NRF_DPPIC 81 select HAS_HW_NRF_ECB 82 select HAS_HW_NRF_EGU0 83 select HAS_HW_NRF_GPIO0 84 select HAS_HW_NRF_GPIO1 85 select HAS_HW_NRF_GPIOTE 86 select HAS_HW_NRF_IPC 87 select HAS_HW_NRF_NVMC_PE 88 select HAS_HW_NRF_POWER 89 select HAS_HW_NRF_RADIO_BLE_2M 90 select HAS_HW_NRF_RADIO_BLE_CODED 91 select HAS_HW_NRF_RADIO_IEEE802154 92 select HAS_HW_NRF_RNG 93 select HAS_HW_NRF_RTC0 94 select HAS_HW_NRF_RTC1 95 select HAS_HW_NRF_SPIM0 96 select HAS_HW_NRF_SPIS0 97 select HAS_HW_NRF_SWI0 98 select HAS_HW_NRF_SWI1 99 select HAS_HW_NRF_SWI2 100 select HAS_HW_NRF_SWI3 101 select HAS_HW_NRF_TEMP 102 select HAS_HW_NRF_TIMER0 103 select HAS_HW_NRF_TIMER1 104 select HAS_HW_NRF_TIMER2 105 select HAS_HW_NRF_TWIM0 106 select HAS_HW_NRF_TWIS0 107 select HAS_HW_NRF_UARTE0 108 select HAS_HW_NRF_WDT 109 select HAS_NO_SYS_PM 110 111choice 112 prompt "nRF53x MCU Selection" 113 depends on SOC_SERIES_NRF53X 114 115config SOC_NRF5340_CPUAPP_QKAA 116 bool "NRF5340_CPUAPP_QKAA" 117 select SOC_NRF5340_CPUAPP 118 119config SOC_NRF5340_CPUNET_QKAA 120 bool "NRF5340_CPUNET_QKAA" 121 select SOC_NRF5340_CPUNET 122 123endchoice 124 125 126if SOC_NRF5340_CPUAPP 127 128config SOC_DCDC_NRF53X_APP 129 bool 130 help 131 Enable nRF53 series System on Chip Application MCU DC/DC converter. 132 133config SOC_DCDC_NRF53X_NET 134 bool 135 help 136 Enable nRF53 series System on Chip Network MCU DC/DC converter. 137 138config SOC_DCDC_NRF53X_HV 139 bool 140 help 141 Enable nRF53 series System on Chip High Voltage DC/DC converter. 142 143if !TRUSTED_EXECUTION_NONSECURE 144 145config SOC_ENABLE_LFXO 146 bool "Enable LFXO" 147 default y 148 help 149 Enable the low-frequency oscillator (LFXO) functionality on XL1 and 150 XL2 pins. 151 This option must be enabled if either application or network core is 152 to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular 153 GPIOs. 154 155choice SOC_LFXO_LOAD_CAPACITANCE 156 prompt "LFXO load capacitance" 157 depends on SOC_ENABLE_LFXO 158 default SOC_LFXO_CAP_INT_7PF 159 160config SOC_LFXO_CAP_EXTERNAL 161 bool "Use external load capacitors" 162 163config SOC_LFXO_CAP_INT_6PF 164 bool "6 pF internal load capacitance" 165 166config SOC_LFXO_CAP_INT_7PF 167 bool "7 pF internal load capacitance" 168 169config SOC_LFXO_CAP_INT_9PF 170 bool "9 pF internal load capacitance" 171 172endchoice 173 174choice SOC_HFXO_LOAD_CAPACITANCE 175 prompt "HFXO load capacitance" 176 default SOC_HFXO_CAP_DEFAULT 177 178config SOC_HFXO_CAP_DEFAULT 179 bool "SoC default" 180 help 181 When this option is used, the SoC initialization routine does not 182 touch the XOSC32MCAPS register value, so the default setting for 183 the SoC is in effect. Please note that this may not necessarily be 184 the reset value (0) for the register, as the register can be set 185 during the device trimming in the SystemInit() function. 186 187config SOC_HFXO_CAP_EXTERNAL 188 bool "Use external load capacitors" 189 190config SOC_HFXO_CAP_INTERNAL 191 bool "Use internal load capacitors" 192 193endchoice 194 195config SOC_HFXO_CAP_INT_VALUE_X2 196 int "Doubled value of HFXO internal load capacitors (in pF)" 197 depends on SOC_HFXO_CAP_INTERNAL 198 range 14 40 199 help 200 Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps 201 can be enabled on pins XC1 and XC2. This option specifies doubled 202 capacitance value for the two capacitors. Set it to 14 to get 7.0 pF 203 for each capacitor, 15 to get 7.5 pF, and so on. 204 205endif # !TRUSTED_EXECUTION_NONSECURE 206 207endif # SOC_NRF5340_CPUAPP 208 209 210config NRF_ENABLE_CACHE 211 bool "Enable cache" 212 depends on (SOC_NRF5340_CPUAPP && !TRUSTED_EXECUTION_NONSECURE) \ 213 || SOC_NRF5340_CPUNET 214 default y 215 help 216 Instruction and Data cache is available on nRF5340 CPUAPP 217 (Application MCU). It may only be accessed by Secure code. 218 219 Instruction cache only (I-Cache) is available in nRF5340 220 CPUNET (Network MCU). 221
