1# Nordic Semiconductor nRF53 MCU line
2
3# Copyright (c) 2019 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6if SOC_SERIES_NRF53X
7config SOC_NRF5340_CPUAPP
8	bool
9	select CPU_HAS_NRF_IDAU
10	select CPU_HAS_FPU
11	select ARMV8_M_DSP
12	select HAS_POWEROFF
13	select SOC_COMPATIBLE_NRF5340_CPUAPP
14	imply SOC_NRF53_RTC_PRETICK
15
16config SOC_NRF5340_CPUNET
17	bool
18	select ARM_ON_EXIT_CPU_IDLE
19	select SOC_COMPATIBLE_NRF5340_CPUNET
20	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
21	imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
22
23choice
24	prompt "nRF53x MCU Selection"
25
26config SOC_NRF5340_CPUAPP_QKAA
27	bool "NRF5340_CPUAPP_QKAA"
28	select SOC_NRF5340_CPUAPP
29
30config SOC_NRF5340_CPUNET_QKAA
31	bool "NRF5340_CPUNET_QKAA"
32	select SOC_NRF5340_CPUNET
33
34endchoice
35
36config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
37	bool "Workaround for nRF5340 anomaly 160"
38	imply SOC_NRF53_ANOMALY_160_WORKAROUND
39	help
40	  Indicates that the workaround for the anomaly 160 that affects
41	  the nRF5340 SoC should be applied.
42	  This option is enabled by default for the Application MCU when
43	  DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
44	  and always for the Network MCU.
45	  If this option is enabled, but the workaround cannot be applied,
46	  because the system clock is disabled, a related cmake warning is
47	  issued.
48
49config SOC_NRF53_ANOMALY_160_WORKAROUND
50	bool
51	depends on SYS_CLOCK_EXISTS
52	select ARM_ON_ENTER_CPU_IDLE_HOOK
53
54config SOC_NRF53_RTC_PRETICK
55	bool "Pre-tick workaround for nRF5340 anomaly 165"
56	depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
57	select NRFX_DPPI
58	select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
59	select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
60	help
61	  Indicates that the pre-tick workaround for the anomaly 165 that affects
62	  the nRF5340 SoC should be applied. The workaround applies to wake ups caused
63	  by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
64	  enabled through INTENSET register. The case when these events are generated
65	  by EVTEN but without interrupts enabled through INTENSET is not handled.
66	  The EVENTS_TICK event is not handled.
67
68if SOC_NRF53_RTC_PRETICK
69
70config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
71	int "IPC 0 channel for RTC pretick"
72	range 0 15
73	default 10
74
75config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
76	int "IPC 1 channel for RTC pretick"
77	range 0 15
78	default 11
79
80endif
81
82if SOC_NRF5340_CPUAPP
83
84config SOC_DCDC_NRF53X_APP
85	bool
86	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
87	help
88	  Enable nRF53 series System on Chip Application MCU DC/DC converter.
89
90config SOC_DCDC_NRF53X_NET
91	bool
92	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
93	help
94	  Enable nRF53 series System on Chip Network MCU DC/DC converter.
95
96config SOC_DCDC_NRF53X_HV
97	bool
98	help
99	  Enable nRF53 series System on Chip High Voltage DC/DC converter.
100
101config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
102	bool
103	depends on NRF_SOC_SECURE_SUPPORTED
104	help
105	  hidden option for including the nRF GPIO pin forwarding
106
107if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
108
109config SOC_ENABLE_LFXO
110	bool "LFXO"
111	default y
112	help
113	  Enable the low-frequency oscillator (LFXO) functionality on XL1 and
114	  XL2 pins.
115	  This option must be enabled if either application or network core is
116	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
117	  GPIOs.
118
119choice SOC_LFXO_LOAD_CAPACITANCE
120	prompt "LFXO load capacitance"
121	depends on SOC_ENABLE_LFXO
122	default SOC_LFXO_CAP_INT_7PF
123
124config SOC_LFXO_CAP_EXTERNAL
125	bool "Use external load capacitors"
126
127config SOC_LFXO_CAP_INT_6PF
128	bool "6 pF internal load capacitance"
129
130config SOC_LFXO_CAP_INT_7PF
131	bool "7 pF internal load capacitance"
132
133config SOC_LFXO_CAP_INT_9PF
134	bool "9 pF internal load capacitance"
135
136endchoice
137
138choice SOC_HFXO_LOAD_CAPACITANCE
139	prompt "HFXO load capacitance"
140	default SOC_HFXO_CAP_DEFAULT
141
142config SOC_HFXO_CAP_DEFAULT
143	bool "SoC default"
144	help
145	  When this option is used, the SoC initialization routine does not
146	  touch the XOSC32MCAPS register value, so the default setting for
147	  the SoC is in effect. Please note that this may not necessarily be
148	  the reset value (0) for the register, as the register can be set
149	  during the device trimming in the SystemInit() function.
150
151config SOC_HFXO_CAP_EXTERNAL
152	bool "Use external load capacitors"
153
154config SOC_HFXO_CAP_INTERNAL
155	bool "Use internal load capacitors"
156	depends on NRF_SOC_SECURE_SUPPORTED
157
158endchoice
159
160config SOC_HFXO_CAP_INT_VALUE_X2
161	int "Doubled value of HFXO internal load capacitors (in pF)"
162	depends on SOC_HFXO_CAP_INTERNAL
163	range 14 40
164	help
165	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
166	  can be enabled on pins XC1 and XC2. This option specifies doubled
167	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
168	  for each capacitor, 15 to get 7.5 pF, and so on.
169
170endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
171
172endif # SOC_NRF5340_CPUAPP
173
174
175config NRF_ENABLE_CACHE
176	bool "Cache"
177	depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
178			|| SOC_NRF5340_CPUNET
179	default y
180	help
181	  Instruction and Data cache is available on nRF5340 CPUAPP
182	  (Application MCU). It may only be accessed by Secure code.
183
184	  Instruction cache only (I-Cache) is available in nRF5340
185	  CPUNET (Network MCU).
186
187config BUILD_WITH_TFM
188	# TF-M nRF53 platform enables the cache unconditionally.
189	select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
190
191config NRF53_SYNC_RTC
192	bool "RTC clock synchronization"
193	default y if LOG && !LOG_MODE_MINIMAL
194	depends on NRF_RTC_TIMER
195	select NRFX_DPPI
196	select MBOX if !IPM
197
198if NRF53_SYNC_RTC
199
200module = SYNC_RTC
201module-str = Synchronized RTC
202source "subsys/logging/Kconfig.template.log_config"
203
204config NRF53_SYNC_RTC_INIT_PRIORITY
205	int "nRF53 Synchronized RTC init priority"
206	default APPLICATION_INIT_PRIORITY
207	help
208	  nRF53 Synchronized RTC initialization priority.
209
210config NRF_RTC_TIMER_USER_CHAN_COUNT
211	default 2 if NRF_802154_RADIO_DRIVER && SOC_NRF5340_CPUNET
212	default 3 if NRF_802154_RADIO_DRIVER
213	default 1
214
215config NRF53_SYNC_RTC_LOG_TIMESTAMP
216	bool "Use Synchronized RTC for logging timestamp"
217	default y
218
219config NRF53_SYNC_RTC_IPM_OUT
220	int "IPM channel from APP to NET"
221	range 0 15
222	default 7 if SOC_NRF5340_CPUAPP
223	default 8
224
225config NRF53_SYNC_RTC_IPM_IN
226	int "IPM channel from APP to NET"
227	range 0 15
228	default 8 if SOC_NRF5340_CPUAPP
229	default 7
230
231ipm_num = 0
232rsource "Kconfig.sync_rtc_ipm"
233ipm_num = 1
234rsource "Kconfig.sync_rtc_ipm"
235ipm_num = 2
236rsource "Kconfig.sync_rtc_ipm"
237ipm_num = 3
238rsource "Kconfig.sync_rtc_ipm"
239ipm_num = 4
240rsource "Kconfig.sync_rtc_ipm"
241ipm_num = 5
242rsource "Kconfig.sync_rtc_ipm"
243ipm_num = 6
244rsource "Kconfig.sync_rtc_ipm"
245ipm_num = 7
246rsource "Kconfig.sync_rtc_ipm"
247ipm_num = 8
248rsource "Kconfig.sync_rtc_ipm"
249ipm_num = 9
250rsource "Kconfig.sync_rtc_ipm"
251ipm_num = 10
252rsource "Kconfig.sync_rtc_ipm"
253ipm_num = 11
254rsource "Kconfig.sync_rtc_ipm"
255ipm_num = 12
256rsource "Kconfig.sync_rtc_ipm"
257ipm_num = 13
258rsource "Kconfig.sync_rtc_ipm"
259ipm_num = 14
260rsource "Kconfig.sync_rtc_ipm"
261ipm_num = 15
262rsource "Kconfig.sync_rtc_ipm"
263
264endif # NRF53_SYNC_RTC
265endif # SOC_SERIES_NRF53X
266