1# i.MX RT series 2 3# Copyright (c) 2017-2021, NXP 4# SPDX-License-Identifier: Apache-2.0 5 6choice 7 prompt "i.MX RT Selection" 8 depends on SOC_SERIES_IMX_RT 9 10config SOC_MIMXRT1011 11 bool "SOC_MIMXRT1011" 12 select SOC_SERIES_IMX_RT10XX 13 select HAS_MCUX 14 select HAS_MCUX_CACHE 15 select HAS_MCUX_CCM 16 select HAS_MCUX_FLEXSPI 17 select HAS_MCUX_IGPIO 18 select HAS_MCUX_LPI2C 19 select HAS_MCUX_LPSPI 20 select HAS_MCUX_LPUART 21 select HAS_MCUX_GPT 22 select HAS_MCUX_TRNG 23 select CPU_HAS_ARM_MPU 24 select INIT_SYS_PLL 25 select INIT_USB1_PLL 26 select INIT_ENET_PLL 27 select HAS_MCUX_USB_EHCI 28 select HAS_MCUX_USDHC1 29 select HAS_MCUX_USDHC2 30 select HAS_MCUX_EDMA 31 32config SOC_MIMXRT1015 33 bool "SOC_MIMXRT1015" 34 select SOC_SERIES_IMX_RT10XX 35 select HAS_MCUX 36 select HAS_MCUX_CACHE 37 select HAS_MCUX_CCM 38 select HAS_MCUX_FLEXSPI 39 select HAS_MCUX_IGPIO 40 select HAS_MCUX_LPI2C 41 select HAS_MCUX_LPSPI 42 select HAS_MCUX_LPUART 43 select HAS_MCUX_GPT 44 select HAS_MCUX_TRNG 45 select CPU_HAS_FPU_DOUBLE_PRECISION 46 select CPU_HAS_ARM_MPU 47 select INIT_SYS_PLL 48 select INIT_USB1_PLL 49 select INIT_ENET_PLL 50 select HAS_MCUX_USB_EHCI 51 select HAS_MCUX_USDHC1 52 select HAS_MCUX_USDHC2 53 select HAS_MCUX_EDMA 54 55config SOC_MIMXRT1021 56 bool "SOC_MIMXRT1021" 57 select SOC_SERIES_IMX_RT10XX 58 select HAS_MCUX 59 select HAS_MCUX_CACHE 60 select HAS_MCUX_CCM 61 select HAS_MCUX_ENET 62 select HAS_MCUX_FLEXSPI 63 select HAS_MCUX_IGPIO 64 select HAS_MCUX_LPI2C 65 select HAS_MCUX_LPSPI 66 select HAS_MCUX_LPUART 67 select HAS_MCUX_GPT 68 select HAS_MCUX_SEMC 69 select HAS_MCUX_TRNG 70 select CPU_HAS_FPU_DOUBLE_PRECISION 71 select CPU_HAS_ARM_MPU 72 select INIT_SYS_PLL 73 select INIT_USB1_PLL 74 select INIT_ENET_PLL 75 select HAS_MCUX_USB_EHCI 76 select HAS_MCUX_USDHC1 77 select HAS_MCUX_USDHC2 78 select HAS_MCUX_EDMA 79 select HAS_MCUX_FLEXCAN 80 81config SOC_MIMXRT1024 82 bool "SOC_MIMXRT1024" 83 select SOC_SERIES_IMX_RT10XX 84 select HAS_MCUX 85 select HAS_MCUX_CACHE 86 select HAS_MCUX_CCM 87 select HAS_MCUX_ENET 88 select HAS_MCUX_FLEXSPI 89 select HAS_MCUX_IGPIO 90 select HAS_MCUX_LPI2C 91 select HAS_MCUX_LPSPI 92 select HAS_MCUX_LPUART 93 select HAS_MCUX_GPT 94 select HAS_MCUX_SEMC 95 select HAS_MCUX_TRNG 96 select CPU_HAS_FPU_DOUBLE_PRECISION 97 select CPU_HAS_ARM_MPU 98 select INIT_SYS_PLL 99 select INIT_USB1_PLL 100 select INIT_ENET_PLL 101 select HAS_MCUX_USB_EHCI 102 select HAS_MCUX_USDHC1 103 select HAS_MCUX_USDHC2 104 select HAS_MCUX_EDMA 105 select HAS_MCUX_FLEXCAN 106 107config SOC_MIMXRT1051 108 bool "SOC_MIMXRT1051" 109 select SOC_SERIES_IMX_RT10XX 110 select HAS_MCUX 111 select HAS_MCUX_CACHE 112 select HAS_MCUX_CCM 113 select HAS_MCUX_ENET 114 select HAS_MCUX_FLEXSPI 115 select HAS_MCUX_IGPIO 116 select HAS_MCUX_LPI2C 117 select HAS_MCUX_LPSPI 118 select HAS_MCUX_LPUART 119 select HAS_MCUX_GPT 120 select HAS_MCUX_SEMC 121 select HAS_MCUX_TRNG 122 select CPU_HAS_FPU_DOUBLE_PRECISION 123 select CPU_HAS_ARM_MPU 124 select INIT_ARM_PLL 125 select INIT_SYS_PLL 126 select INIT_USB1_PLL 127 select HAS_MCUX_USB_EHCI 128 select HAS_MCUX_USDHC1 129 select HAS_MCUX_USDHC2 130 select HAS_MCUX_CSI 131 select HAS_MCUX_EDMA 132 select HAS_MCUX_FLEXCAN 133 134config SOC_MIMXRT1052 135 bool "SOC_MIMXRT1052" 136 select SOC_SERIES_IMX_RT10XX 137 select HAS_MCUX 138 select HAS_MCUX_CACHE 139 select HAS_MCUX_CCM 140 select HAS_MCUX_ELCDIF 141 select HAS_MCUX_ENET 142 select HAS_MCUX_FLEXSPI 143 select HAS_MCUX_IGPIO 144 select HAS_MCUX_LPI2C 145 select HAS_MCUX_LPSPI 146 select HAS_MCUX_LPUART 147 select HAS_MCUX_GPT 148 select HAS_MCUX_SEMC 149 select HAS_MCUX_TRNG 150 select CPU_HAS_FPU_DOUBLE_PRECISION 151 select CPU_HAS_ARM_MPU 152 select INIT_ARM_PLL 153 select INIT_SYS_PLL 154 select INIT_USB1_PLL 155 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 156 select INIT_ENET_PLL if NET_L2_ETHERNET 157 select HAS_MCUX_USB_EHCI 158 select HAS_MCUX_USDHC1 159 select HAS_MCUX_USDHC2 160 select HAS_MCUX_CSI 161 select HAS_MCUX_EDMA 162 select HAS_MCUX_FLEXCAN 163 select HAS_MCUX_PWM 164 165config SOC_MIMXRT1061 166 bool "SOC_MIMXRT1061" 167 select SOC_SERIES_IMX_RT10XX 168 select HAS_MCUX 169 select HAS_MCUX_CACHE 170 select HAS_MCUX_CCM 171 select HAS_MCUX_ENET 172 select HAS_MCUX_FLEXSPI 173 select HAS_MCUX_IGPIO 174 select HAS_MCUX_LPI2C 175 select HAS_MCUX_LPSPI 176 select HAS_MCUX_LPUART 177 select HAS_MCUX_GPT 178 select HAS_MCUX_SEMC 179 select HAS_MCUX_TRNG 180 select CPU_HAS_FPU_DOUBLE_PRECISION 181 select CPU_HAS_ARM_MPU 182 select INIT_ARM_PLL 183 select INIT_SYS_PLL 184 select INIT_USB1_PLL 185 select HAS_MCUX_USB_EHCI 186 select HAS_MCUX_USDHC1 187 select HAS_MCUX_USDHC2 188 select HAS_MCUX_CSI 189 select HAS_MCUX_EDMA 190 select HAS_MCUX_FLEXCAN 191 192config SOC_MIMXRT1062 193 bool "SOC_MIMXRT1062" 194 select SOC_SERIES_IMX_RT10XX 195 select HAS_MCUX 196 select HAS_MCUX_CACHE 197 select HAS_MCUX_CCM 198 select HAS_MCUX_ELCDIF 199 select HAS_MCUX_ENET 200 select HAS_MCUX_FLEXSPI 201 select HAS_MCUX_PWM 202 select HAS_MCUX_IGPIO 203 select HAS_MCUX_LPI2C 204 select HAS_MCUX_LPSPI 205 select HAS_MCUX_LPUART 206 select HAS_MCUX_GPT 207 select HAS_MCUX_SEMC 208 select HAS_MCUX_TRNG 209 select CPU_HAS_FPU_DOUBLE_PRECISION 210 select CPU_HAS_ARM_MPU 211 select INIT_ARM_PLL 212 select INIT_SYS_PLL 213 select INIT_USB1_PLL 214 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 215 select INIT_ENET_PLL if NET_L2_ETHERNET 216 select HAS_MCUX_USB_EHCI 217 select HAS_MCUX_USDHC1 218 select HAS_MCUX_USDHC2 219 select HAS_MCUX_CSI 220 select HAS_MCUX_EDMA 221 select HAS_MCUX_FLEXCAN 222 223config SOC_MIMXRT1064 224 bool "SOC_MIMXRT1064" 225 select SOC_SERIES_IMX_RT10XX 226 select HAS_MCUX 227 select HAS_MCUX_CACHE 228 select HAS_MCUX_CCM 229 select HAS_MCUX_ELCDIF 230 select HAS_MCUX_ENET 231 select HAS_MCUX_FLEXSPI 232 select HAS_MCUX_PWM 233 select HAS_MCUX_IGPIO 234 select HAS_MCUX_LPI2C 235 select HAS_MCUX_LPSPI 236 select HAS_MCUX_LPUART 237 select HAS_MCUX_GPT 238 select HAS_MCUX_SEMC 239 select HAS_MCUX_TRNG 240 select CPU_HAS_FPU_DOUBLE_PRECISION 241 select CPU_HAS_ARM_MPU 242 select INIT_ARM_PLL 243 select INIT_SYS_PLL 244 select INIT_USB1_PLL 245 select INIT_VIDEO_PLL if DISPLAY_MCUX_ELCDIF 246 select INIT_ENET_PLL if NET_L2_ETHERNET 247 select HAS_MCUX_USB_EHCI 248 select HAS_MCUX_USDHC1 249 select HAS_MCUX_USDHC2 250 select HAS_MCUX_CSI 251 select HAS_MCUX_EDMA 252 select HAS_MCUX_FLEXCAN 253 254config SOC_MIMXRT1176_CM7 255 bool "SOC_MIMXRT1176_CM7" 256 select CPU_CORTEX_M7 257 select CPU_CORTEX_M_HAS_DWT 258 select SOC_SERIES_IMX_RT11XX 259 select HAS_MCUX_CACHE 260 select HAS_MCUX 261 select HAS_MCUX_SEMC 262 select HAS_MCUX_CCM_REV2 263 select HAS_MCUX_IGPIO 264 select HAS_MCUX_LPI2C 265 select HAS_MCUX_LPSPI 266 select HAS_MCUX_LPADC 267 select HAS_MCUX_LPUART 268 select HAS_MCUX_GPT 269 select HAS_MCUX_FLEXCAN 270 select CPU_HAS_ARM_MPU 271 select INIT_ARM_PLL 272 select INIT_ENET_PLL if NET_L2_ETHERNET 273 select INIT_VIDEO_PLL 274 select HAS_MCUX_EDMA 275 select CPU_HAS_FPU_DOUBLE_PRECISION 276 select ADJUST_DCDC 277 select BYPASS_LDO_LPSR 278 select ADJUST_LDO 279 280config SOC_MIMXRT1176_CM4 281 bool "SOC_MIMXRT1176_CM4" 282 select CPU_CORTEX_M4 283 select SOC_SERIES_IMX_RT11XX 284 select HAS_MCUX_CACHE 285 select HAS_MCUX 286 select HAS_MCUX_SEMC 287 select HAS_MCUX_CCM_REV2 288 select HAS_MCUX_IGPIO 289 select HAS_MCUX_LPI2C 290 select HAS_MCUX_LPSPI 291 select HAS_MCUX_LPUART 292 select HAS_MCUX_GPT 293 select CPU_HAS_ARM_MPU 294 select INIT_ARM_PLL 295 select INIT_ENET_PLL if NET_L2_ETHERNET 296 select INIT_VIDEO_PLL 297 select HAS_MCUX_EDMA 298 299endchoice 300 301if SOC_SERIES_IMX_RT 302 303config SOC_PART_NUMBER_MIMXRT1011CAE4A 304 bool 305 306config SOC_PART_NUMBER_MIMXRT1011DAE5A 307 bool 308 309config SOC_PART_NUMBER_MIMXRT1015CAF4A 310 bool 311 312config SOC_PART_NUMBER_MIMXRT1015DAF5A 313 bool 314 315config SOC_PART_NUMBER_MIMXRT1021CAF4A 316 bool 317 318config SOC_PART_NUMBER_MIMXRT1021CAG4A 319 bool 320 321config SOC_PART_NUMBER_MIMXRT1021DAF5A 322 bool 323 324config SOC_PART_NUMBER_MIMXRT1021DAG5A 325 bool 326 327config SOC_PART_NUMBER_MIMXRT1024CAG4A 328 bool 329 330config SOC_PART_NUMBER_MIMXRT1024DAG5A 331 bool 332 333config SOC_PART_NUMBER_MIMXRT1051CVL5A 334 bool 335 336config SOC_PART_NUMBER_MIMXRT1051DVL6A 337 bool 338 339config SOC_PART_NUMBER_MIMXRT1052CVJ5B 340 bool 341 342config SOC_PART_NUMBER_MIMXRT1052CVL5A 343 bool 344 345config SOC_PART_NUMBER_MIMXRT1052CVL5B 346 bool 347 348config SOC_PART_NUMBER_MIMXRT1052DVJ6B 349 bool 350 351config SOC_PART_NUMBER_MIMXRT1052DVL6A 352 bool 353 354config SOC_PART_NUMBER_MIMXRT1052DVL6B 355 bool 356 357config SOC_PART_NUMBER_MIMXRT1061CVL5A 358 bool 359 360config SOC_PART_NUMBER_MIMXRT1061DVL6A 361 bool 362 363config SOC_PART_NUMBER_MIMXRT1062CVL5A 364 bool 365 366config SOC_PART_NUMBER_MIMXRT1062DVJ6A 367 bool 368 369config SOC_PART_NUMBER_MIMXRT1062DVL6A 370 bool 371 372config SOC_PART_NUMBER_MIMXRT1064CVL5A 373 bool 374 375config SOC_PART_NUMBER_MIMXRT1064DVL6A 376 bool 377 378config SOC_PART_NUMBER_MIMXRT1176AVM8A 379 bool 380 381config SOC_PART_NUMBER_MIMXRT1176CVM8A 382 bool 383 384config SOC_PART_NUMBER_MIMXRT1176DVMAA 385 bool 386 387config SOC_PART_NUMBER_MIMXRT1175AVM8A 388 bool 389 390config SOC_PART_NUMBER_MIMXRT1175CVM8A 391 bool 392 393config SOC_PART_NUMBER_MIMXRT1175DVMAA 394 bool 395 396config SOC_PART_NUMBER_MIMXRT1173CVM8A 397 bool 398 399config SOC_PART_NUMBER_MIMXRT1172AVM8A 400 bool 401 402config SOC_PART_NUMBER_MIMXRT1172CVM8A 403 bool 404 405config SOC_PART_NUMBER_MIMXRT1172DVMAA 406 bool 407 408config SOC_PART_NUMBER_MIMXRT1171AVM8A 409 bool 410 411config SOC_PART_NUMBER_MIMXRT1171CVM8A 412 bool 413 414config SOC_PART_NUMBER_MIMXRT1171DVMAA 415 bool 416 417config SOC_PART_NUMBER_IMX_RT 418 string 419 default "MIMXRT1011CAE4A" if SOC_PART_NUMBER_MIMXRT1011CAE4A 420 default "MIMXRT1011DAE5A" if SOC_PART_NUMBER_MIMXRT1011DAE5A 421 default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A 422 default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A 423 default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A 424 default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A 425 default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A 426 default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A 427 default "MIMXRT1024CAG4A" if SOC_PART_NUMBER_MIMXRT1024CAG4A 428 default "MIMXRT1024DAG5A" if SOC_PART_NUMBER_MIMXRT1024DAG5A 429 default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A 430 default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A 431 default "MIMXRT1052CVJ5B" if SOC_PART_NUMBER_MIMXRT1052CVJ5B 432 default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A 433 default "MIMXRT1052CVL5B" if SOC_PART_NUMBER_MIMXRT1052CVL5B 434 default "MIMXRT1052DVJ6B" if SOC_PART_NUMBER_MIMXRT1052DVJ6B 435 default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A 436 default "MIMXRT1052DVL6B" if SOC_PART_NUMBER_MIMXRT1052DVL6B 437 default "MIMXRT1061CVL5A" if SOC_PART_NUMBER_MIMXRT1061CVL5A 438 default "MIMXRT1061DVL6A" if SOC_PART_NUMBER_MIMXRT1061DVL6A 439 default "MIMXRT1062CVL5A" if SOC_PART_NUMBER_MIMXRT1062CVL5A 440 default "MIMXRT1062DVJ6A" if SOC_PART_NUMBER_MIMXRT1062DVJ6A 441 default "MIMXRT1062DVL6A" if SOC_PART_NUMBER_MIMXRT1062DVL6A 442 default "MIMXRT1064CVL5A" if SOC_PART_NUMBER_MIMXRT1064CVL5A 443 default "MIMXRT1064DVL6A" if SOC_PART_NUMBER_MIMXRT1064DVL6A 444 default "MIMXRT1176AVM8A" if SOC_PART_NUMBER_MIMXRT1176AVM8A 445 default "MIMXRT1176CVM8A" if SOC_PART_NUMBER_MIMXRT1176CVM8A 446 default "MIMXRT1176DVMAA" if SOC_PART_NUMBER_MIMXRT1176DVMAA 447 default "MIMXRT1175AVM8A" if SOC_PART_NUMBER_MIMXRT1175AVM8A 448 default "MIMXRT1175CVM8A" if SOC_PART_NUMBER_MIMXRT1175CVM8A 449 default "MIMXRT1175DVMAA" if SOC_PART_NUMBER_MIMXRT1175DVMAA 450 default "MIMXRT1173CVM8A" if SOC_PART_NUMBER_MIMXRT1173CVM8A 451 default "MIMXRT1172AVM8A" if SOC_PART_NUMBER_MIMXRT1172AVM8A 452 default "MIMXRT1172CVM8A" if SOC_PART_NUMBER_MIMXRT1172CVM8A 453 default "MIMXRT1172DVMAA" if SOC_PART_NUMBER_MIMXRT1172DVMAA 454 default "MIMXRT1171AVM8A" if SOC_PART_NUMBER_MIMXRT1171AVM8A 455 default "MIMXRT1171CVM8A" if SOC_PART_NUMBER_MIMXRT1171CVM8A 456 default "MIMXRT1171DVMAA" if SOC_PART_NUMBER_MIMXRT1171DVMAA 457 help 458 This string holds the full part number of the SoC. It is a hidden option 459 that you should not set directly. The part number selection choice defines 460 the default value for this string. 461 462config SOC_SERIES_IMX_RT10XX 463 bool "i.MX RT 10XX Series" 464 select CPU_CORTEX_M7 465 select CPU_CORTEX_M_HAS_DWT 466 467config SOC_SERIES_IMX_RT11XX 468 bool "i.MX RT 11XX Series" 469 470config INIT_ARM_PLL 471 bool "Initialize ARM PLL" 472 473config INIT_SYS_PLL 474 bool "Initialize SYS PLL" 475 476config INIT_USB1_PLL 477 bool "Initialize USB1 PLL" 478 479config INIT_VIDEO_PLL 480 bool "Initialize Video PLL" 481 482config INIT_ENET_PLL 483 bool 484 help 485 If y, the Ethernet PLL is initialized. Always enabled on e.g. 486 MIMXRT1021 - see commit 17f4d6bec7 ("soc: nxp_imx: fix ENET_PLL selection 487 for MIMXRT1021"). 488 489config HAS_ARM_DIV 490 bool "Has the divider for ARM" 491 default y 492 493config ARM_DIV 494 int "ARM clock divider" 495 range 0 7 496 default 0 497 498config AHB_DIV 499 int "AHB clock divider" 500 range 0 7 501 default 0 502 503config IPG_DIV 504 int "IPG clock divider" 505 range 0 3 506 default 0 507 508config ADJUST_DCDC 509 bool "Adjust internal DCDC output" 510 511config BYPASS_LDO_LPSR 512 bool "Bypass LDO lpsr" 513 514config ADJUST_LDO 515 bool "Adjust LDO setting" 516 517menuconfig NXP_IMX_RT_BOOT_HEADER 518 bool "Enable the boot header" 519 depends on !BOOTLOADER_MCUBOOT 520 help 521 Enable data structures required by the boot ROM to boot the 522 application from an external flash device. 523 524if NXP_IMX_RT_BOOT_HEADER 525 526choice BOOT_DEVICE 527 prompt "Boot device selection" 528 default BOOT_FLEXSPI_NOR 529 530config BOOT_FLEXSPI_NOR 531 bool "FlexSPI serial NOR" 532 533config BOOT_FLEXSPI_NAND 534 bool "FlexSPI serial NAND" 535 536config BOOT_SEMC_NOR 537 bool "SEMC parallel NOR" 538 539config BOOT_SEMC_NAND 540 bool "SEMC parallel NAND" 541 542endchoice 543 544config FLEXSPI_CONFIG_BLOCK_OFFSET 545 hex "FlexSPI config block offset" 546 default 0x0 if BOOT_FLEXSPI_NOR 547 help 548 FlexSPI configuration block consists of parameters regarding specific 549 flash devices including read command sequence, quad mode enablement 550 sequence (optional), etc. The boot ROM expectes FlexSPI configuration 551 parameter to be presented in serial nor flash. 552 553config IMAGE_VECTOR_TABLE_OFFSET 554 hex "Image vector table offset" 555 default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR 556 default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND 557 help 558 The Image Vector Table (IVT) provides the boot ROM with pointers to 559 the application entry point and device configuration data. The boot 560 ROM requires a fixed IVT offset for each type of boot device. 561 562config DEVICE_CONFIGURATION_DATA 563 bool "Enable device configuration data" 564 default y if HAS_MCUX_SEMC 565 help 566 Device configuration data (DCD) provides a sequence of commands to 567 the boot ROM to initialize components such as an SDRAM. 568 569endif # NXP_IMX_RT_BOOT_HEADER 570 571choice CODE_LOCATION 572 prompt "Code location selection" 573 default CODE_ITCM 574 575config CODE_SEMC 576 bool "Link code into external SEMC-controlled memory" 577 578config CODE_ITCM 579 bool "Link code into internal instruction tightly coupled memory (ITCM)" 580 581config CODE_FLEXSPI 582 bool "Link code into external FlexSPI-controlled memory" 583 select NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 584 585config CODE_FLEXSPI2 586 bool "Link code into internal FlexSPI-controlled memory" 587 select NXP_IMX_RT_BOOT_HEADER if !BOOTLOADER_MCUBOOT 588 589config CODE_SRAM0 590 bool "Link code into RAM_L memory (RAM_L)" 591endchoice 592 593endif # SOC_SERIES_IMX_RT 594
