1# Copyright (c) 2020 ITE Corporation. All Rights Reserved. 2# SPDX-License-Identifier: Apache-2.0 3 4config SOC_SERIES_IT8XXX2 5 select CPU_HAS_FPU if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "zephyr" || RISCV_ISA_EXT_M 6 select HAS_PM 7 select ARCH_HAS_CUSTOM_CPU_IDLE 8 select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE 9 select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING 10 11if SOC_SERIES_IT8XXX2 12 13config SOC_IT8XXX2 14 select RISCV 15 select ATOMIC_OPERATIONS_BUILTIN 16 select RISCV_ISA_RV32I 17 select RISCV_ISA_EXT_ZICSR 18 select RISCV_ISA_EXT_ZIFENCEI 19 # Workaround mul instruction bug, see: 20 # https://www.ite.com.tw/uploads/product_download/it81202-bx-chip-errata.pdf 21 select RISCV_ISA_EXT_M if !(SOC_IT81302BX || SOC_IT81202BX) 22 select RISCV_ISA_EXT_A 23 select RISCV_ISA_EXT_C 24 imply XIP 25 26config SOC_IT8XXX2_REG_SET_V1 27 bool 28 help 29 This option is selected by a variable of which soc, and will 30 determine the register for the IT81xx2 specification. 31 32config SOC_IT8XXX2_REG_SET_V2 33 bool 34 help 35 This option is selected by a variable of which soc, and will 36 determine the register for the IT82xx2 specification. 37 38config SOC_IT8XXX2_USBPD_PHY_V1 39 bool 40 help 41 This option is automatically selected by variant soc and sets 42 the USBPD PHY version. 43 44config SOC_IT8XXX2_USBPD_PHY_V2 45 bool 46 help 47 This option is automatically selected by variant soc and sets 48 the USBPD PHY version. 49 50config SOC_IT81302BX 51 select SOC_IT8XXX2_REG_SET_V1 52 select SOC_IT8XXX2_USBPD_PHY_V1 53 54config SOC_IT81202BX 55 select SOC_IT8XXX2_REG_SET_V1 56 select SOC_IT8XXX2_USBPD_PHY_V1 57 58config SOC_IT81302CX 59 select SOC_IT8XXX2_REG_SET_V1 60 select SOC_IT8XXX2_USBPD_PHY_V2 61 62config SOC_IT81202CX 63 select SOC_IT8XXX2_REG_SET_V1 64 select SOC_IT8XXX2_USBPD_PHY_V2 65 66config SOC_IT81302DX 67 select SOC_IT8XXX2_REG_SET_V1 68 select SOC_IT8XXX2_USBPD_PHY_V2 69 70config SOC_IT81202DX 71 select SOC_IT8XXX2_REG_SET_V1 72 select SOC_IT8XXX2_USBPD_PHY_V2 73 74config SOC_IT82202AX 75 select SOC_IT8XXX2_REG_SET_V2 76 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 77 select SOC_IT8XXX2_USBPD_PHY_V2 78 79config SOC_IT82302AX 80 select SOC_IT8XXX2_REG_SET_V2 81 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 82 select SOC_IT8XXX2_USBPD_PHY_V2 83 84config SOC_IT82002AW 85 select SOC_IT8XXX2_REG_SET_V2 86 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 87 select SOC_IT8XXX2_USBPD_PHY_V2 88 89config SOC_IT82002BW 90 select SOC_IT8XXX2_REG_SET_V2 91 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 92 select SOC_IT8XXX2_USBPD_PHY_V2 93 94config SOC_IT82202BW 95 select SOC_IT8XXX2_REG_SET_V2 96 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 97 select SOC_IT8XXX2_USBPD_PHY_V2 98 99config SOC_IT82302BW 100 select SOC_IT8XXX2_REG_SET_V2 101 select SOC_IT8XXX2_EC_BUS_24MHZ if !DT_HAS_ITE_IT82XX2_USB_ENABLED 102 select SOC_IT8XXX2_USBPD_PHY_V2 103 104config SOC_IT8XXX2_PLL_FLASH_48M 105 bool "Flash frequency is 48MHz" 106 default y 107 select FLASH 108 help 109 Change frequency of PLL, CPU, and flash to 48MHz during initialization. 110 111 Set n to use the default settings. 112 (PLL and CPU run at 48MHz, flash frequency is 16MHz) 113 114config SOC_IT8XXX2_GPIO_GROUP_K_L_DEFAULT_PULL_DOWN 115 bool "The pins of GPIO group K and L aren't bonding with pad" 116 default y 117 help 118 On IT81202 (128-pins package), the pins of GPIO group K and L aren't 119 bonding with pad. So we configure these pins as internal pull-down 120 at default to prevent leakage current due to floating. 121 122config SOC_IT8XXX2_GPIO_H7_DEFAULT_OUTPUT_LOW 123 bool "The GPIOH7 isn't bonding with pad and is left floating internally" 124 default y 125 help 126 On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left 127 floating internally. We need to enable internal pull-down for the pin 128 to prevent leakage current, but IT81202/IT81302 doesn't have the 129 capability to pull it down. We can only set it as output low, 130 so we enable output low for it at initialization to prevent leakage. 131 132config SOC_IT8XXX2_CPU_IDLE_GATING 133 bool 134 help 135 This option determines whether the entering CPU idle mode can be 136 gated by individual drivers. When this option is disabled, CPU idle 137 mode is always permitted. 138 139config SOC_IT8XXX2_EC_BUS_24MHZ 140 bool "EC bus is 24MHz" 141 help 142 Raise EC bus to 24MHz (default is 8MHz). 143 This reduces read/write EC registers latency by 50%. 144 NOTE: There is limitation to enabling this config on it81xx2 series. 145 The clock_frequency of ite,it8xxx2-i2c node (i2c0, i2c1, and i2c2) will 146 be fixed at 400KHz. 147 148config SOC_IT8XXX2_JTAG_DEBUG_INTERFACE 149 bool "JTAG debug interface" 150 help 151 If enabled, the below five pins are configured as JTAG debug interface: 152 - GPIOA0 -> TCK 153 - GPIOA1 -> TDI 154 - GPIOA4 -> TDO 155 - GPIOA5 -> TMS 156 - GPIOA6 -> TRST 157 Supported I/O voltage is 3.3V. 158 159config SOC_IT8XXX2_LCVCO 160 bool "LCVCO calibration" 161 depends on SOC_IT8XXX2_INT_32K 162 help 163 The LCVCO is a highly precise clock controller used for 164 calibrating the frequency shift of the PLL. Enabling this 165 option allows for supported LCVCO calibration, improving 166 the accuracy of the USB clock. 167 168choice 169 prompt "Clock source for PLL reference clock" 170 171config SOC_IT8XXX2_INT_32K 172 bool "Use the +/-2.3% internal clock generator" 173 174config SOC_IT8XXX2_EXT_32K 175 bool "Use external 32.768 kHz clock source" 176 177endchoice 178 179config SOC_IT8XXX2_USE_ILM 180 bool 181 default y 182 help 183 If enabled, Instruction Local Memory (ILM) will be configured to execute 184 code placed in the .__ram_code section out of RAM. This consumes RAM in 185 blocks of 4 kilobytes, but performance of code in ILM is much more 186 predictable than executing from Flash directly, and some code (such as code 187 that writes to the internal Flash) must execute out of RAM. 188 189config SOC_IT8XXX2_EXCEPTIONS_IN_RAM 190 bool "Place exception handling code in RAM" 191 default y 192 select SOC_IT8XXX2_USE_ILM 193 help 194 Place exception handling (ISR entry/exit and related) code in ILM, which 195 has more reliable performance characteristics than executing directly from 196 Flash. This can significantly improve performance when under I-cache 197 pressure. 198 199config SOC_IT8XXX2_LIBRARY_TO_RAM 200 bool 201 help 202 If this is selected it means that there is a library that needs to be excluded 203 from the text section. 204 205config SOC_IT8XXX2_SERIAL_IN_RAM 206 bool "Place serial handling code in RAM" 207 select SOC_IT8XXX2_USE_ILM 208 select SOC_IT8XXX2_LIBRARY_TO_RAM 209 help 210 Place serial handling (Include uart_ns16550.c and uart_ite_it8xxx2.c) code 211 in ILM. This can improve performance. 212 213config SOC_IT8XXX2_KERNEL_IN_RAM 214 bool "Place kernel handling code in RAM" 215 select SOC_IT8XXX2_USE_ILM 216 select SOC_IT8XXX2_LIBRARY_TO_RAM 217 help 218 Place kernel handling code in ILM. This can significantly improve performance. 219 220config SOC_IT8XXX2_ZEPHYR_IN_RAM 221 bool "Place zephyr handling code in RAM" 222 select SOC_IT8XXX2_USE_ILM 223 select SOC_IT8XXX2_LIBRARY_TO_RAM 224 help 225 Place zephyr handling code in ILM. This can significantly improve performance. 226 227config SOC_IT8XXX2_SHA256_HW_ACCELERATE 228 bool "HW SHA256 calculation" 229 help 230 IT8XXX2 HW support sha256 calculation, and its calculation is faster than FW. 231 We place SHA256 message, hash and key data (total 512bytes) in RAM. 232 If we enable this config, because HW limits, the sha256 data must place in 233 first 4KB of RAM. 234 235config SOC_IT8XXX2_SHA256_BLOCK_SIZE 236 hex 237 default 0x500 if SOC_IT8XXX2_REG_SET_V2 238 default 0x200 239 240DT_CHOSEN_ZEPHYR_FLASH := zephyr,flash 241 242config SOC_IT8XXX2_FLASH_SIZE_BYTES 243 hex 244 default $(dt_chosen_reg_size_hex,$(DT_CHOSEN_ZEPHYR_FLASH)) 245 help 246 Total size of writable flash. 247 248config ILM_MAX_SIZE 249 int "ILM Size in kB" 250 default SRAM_SIZE 251 252endif # SOC_SERIES_IT8XXX2 253
