1# Copyright (c) 2022-2024 Intel Corporation
2#
3# SPDX-License-Identifier: Apache-2.0
4
5config SOC_SERIES_INTEL_ADSP_ACE
6	select XTENSA
7	select XTENSA_HAL if (("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc") && ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang"))
8	select ATOMIC_OPERATIONS_BUILTIN if "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc"
9	select ARCH_HAS_COHERENCE
10	select SCHED_IPI_SUPPORTED
11	select ARCH_HAS_CUSTOM_CPU_IDLE
12	select DW_ICTL_ACE
13	select SOC_HAS_RUNTIME_NUM_CPUS
14	select HAS_PM
15	select XTENSA_CPU_HAS_HIFI3
16	select XTENSA_CPU_HAS_HIFI4
17	select ARCH_HAS_RESERVED_PAGE_FRAMES if MMU
18
19config SOC_INTEL_COMM_WIDGET
20	bool "Intel Communication Widget driver"
21	default y
22	depends on DT_HAS_INTEL_ADSP_COMMUNICATION_WIDGET_ENABLED
23	help
24	  Select this to enable Intel Communication Widget driver.
25	  DSP Communication Widget is a device for generic sideband message transmit/receive.
26
27config SRAM_RETENTION_MODE
28	bool "SRAM retention mode during initialization"
29	default y
30	help
31	  When this option is enabled, the SRAM retention mode will be
32	  activated during the firmware boot-up process. If disabled,
33	  the retention mode will not be activated.
34