1# Nordic Semiconductor nRF53 MCU line
2
3# Copyright (c) 2019 Nordic Semiconductor ASA
4# SPDX-License-Identifier: Apache-2.0
5
6config SOC_SERIES_NRF53X
7	bool
8	select ARM
9	select SOC_COMPATIBLE_NRF53X
10	select CPU_CORTEX_M33
11	select CPU_CORTEX_M_HAS_DWT
12	select CPU_HAS_ARM_MPU
13	imply XIP
14	select HAS_NRFX
15	select HAS_NORDIC_DRIVERS
16	select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
17	select HAS_SWO
18	help
19	 Enable support for NRF53 MCU series
20
21config SOC_NRF5340_CPUAPP
22	select CPU_HAS_NRF_IDAU
23	select CPU_HAS_FPU
24	select ARMV8_M_DSP
25	select HAS_POWEROFF
26	select SOC_COMPATIBLE_NRF5340_CPUAPP
27	select SOC_NRF53_CPUNET_MGMT
28	imply SOC_NRF53_RTC_PRETICK
29	imply SOC_NRF53_ANOMALY_168_WORKAROUND
30
31config SOC_NRF5340_CPUNET
32	select ARM_ON_EXIT_CPU_IDLE
33	select SOC_COMPATIBLE_NRF5340_CPUNET
34	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
35	imply SOC_NRF53_RTC_PRETICK if !WDT_NRFX
36	imply SOC_NRF53_ANOMALY_168_WORKAROUND
37
38if SOC_SERIES_NRF53X
39
40VREGMAIN_PATH := $(dt_nodelabel_path,vregmain)
41VREGRADIO_PATH := $(dt_nodelabel_path,vregradio)
42
43config SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
44	bool "Workaround for nRF5340 anomaly 160"
45	imply SOC_NRF53_ANOMALY_160_WORKAROUND
46	default y if "$(dt_node_int_prop_int,$(VREGMAIN_PATH),regulator-initial-mode)" = 1
47	default y if "$(dt_node_int_prop_int,$(VREGRADIO_PATH),regulator-initial-mode)" = 1
48	help
49	  Indicates that the workaround for the anomaly 160 that affects
50	  the nRF5340 SoC should be applied.
51	  This option is enabled by default for the Application MCU when
52	  DC/DC mode is enabled for the VREGMAIN or VREGRADIO regulator
53	  and always for the Network MCU.
54	  If this option is enabled, but the workaround cannot be applied,
55	  because the system clock is disabled, a related cmake warning is
56	  issued.
57
58config SOC_NRF53_ANOMALY_160_WORKAROUND
59	bool
60	depends on SYS_CLOCK_EXISTS
61	select ARM_ON_ENTER_CPU_IDLE_HOOK
62
63config SOC_NRF53_ANOMALY_168_WORKAROUND
64	bool "Workaround for nRF5340 anomaly 168"
65	select ARM_ON_EXIT_CPU_IDLE
66	help
67	  Indicates that the workaround for the anomaly 168 that affects
68	  the nRF5340 SoC should be applied.
69	  The workaround involves execution of 8 NOP instructions when the CPU
70	  exist its idle state (when the WFI/WFE instruction returns) and it is
71	  enabled by default for both the application and network core.
72
73config SOC_NRF53_ANOMALY_168_WORKAROUND_FOR_EXECUTION_FROM_RAM
74	bool "Extend the workaround to execution at 128 MHz from RAM"
75	depends on SOC_NRF53_ANOMALY_168_WORKAROUND && SOC_NRF5340_CPUAPP
76	help
77	  Indicates that the anomaly 168 workaround is to be extended to cover
78	  also a specific case when the WFI/WFE instruction is executed at 128
79	  MHz from RAM. Then, 26 instead of 8 NOP instructions needs to be
80	  executed after WFI/WFE. This extension is not enabled by default.
81
82config SOC_NRF53_RTC_PRETICK
83	bool "Pre-tick workaround for nRF5340 anomaly 165"
84	depends on (SYS_CLOCK_EXISTS && SOC_NRF5340_CPUNET) || SOC_NRF5340_CPUAPP
85	select NRFX_GPPI
86	select ARM_ON_ENTER_CPU_IDLE_HOOK if SOC_NRF5340_CPUNET
87	select ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK if SOC_NRF5340_CPUNET
88	help
89	  Indicates that the pre-tick workaround for the anomaly 165 that affects
90	  the nRF5340 SoC should be applied. The workaround applies to wake ups caused
91	  by EVENTS_COMPARE and EVENTS_OVRFLW on RTC0 and RTC1 for which interrupts are
92	  enabled through INTENSET register. The case when these events are generated
93	  by EVTEN but without interrupts enabled through INTENSET is not handled.
94	  The EVENTS_TICK event is not handled.
95
96if SOC_NRF53_RTC_PRETICK
97
98config SOC_NRF53_RTC_PRETICK_IPC_CH_FROM_NET
99	int "IPC 0 channel for RTC pretick"
100	range 0 15
101	default 10
102
103config SOC_NRF53_RTC_PRETICK_IPC_CH_TO_NET
104	int "IPC 1 channel for RTC pretick"
105	range 0 15
106	default 11
107
108endif
109
110if SOC_NRF5340_CPUAPP
111
112config SOC_DCDC_NRF53X_APP
113	bool
114	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
115	select DEPRECATED
116	help
117	  This option is deprecated, use devicetree instead. Example
118	  configuration:
119
120	  &vregmain {
121	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
122	  };
123
124	  Enable nRF53 series System on Chip Application MCU DC/DC converter.
125
126config SOC_DCDC_NRF53X_NET
127	bool
128	imply SOC_NRF53_ANOMALY_160_WORKAROUND_NEEDED
129	select DEPRECATED
130	help
131	  This option is deprecated, use devicetree instead. Example
132	  configuration:
133
134	  &vregradio {
135	    regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
136	  };
137
138	  Enable nRF53 series System on Chip Network MCU DC/DC converter.
139
140config SOC_DCDC_NRF53X_HV
141	bool
142	select DEPRECATED
143	help
144	  This option is deprecated, use devicetree instead. Example
145	  configuration:
146
147	  &vregh {
148	    status = "okay";
149	  };
150
151	  Enable nRF53 series System on Chip High Voltage DC/DC converter.
152
153config NRF_SPU_FLASH_REGION_SIZE
154	hex
155	default 0x4000
156	help
157	  FLASH region size for the NRF_SPU peripheral
158
159config NRF_SPU_RAM_REGION_SIZE
160	hex
161	default 0x2000
162	help
163	  RAM region size for the NRF_SPU peripheral
164
165config SOC_NRF_GPIO_FORWARDER_FOR_NRF5340
166	bool "Forward GPIO pins to network core"
167	depends on NRF_SOC_SECURE_SUPPORTED
168	default y if $(dt_compat_enabled,$(DT_COMPAT_NORDIC_NRF_GPIO_FORWARDER))
169	help
170	  Will forward configured pins with the forwarder compatible to the network core for usage.
171
172config SOC_NRF53_CPUNET_MGMT
173	bool
174	select ONOFF
175	help
176	  hidden option for including the nRF53 network CPU management
177
178config SOC_NRF53_CPUNET_ENABLE
179	bool "NRF53 Network MCU is enabled at boot time"
180	default y if NRF_802154_SER_HOST
181	select SOC_NRF53_CPUNET_MGMT
182	help
183	  This option enables releasing the Network 'force off' signal, which
184	  as a consequence will power up the Network MCU during system boot.
185	  Additionally, the option allocates GPIO pins that will be used by UARTE
186	  of the Network MCU.
187	  Note: GPIO pin allocation can only be configured by the secure Application
188	  MCU firmware, so when this option is used with the non-secure version of
189	  the board, the application needs to take into consideration, that the
190	  secure firmware image must already have configured GPIO allocation for the
191	  Network MCU.
192
193config BOARD_ENABLE_CPUNET
194	bool "[DEPRECATED] NRF53 Network MCU is enabled at boot time"
195	select SOC_NRF53_CPUNET_ENABLE
196	select DEPRECATED
197	help
198	  Use SOC_NRF53_CPUNET_ENABLE instead.
199
200if !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
201
202config SOC_ENABLE_LFXO
203	bool "LFXO"
204	select DEPRECATED
205	help
206	  This option is deprecated, use DT instead. For this option to apply,
207	  make sure to select either "internal" or "external" in the
208	  load-capacitors property.
209
210	  Enable the low-frequency oscillator (LFXO) functionality on XL1 and
211	  XL2 pins.
212	  This option must be enabled if either application or network core is
213	  to use the LFXO. Otherwise, XL1 and XL2 pins will behave as regular
214	  GPIOs.
215
216choice SOC_LFXO_LOAD_CAPACITANCE
217	prompt "LFXO load capacitance"
218	depends on SOC_ENABLE_LFXO
219
220config SOC_LFXO_CAP_EXTERNAL
221	bool "Use external load capacitors"
222	select DEPRECATED
223	help
224	  This option is deprecated, use DT instead. Example configuration:
225
226	  &lfxo {
227	      load-capacitors = "external";
228	  };
229
230config SOC_LFXO_CAP_INT_6PF
231	bool "6 pF internal load capacitance"
232	select DEPRECATED
233	help
234	  This option is deprecated, use DT instead. Example configuration:
235
236	  &lfxo {
237	      load-capacitors = "internal";
238	      load-capacitance-picofarad = <6>;
239	  };
240
241config SOC_LFXO_CAP_INT_7PF
242	bool "7 pF internal load capacitance"
243	select DEPRECATED
244	help
245	  This option is deprecated, use DT instead. Example configuration:
246
247	  &lfxo {
248	      load-capacitors = "internal";
249	      load-capacitance-picofarad = <7>;
250	  };
251
252config SOC_LFXO_CAP_INT_9PF
253	bool "9 pF internal load capacitance"
254	select DEPRECATED
255	help
256	  This option is deprecated, use DT instead. Example configuration:
257
258	  &lfxo {
259	      load-capacitors = "internal";
260	      load-capacitance-picofarad = <9>;
261	  };
262
263endchoice
264
265choice SOC_HFXO_LOAD_CAPACITANCE
266	prompt "HFXO load capacitance"
267	default SOC_HFXO_CAP_DEFAULT
268
269config SOC_HFXO_CAP_DEFAULT
270	bool "SoC default"
271	help
272	  This option is deprecated, use DT instead. For this configuration to
273	  apply, no DT changes are required from the SoC DT file defaults.
274
275	  When this option is used, the SoC initialization routine does not
276	  touch the XOSC32MCAPS register value, so the default setting for
277	  the SoC is in effect. Please note that this may not necessarily be
278	  the reset value (0) for the register, as the register can be set
279	  during the device trimming in the SystemInit() function.
280
281config SOC_HFXO_CAP_EXTERNAL
282	bool "Use external load capacitors"
283	select DEPRECATED
284	help
285	  This option is deprecated, use DT instead. Example configuration:
286
287	  &hfxo {
288	      load-capacitors = "external";
289	  };
290
291config SOC_HFXO_CAP_INTERNAL
292	bool "Use internal load capacitors"
293	depends on NRF_SOC_SECURE_SUPPORTED
294	select DEPRECATED
295	help
296	  This option is deprecated, use DT instead. Example configuration:
297
298	  &hfxo {
299	      load-capacitors = "internal";
300	      ...
301	  };
302
303	  See CONFIG_SOC_HFXO_CAP_INT_VALUE_X2 for more information.
304
305endchoice
306
307config SOC_HFXO_CAP_INT_VALUE_X2
308	int "Doubled value of HFXO internal load capacitors (in pF)"
309	depends on SOC_HFXO_CAP_INTERNAL
310	range 14 40
311	help
312	  This option is deprecated, use DT instead. Example configuration:
313
314	  &hfxo {
315	      load-capacitors = "internal";
316	      load-capacitance-femtofarad = <7000>;
317	  };
318
319	  Internal capacitors ranging from 7.0 pF to 20.0 pF in 0.5 pF steps
320	  can be enabled on pins XC1 and XC2. This option specifies doubled
321	  capacitance value for the two capacitors. Set it to 14 to get 7.0 pF
322	  for each capacitor, 15 to get 7.5 pF, and so on.
323
324endif # !TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM
325
326endif # SOC_NRF5340_CPUAPP
327
328
329config NRF_ENABLE_CACHE
330	bool "Cache"
331	depends on (SOC_NRF5340_CPUAPP && (!TRUSTED_EXECUTION_NONSECURE || BUILD_WITH_TFM)) \
332			|| SOC_NRF5340_CPUNET
333	default y
334	help
335	  Instruction and Data cache is available on nRF5340 CPUAPP
336	  (Application MCU). It may only be accessed by Secure code.
337
338	  Instruction cache only (I-Cache) is available in nRF5340
339	  CPUNET (Network MCU).
340
341config BUILD_WITH_TFM
342	# TF-M nRF53 platform enables the cache unconditionally.
343	select NRF_ENABLE_CACHE if SOC_NRF5340_CPUAPP
344
345rsource "Kconfig.sync_rtc"
346
347endif # SOC_SERIES_NRF53X
348