1# Copyright (c) 2021 Argentum Systems Ltd.
2# SPDX-License-Identifier: Apache-2.0
3
4if SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
5
6config SOC_ATMEL_SAML_DEBUG_PAUSE
7	bool "Insert a pause at boot, to allow a debugger to attach"
8	default y
9	help
10	  Issues have been observed while attempting to attach a debugger.
11	  These can be mitigated by inserting a small delay during the early boot
12	  sequence, before the system clock is configured.
13
14	  If you ever intend to attach a debugger, say y.
15	  If you are confident that you will never attach a debugger to the
16	  resulting binary, or require the best possible boot time, say n.
17
18config SOC_ATMEL_SAML_OSC32K
19	bool "Internal 32.768 kHz RC oscillator"
20	help
21	  Eable the internal 32.768 kHz RC oscillator at startup.
22	  This can then be selected as the main clock reference for the SOC.
23
24config SOC_ATMEL_SAML_XOSC32K
25	bool "External 32.768 kHz clock source"
26	help
27	  Enable the external 32.768 kHz cloud source at startup.
28	  This can then be selected as the main clock reference for the SOC.
29
30config SOC_ATMEL_SAML_XOSC32K_CRYSTAL
31	bool "External 32.768 kHz clock is a crystal oscillator"
32	depends on SOC_ATMEL_SAML_XOSC32K
33	default y
34	help
35	  Enable the crystal oscillator (if disabled, expect a clock signal on
36	  XIN32).
37
38config SOC_ATMEL_SAML_OSC16M
39	bool "Internal 16 MHz RC oscillator"
40	help
41	  Enable the internal 16 MHz RC oscillator at startup.
42	  This can then be selected as the main clock reference for the SOC.
43
44# NOTE: XOSC is not currently supported
45
46
47choice
48	prompt "Main clock reference"
49	default SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
50	help
51	  Selects the clock that will be used for the DFLL48M's reference.
52	  Main clocks, such as the CPU and AHB clocks will be derived from
53	  DFLL48M configured for 48 MHz.
54
55config SOC_ATMEL_SAML_OPENLOOP_AS_MAIN
56	bool "OPENLOOP"
57	help
58	  Note, this mode can only be used with an LDO regulator.
59
60config SOC_ATMEL_SAML_OSC32K_AS_MAIN
61	bool "OSC32K"
62	depends on SOC_ATMEL_SAML_OSC32K
63
64config SOC_ATMEL_SAML_XOSC32K_AS_MAIN
65	bool "XOSC32K"
66	depends on SOC_ATMEL_SAML_XOSC32K
67
68config SOC_ATMEL_SAML_OSC16M_AS_MAIN
69	bool "OSC16M"
70	depends on SOC_ATMEL_SAML_OSC16M
71
72endchoice
73
74config SOC_ATMEL_SAMR3X_RADIO_OFF_SETUP
75	bool "Configure LoRa radio pins if not in use"
76	default y if !LORA
77	depends on SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
78	help
79	  As detailed in DS70005356C, LoRa radio SPI pins do not have pull-ups,
80	  so when the radio is not in use, it's important that CS is kept high,
81	  to avoid unexpected behavior and increased current consumption. To
82	  further reduce power consumption, radio can be kept in reset state by
83	  keeping nRST pin low. When enabling this option, both CS and nRST will
84	  be configured high and low, respectively.
85
86endif # SOC_SERIES_SAML21 || SOC_SERIES_SAMR34 || SOC_SERIES_SAMR35
87