1# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4menu "RISCV Options"
5	depends on RISCV
6
7config ARCH
8	string
9	default "riscv64" if 64BIT
10	default "riscv32"
11
12config FLOAT_HARD
13	bool "Hard-float calling convention"
14	default y
15	depends on FPU
16	help
17	  This option enables the hard-float calling convention.
18
19config RISCV_GP
20	bool "RISC-V global pointer relative addressing"
21	default n
22	help
23	  Use global pointer relative addressing for small globals declared
24	  anywhere in the executable. It can benefit performance and reduce
25	  the code size.
26
27	  Note: To support this feature, RISC-V SoC needs to initialize
28	  global pointer at program start or earlier than any instruction
29	  using GP relative addressing.
30
31config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
32	bool "Do not use mret outside a trap handler context"
33	depends on MULTITHREADING
34	depends on !RISCV_PMP
35	help
36	  Use mret instruction only when in a trap handler.
37	  This is for RISC-V implementations that require every mret to be
38	  balanced with an ecall. This is not required by the RISC-V spec
39	  and most people should say n here to minimize context switching
40	  overhead.
41
42menu "RISCV Processor Options"
43
44config INCLUDE_RESET_VECTOR
45	bool "Include Reset vector"
46	help
47	  Include the reset vector stub, which initializes the stack and
48	  prepares for running C code.
49
50config RISCV_SOC_HAS_ISR_STACKING
51	bool
52	depends on !USERSPACE
53	help
54	  Enable low-level SOC-specific hardware stacking / unstacking
55	  operations during ISR. This hidden option needs to be selected by SoC
56	  if this feature is supported.
57
58	  Some SOCs implement a mechanism for which, on interrupt handling,
59	  part of the context is automatically saved by the hardware on the
60	  stack according to a custom ESF format. The same part of the context
61	  is automatically restored by hardware on mret.
62
63	  Enabling this option requires that the SoC provides a
64	  soc_isr_stacking.h header which defines the following:
65
66	  - SOC_ISR_SW_STACKING: macro guarded by _ASMLANGUAGE called by the
67	    IRQ wrapper assembly code on ISR entry to save in the ESF the
68	    remaining part of the context not pushed already on the stack by
69	    the hardware.
70
71	  - SOC_ISR_SW_UNSTACKING: macro guarded by _ASMLANGUAGE called by the
72	    IRQ wrapper assembly code on ISR exit to restore the part of the
73	    context from the ESF that won't be restored by hardware on mret.
74
75	  - SOC_ISR_STACKING_ESF_DECLARE: structure declaration for the ESF
76	    guarded by !_ASMLANGUAGE. The ESF should be defined to account for
77	    the hardware stacked registers in the proper order as they are
78	    saved on the stack by the hardware, and the registers saved by the
79	    software macros. The structure must be called '__esf'.
80
81config RISCV_SOC_HAS_CUSTOM_IRQ_LOCK_OPS
82	bool
83	help
84	  Hidden option to allow SoC to overwrite arch_irq_lock(),
85	  arch_irq_unlock() and arch_irq_unlocked() functions with
86	  platform-specific versions named z_soc_irq_lock(), z_soc_irq_unlock()
87	  and z_soc_irq_unlocked().
88
89	  Enable this hidden option and specialize the z_soc_* functions when
90	  the RISC-V SoC needs to do something different and more than reading and
91	  writing the mstatus register to lock and unlock the IRQs.
92
93config RISCV_SOC_HAS_CUSTOM_SYS_IO
94	bool
95	help
96	  Hidden option to allow SoC to overwrite sys_read*(), sys_write*() functions with
97	  platform-specific versions named z_soc_sys_read*() and z_soc_sys_write*().
98
99	  Enable this hidden option and specialize the z_soc_* functions when
100	  the RISC-V SoC needs to do something different and more than reading and
101	  writing the registers.
102
103config RISCV_SOC_CONTEXT_SAVE
104	bool "SOC-based context saving in IRQ handlers"
105	select RISCV_SOC_OFFSETS
106	help
107	  Enable low-level SOC-specific context management, for SOCs
108	  with extra state that must be saved when entering an
109	  interrupt/exception, and restored on exit. If unsure, leave
110	  this at the default value.
111
112	  Enabling this option requires that the SoC provide a
113	  soc_context.h header which defines the following macros:
114
115	  - SOC_ESF_MEMBERS: structure component declarations to
116	    allocate space for. The last such declaration should not
117	    end in a semicolon, for portability. The generic RISC-V
118	    architecture code will allocate space for these members in
119	    a "struct soc_esf" type (typedefed to soc_esf_t), which will
120	    be available if arch.h is included.
121
122	  - SOC_ESF_INIT: structure contents initializer for struct soc_esf
123	    state. The last initialized member should not end in a comma.
124
125	  The generic architecture IRQ wrapper will also call
126	  \_\_soc_save_context and \_\_soc_restore_context routines at
127	  ISR entry and exit, respectively. These should typically
128	  be implemented in assembly. If they were C functions, they
129	  would have these signatures:
130
131	  ``void __soc_save_context(soc_esf_t *state);``
132
133	  ``void __soc_restore_context(soc_esf_t *state);``
134
135	  The calls obey standard calling conventions; i.e., the state
136	  pointer address is in a0, and ra contains the return address.
137
138config RISCV_SOC_OFFSETS
139	bool "SOC-based offsets"
140	help
141	  Enabling this option requires that the SoC provide a soc_offsets.h
142	  header which defines the following macros:
143
144	  - GEN_SOC_OFFSET_SYMS(): a macro which expands to
145	    GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
146	    to ensure offset macros for SOC_ESF_MEMBERS are defined
147	    in offsets.h. The last one should not end in a semicolon.
148	    See gen_offset.h for more details.
149
150config RISCV_SOC_INTERRUPT_INIT
151	bool "SOC-based interrupt initialization"
152	help
153	  Enable SOC-based interrupt initialization
154	  (call soc_interrupt_init, within _IntLibInit when enabled)
155
156config RISCV_SOC_MCAUSE_EXCEPTION_MASK
157	hex
158	default 0x7FFFFFFFFFFFFFFF if 64BIT
159	default 0x7FFFFFFF
160	help
161	  Specify the bits to use for exception code in mcause register.
162
163config RISCV_GENERIC_TOOLCHAIN
164	bool "Compile using generic riscv32 toolchain"
165	default y
166	help
167	  Compile using generic riscv32 toolchain.
168	  Allow SOCs that have custom extended riscv ISA to still
169	  compile with generic riscv32 toolchain.
170
171config RISCV_HAS_CPU_IDLE
172	bool "Does SOC has CPU IDLE instruction"
173	help
174	  Does SOC has CPU IDLE instruction
175
176config GEN_ISR_TABLES
177	default y
178
179config GEN_IRQ_VECTOR_TABLE
180	default n
181
182config RISCV_RESERVED_IRQ_ISR_TABLES_OFFSET
183	int
184	default 0
185	depends on GEN_ISR_TABLES
186	help
187	  On some RISCV platform the first interrupt vectors are primarly
188	  intended for inter-hart interrupt signaling and so retained for that
189	  purpose and not available. When this option is set, all the IRQ
190	  vectors are shifted by this offset value when installed into the
191	  software ISR table and the IRQ vector table. CONFIG_NUM_IRQS must be
192	  properly sized to take into account this offset. This is a hidden
193	  option which needs to be set per architecture and left alone.
194
195config NUM_IRQS
196	int
197
198config RV_BOOT_HART
199	int "Starting HART ID"
200	default 0
201	help
202	  This option sets the starting HART ID for the SMP core.
203	  For RISC-V systems such as MPFS and FU540 this would be set to 1 to
204	  skip the E51 HART 0 as it is not usable in SMP configurations.
205
206config RISCV_PMP
207	bool "RISC-V PMP Support"
208	select THREAD_STACK_INFO
209	select CPU_HAS_MPU
210	select ARCH_HAS_USERSPACE
211	select ARCH_HAS_STACK_PROTECTION
212	select MPU
213	select SRAM_REGION_PERMISSIONS
214	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
215	select ARCH_MEM_DOMAIN_DATA if USERSPACE
216	select THREAD_LOCAL_STORAGE if USERSPACE
217	help
218	  MCU implements Physical Memory Protection.
219
220if RISCV_PMP
221
222config PMP_SLOTS
223	int "Number of PMP slots"
224	default 8
225	help
226	  This is the number of PMP entries implemented by the hardware.
227	  Typical values are 8 or 16.
228
229config PMP_NO_TOR
230	bool
231	help
232	  Set this if TOR (Top Of Range) mode is not supported.
233
234config PMP_NO_NA4
235	bool
236	help
237	  Set this if NA4 (Naturally Aligned 4-byte) mode is not supported.
238
239config PMP_NO_NAPOT
240	bool
241	help
242	  Set this if NAPOT (Naturally Aligned Power Of Two) is not supported.
243
244config PMP_POWER_OF_TWO_ALIGNMENT
245	bool "Enforce power-of-two alignment on PMP memory areas" if !PMP_NO_TOR
246	default y if TEST_USERSPACE
247	default y if (PMP_SLOTS = 8)
248	default y if PMP_NO_TOR
249	select MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT
250	select GEN_PRIV_STACKS
251	help
252	  This option reduces the PMP slot usage but increases
253	  memory consumption. Useful when enabling userspace mode with
254	  many memory domains and/or few PMP slots available.
255
256config PMP_GRANULARITY
257	int "The granularity of PMP address matching"
258	default 8 if (PMP_NO_TOR && PMP_NO_NA4)
259	default 4
260	help
261	  The granularity must be a power of 2 greater than or equal to 4
262	  (ie 4, 8, 16, ...), but if neither TOR mode nor NA4 mode is
263	  supported, the minimum granularity is 8.
264
265endif #RISCV_PMP
266
267config PMP_STACK_GUARD
268	def_bool y
269	depends on MULTITHREADING
270	depends on HW_STACK_PROTECTION
271
272config PMP_STACK_GUARD_MIN_SIZE
273	int "Stack Guard area size"
274	depends on PMP_STACK_GUARD
275	default 1024 if 64BIT
276	default 512
277	help
278	  The Hardware Stack Protection implements a guard area at the bottom
279	  of the stack using the PMP to catch stack overflows by marking that
280	  guard area not accessible.
281
282	  This is the size of the guard area. This should be large enough to
283	  catch any sudden jump in stack pointer decrement, plus some
284	  wiggle room to accommodate the eventual overflow exception
285	  stack usage.
286
287# Implement the null pointer detection using the Physical Memory Protection
288# (PMP) Unit.
289config NULL_POINTER_EXCEPTION_DETECTION_PMP
290	bool "Use PMP for null pointer exception detection"
291	depends on RISCV_PMP
292	help
293	  Null pointer dereference detection implemented
294	  using PMP functionality.
295
296if NULL_POINTER_EXCEPTION_DETECTION_PMP
297
298config NULL_POINTER_EXCEPTION_REGION_SIZE
299	hex "Inaccessible region to implement null pointer detection"
300	default 0x10
301	help
302	  Use a PMP slot to make region (starting at address 0x0) inaccessible for
303	  detecting null pointer dereferencing (raising a CPU access fault).
304	  Minimum is 4 bytes.
305
306endif # NULL_POINTER_EXCEPTION_DETECTION_PMP
307
308endmenu
309
310config MAIN_STACK_SIZE
311	default 4096 if 64BIT
312	default 2048 if PMP_STACK_GUARD
313
314config TEST_EXTRA_STACK_SIZE
315	default 1536
316
317config CMSIS_THREAD_MAX_STACK_SIZE
318	default 1024 if 64BIT
319
320config CMSIS_V2_THREAD_MAX_STACK_SIZE
321	default 1024 if 64BIT
322
323config ARCH_IRQ_VECTOR_TABLE_ALIGN
324	default 256
325
326config RISCV_TRAP_HANDLER_ALIGNMENT
327	int "Alignment of RISC-V trap handler in bytes"
328	default 4
329	help
330	  This value configures the alignment of RISC-V trap handling
331	  code. The requirement for a particular alignment arises from
332	  the format of MTVEC register which is RISC-V platform-specific.
333	  The minimum alignment is 4 bytes according to the Spec.
334
335config GEN_IRQ_VECTOR_TABLE
336	select RISCV_VECTORED_MODE if SOC_FAMILY_RISCV_PRIVILEGED
337
338config ARCH_HAS_SINGLE_THREAD_SUPPORT
339	default y if !SMP
340
341rsource "Kconfig.isa"
342rsource "Kconfig.core"
343
344endmenu
345