1# Copyright (c) 2016 Jean-Paul Etienne <fractalclone@gmail.com>
2# SPDX-License-Identifier: Apache-2.0
3
4menu "RISCV Options"
5	depends on RISCV
6
7config ARCH
8	string
9	default "riscv64" if 64BIT
10	default "riscv32"
11
12config COMPRESSED_ISA
13	bool
14	default y if 64BIT
15
16config FLOAT_HARD
17	bool "Enable hard-float calling convention"
18	default y
19	depends on FPU
20	help
21	  This option enables the hard-float calling convention.
22
23config RISCV_GP
24	bool "Enable RISC-V global pointer relative addressing"
25	default n
26	help
27	  Use global pointer relative addressing for small globals declared
28	  anywhere in the executable. It can benefit performance and reduce
29	  the code size.
30
31	  Note: To support this feature, RISC-V SoC needs to initialize
32	  global pointer at program start or earlier than any instruction
33	  using GP relative addressing.
34
35menu "RISCV Processor Options"
36
37config CORE_E31
38	bool "Use E31 core"
39	select RISCV_PMP
40	select ARCH_HAS_USERSPACE
41	select ARCH_HAS_STACK_PROTECTION if PMP_STACK_GUARD
42	default n
43	help
44	  This option signifies the use of a core of the E31 family.
45
46config INCLUDE_RESET_VECTOR
47	bool "Include Reset vector"
48	help
49	  Include the reset vector stub, which initializes the stack and
50	  prepares for running C code.
51
52config RISCV_SOC_CONTEXT_SAVE
53	bool "Enable SOC-based context saving in IRQ handlers"
54	select RISCV_SOC_OFFSETS
55	help
56	  Enable low-level SOC-specific context management, for SOCs
57	  with extra state that must be saved when entering an
58	  interrupt/exception, and restored on exit. If unsure, leave
59	  this at the default value.
60
61	  Enabling this option requires that the SoC provide a
62	  soc_context.h header which defines the following macros:
63
64	  - SOC_ESF_MEMBERS: structure component declarations to
65	    allocate space for. The last such declaration should not
66	    end in a semicolon, for portability. The generic RISC-V
67	    architecture code will allocate space for these members in
68	    a "struct soc_esf" type (typedefed to soc_esf_t), which will
69	    be available if arch.h is included.
70
71	  - SOC_ESF_INIT: structure contents initializer for struct soc_esf
72	    state. The last initialized member should not end in a comma.
73
74	  The generic architecture IRQ wrapper will also call
75	  \_\_soc_save_context and \_\_soc_restore_context routines at
76	  ISR entry and exit, respectively. These should typically
77	  be implemented in assembly. If they were C functions, they
78	  would have these signatures:
79
80	  ``void __soc_save_context(soc_esf_t *state);``
81
82	  ``void __soc_restore_context(soc_esf_t *state);``
83
84	  The calls obey standard calling conventions; i.e., the state
85	  pointer address is in a0, and ra contains the return address.
86
87config RISCV_SOC_OFFSETS
88	bool "Enable SOC-based offsets"
89	help
90	  Enabling this option requires that the SoC provide a soc_offsets.h
91	  header which defines the following macros:
92
93	  - GEN_SOC_OFFSET_SYMS(): a macro which expands to
94	    GEN_OFFSET_SYM(soc_esf_t, soc_specific_member) calls
95	    to ensure offset macros for SOC_ESF_MEMBERS are defined
96	    in offsets.h. The last one should not end in a semicolon.
97	    See gen_offset.h for more details.
98
99config RISCV_SOC_INTERRUPT_INIT
100	bool "Enable SOC-based interrupt initialization"
101	help
102	  Enable SOC-based interrupt initialization
103	  (call soc_interrupt_init, within _IntLibInit when enabled)
104
105config RISCV_GENERIC_TOOLCHAIN
106	bool "Compile using generic riscv32 toolchain"
107	default y
108	help
109	  Compile using generic riscv32 toolchain.
110	  Allow SOCs that have custom extended riscv ISA to still
111	  compile with generic riscv32 toolchain.
112
113config RISCV_HAS_CPU_IDLE
114	bool "Does SOC has CPU IDLE instruction"
115	help
116	  Does SOC has CPU IDLE instruction
117
118config GEN_ISR_TABLES
119	default y
120
121config GEN_IRQ_VECTOR_TABLE
122	default n
123
124config NUM_IRQS
125	int
126
127menuconfig RISCV_PMP
128	bool "RISC-V PMP Support"
129	default n
130	select THREAD_STACK_INFO
131	select CPU_HAS_MPU
132	select MPU
133	select SRAM_REGION_PERMISSIONS
134	select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE
135	select PMP_POWER_OF_TWO_ALIGNMENT if USERSPACE
136	help
137	  MCU implements Physical Memory Protection.
138	  Memory protection against read-only area writing
139	  is natively supported on real HW.
140
141if RISCV_PMP
142source "arch/riscv/core/pmp/Kconfig"
143endif #RISCV_PMP
144
145endmenu
146
147config MAIN_STACK_SIZE
148	default 4096 if 64BIT
149
150config TEST_EXTRA_STACKSIZE
151	default 1024
152
153config CMSIS_THREAD_MAX_STACK_SIZE
154	default 1024 if 64BIT
155
156config CMSIS_V2_THREAD_MAX_STACK_SIZE
157	default 1024 if 64BIT
158
159endmenu
160