1# General architecture configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2015 Intel Corporation 5# Copyright (c) 2016 Cadence Design Systems, Inc. 6# SPDX-License-Identifier: Apache-2.0 7 8# Include these first so that any properties (e.g. defaults) below can be 9# overridden (by defining symbols in multiple locations) 10 11# Note: $ARCH might be a glob pattern 12source "$(ARCH_DIR)/$(ARCH)/Kconfig" 13 14# Architecture symbols 15# 16# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that, 17# by SOC_*. 18 19config ARC 20 bool 21 select ARCH_IS_SET 22 select HAS_DTS 23 imply XIP 24 select ARCH_HAS_THREAD_LOCAL_STORAGE 25 help 26 ARC architecture 27 28config ARM 29 bool 30 select ARCH_IS_SET 31 select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M 32 select HAS_DTS 33 # FIXME: current state of the code for all ARM requires this, but 34 # is really only necessary for Cortex-M with ARM MPU! 35 select GEN_PRIV_STACKS 36 select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A 37 select BARRIER_OPERATIONS_ARCH 38 help 39 ARM architecture 40 41config ARM64 42 bool 43 select ARCH_IS_SET 44 select 64BIT 45 select HAS_DTS 46 select HAS_ARM_SMCCC 47 select ARCH_HAS_THREAD_LOCAL_STORAGE 48 select USE_SWITCH 49 select USE_SWITCH_SUPPORTED 50 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 51 select BARRIER_OPERATIONS_ARCH 52 help 53 ARM64 (AArch64) architecture 54 55config MIPS 56 bool 57 select ARCH_IS_SET 58 select ATOMIC_OPERATIONS_C 59 select HAS_DTS 60 help 61 MIPS architecture 62 63config SPARC 64 bool 65 select ARCH_IS_SET 66 select HAS_DTS 67 select USE_SWITCH 68 select USE_SWITCH_SUPPORTED 69 select BIG_ENDIAN 70 select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA 71 select ATOMIC_OPERATIONS_C if !SPARC_CASA 72 select ARCH_HAS_THREAD_LOCAL_STORAGE 73 select ARCH_HAS_EXTRA_EXCEPTION_INFO 74 help 75 SPARC architecture 76 77config X86 78 bool 79 select ARCH_IS_SET 80 select ATOMIC_OPERATIONS_BUILTIN 81 select HAS_DTS 82 select ARCH_SUPPORTS_COREDUMP 83 select CPU_HAS_MMU 84 select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE 85 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 86 select ARCH_HAS_GDBSTUB if !X86_64 87 select ARCH_HAS_TIMING_FUNCTIONS 88 select ARCH_HAS_THREAD_LOCAL_STORAGE 89 select ARCH_HAS_DEMAND_PAGING 90 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 91 select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ 92 && !BOARD_HAS_TIMING_FUNCTIONS \ 93 && !SOC_HAS_TIMING_FUNCTIONS 94 help 95 x86 architecture 96 97config NIOS2 98 bool 99 select ARCH_IS_SET 100 select ATOMIC_OPERATIONS_C 101 select HAS_DTS 102 imply XIP 103 select ARCH_HAS_TIMING_FUNCTIONS 104 help 105 Nios II Gen 2 architecture 106 107config RISCV 108 bool 109 select ARCH_IS_SET 110 select HAS_DTS 111 select ARCH_SUPPORTS_COREDUMP 112 select ARCH_HAS_CODE_DATA_RELOCATION 113 select ARCH_HAS_THREAD_LOCAL_STORAGE 114 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 115 select USE_SWITCH_SUPPORTED 116 select USE_SWITCH 117 select SCHED_IPI_SUPPORTED if SMP 118 select BARRIER_OPERATIONS_BUILTIN 119 imply XIP 120 help 121 RISCV architecture 122 123config XTENSA 124 bool 125 select ARCH_IS_SET 126 select HAS_DTS 127 select USE_SWITCH 128 select USE_SWITCH_SUPPORTED 129 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 130 select ARCH_HAS_CODE_DATA_RELOCATION 131 select ARCH_HAS_TIMING_FUNCTIONS 132 imply ATOMIC_OPERATIONS_ARCH 133 help 134 Xtensa architecture 135 136config ARCH_POSIX 137 bool 138 select ARCH_IS_SET 139 select HAS_DTS 140 select ATOMIC_OPERATIONS_BUILTIN 141 select ARCH_HAS_CUSTOM_SWAP_TO_MAIN 142 select ARCH_HAS_CUSTOM_BUSY_WAIT 143 select ARCH_HAS_THREAD_ABORT 144 select NATIVE_APPLICATION 145 select HAS_COVERAGE_SUPPORT 146 select BARRIER_OPERATIONS_BUILTIN 147 help 148 POSIX (native) architecture 149 150config ARCH_IS_SET 151 bool 152 help 153 Helper symbol to detect SoCs forgetting to select one of the arch 154 symbols above. See the top-level CMakeLists.txt. 155 156menu "General Architecture Options" 157 158source "arch/common/Kconfig" 159 160module = ARCH 161module-str = arch 162source "subsys/logging/Kconfig.template.log_config" 163 164config BIG_ENDIAN 165 bool 166 help 167 This option tells the build system that the target system is big-endian. 168 Little-endian architecture is the default and should leave this option 169 unselected. This option is selected by arch/$ARCH/Kconfig, 170 soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid 171 modifying it. The option is used to select linker script OUTPUT_FORMAT 172 and command line option for gen_isr_tables.py. 173 174config LITTLE_ENDIAN 175 # Hidden Kconfig option representing the default little-endian architecture 176 # This is just the opposite of BIG_ENDIAN and is used for non-negative 177 # conditional compilation 178 bool 179 depends on !BIG_ENDIAN 180 default y 181 182config 64BIT 183 bool 184 help 185 This option tells the build system that the target system is 186 using a 64-bit address space, meaning that pointer and long types 187 are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, 188 soc/**/Kconfig, or boards/**/Kconfig and the user should generally 189 avoid modifying it. 190 191# Workaround for not being able to have commas in macro arguments 192DT_CHOSEN_Z_SRAM := zephyr,sram 193 194config SRAM_SIZE 195 int "SRAM Size in kB" 196 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) 197 help 198 The SRAM size in kB. The default value comes from /chosen/zephyr,sram in 199 devicetree. The user should generally avoid changing it via menuconfig or 200 in configuration files. 201 202config SRAM_BASE_ADDRESS 203 hex "SRAM Base Address" 204 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 205 help 206 The SRAM base address. The default value comes from from 207 /chosen/zephyr,sram in devicetree. The user should generally avoid 208 changing it via menuconfig or in configuration files. 209 210if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV 211 212# Workaround for not being able to have commas in macro arguments 213DT_CHOSEN_Z_FLASH := zephyr,flash 214 215config FLASH_SIZE 216 int "Flash Size in kB" 217 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM 218 help 219 This option specifies the size of the flash in kB. It is normally set by 220 the board's defconfig file and the user should generally avoid modifying 221 it via the menu configuration. 222 223config FLASH_BASE_ADDRESS 224 hex "Flash Base Address" 225 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM 226 help 227 This option specifies the base address of the flash on the board. It is 228 normally set by the board's defconfig file and the user should generally 229 avoid modifying it via the menu configuration. 230 231endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV 232 233if ARCH_HAS_TRUSTED_EXECUTION 234 235config TRUSTED_EXECUTION_SECURE 236 bool "Trusted Execution: Secure firmware image" 237 help 238 Select this option to enable building a Secure firmware 239 image for a platform that supports Trusted Execution. A 240 Secure firmware image will execute in Secure state. It may 241 allow the CPU to execute in Non-Secure (Normal) state. 242 Therefore, a Secure firmware image shall be able to 243 configure security attributions of CPU resources (memory 244 areas, peripherals, interrupts, etc.) as well as to handle 245 faults, related to security violations. It may optionally 246 allow certain functions to be called from the Non-Secure 247 (Normal) domain. 248 249config TRUSTED_EXECUTION_NONSECURE 250 depends on !TRUSTED_EXECUTION_SECURE 251 bool "Trusted Execution: Non-Secure firmware image" 252 help 253 Select this option to enable building a Non-Secure 254 firmware image for a platform that supports Trusted 255 Execution. A Non-Secure firmware image will execute 256 in Non-Secure (Normal) state. Therefore, it shall not 257 access CPU resources (memory areas, peripherals, 258 interrupts etc.) belonging to the Secure domain. 259 260endif # ARCH_HAS_TRUSTED_EXECUTION 261 262config HW_STACK_PROTECTION 263 bool "Hardware Stack Protection" 264 depends on ARCH_HAS_STACK_PROTECTION 265 help 266 Select this option to enable hardware-based platform features to 267 catch stack overflows when the system is running in privileged 268 mode. If CONFIG_USERSPACE is not enabled, the system is always 269 running in privileged mode. 270 271 Note that this does not necessarily prevent corruption and assertions 272 about the overall system state when a fault is triggered cannot be 273 made. 274 275config USERSPACE 276 bool "User mode threads" 277 depends on ARCH_HAS_USERSPACE 278 depends on RUNTIME_ERROR_CHECKS 279 depends on SRAM_REGION_PERMISSIONS 280 select THREAD_STACK_INFO 281 select LINKER_USE_NO_RELAX 282 help 283 When enabled, threads may be created or dropped down to user mode, 284 which has significantly restricted permissions and must interact 285 with the kernel via system calls. See Zephyr documentation for more 286 details about this feature. 287 288 If a user thread overflows its stack, this will be caught and the 289 kernel itself will be shielded from harm. Enabling this option 290 may or may not catch stack overflows when the system is in 291 privileged mode or handling a system call; to ensure these are always 292 caught, enable CONFIG_HW_STACK_PROTECTION. 293 294config PRIVILEGED_STACK_SIZE 295 int "Size of privileged stack" 296 default 2048 if EMUL 297 default 1024 298 depends on ARCH_HAS_USERSPACE 299 help 300 This option sets the privileged stack region size that will be used 301 in addition to the user mode thread stack. During normal execution, 302 this region will be inaccessible from user mode. During system calls, 303 this region will be utilized by the system call. This value must be 304 a multiple of the minimum stack alignment. 305 306config KOBJECT_TEXT_AREA 307 int "Size of kobject text area" 308 default 512 if COVERAGE_GCOV 309 default 512 if NO_OPTIMIZATIONS 310 default 512 if STACK_CANARIES && RISCV 311 default 256 312 depends on ARCH_HAS_USERSPACE 313 help 314 Size of kernel object text area. Used in linker script. 315 316config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 317 int "Reserve extra kobject data area (in percentage)" 318 default 100 319 depends on ARCH_HAS_USERSPACE 320 help 321 Multiplication factor used to calculate the size of placeholder to 322 reserve space for kobject metadata hash table. The hash table is 323 generated via gperf is highly dependent on the absolute addresses of 324 kobjects which might change between prebuilts. To reserve enough 325 space for the hash table during final linking passes to keep 326 kobjects in same place, the size of reserved space is calculated 327 from the first prebuilt plus additional space calculated with 328 this percentage (of the kobject data area in first prebuilt). 329 330config KOBJECT_RODATA_AREA_EXTRA_BYTES 331 int "Reserve extra bytes for kobject rodata area" 332 default 16 333 depends on ARCH_HAS_USERSPACE 334 help 335 Reserve a few more bytes for the RODATA region for kobject metadata. 336 This is to account for the uncertainty of tables generated by gperf. 337 338config GEN_PRIV_STACKS 339 bool 340 help 341 Selected if the architecture requires that privilege elevation stacks 342 be allocated in a separate memory area. This is typical of arches 343 whose MPUs require regions to be power-of-two aligned/sized. 344 345 FIXME: This should be removed and replaced with checks against 346 CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC 347 changes will be necessary for this. 348 349config STACK_GROWS_UP 350 bool "Stack grows towards higher memory addresses" 351 help 352 Select this option if the architecture has upward growing thread 353 stacks. This is not common. 354 355config NO_UNUSED_STACK_INSPECTION 356 bool 357 help 358 Selected if the architecture will generate a fault if unused stack 359 memory is examined, which is the region between the current stack 360 pointer and the deepest available address in the current stack 361 region. 362 363config MAX_THREAD_BYTES 364 int "Bytes to use when tracking object thread permissions" 365 default 2 366 depends on USERSPACE 367 help 368 Every kernel object will have an associated bitfield to store 369 thread permissions for that object. This controls the size of the 370 bitfield (in bytes) and imposes a limit on how many threads can 371 be created in the system. 372 373config DYNAMIC_OBJECTS 374 bool "Allow kernel objects to be allocated at runtime" 375 depends on USERSPACE 376 help 377 Enabling this option allows for kernel objects to be requested from 378 the calling thread's resource pool, at a slight cost in performance 379 due to the supplemental run-time tables required to validate such 380 objects. 381 382 Objects allocated in this way can be freed with a supervisor-only 383 API call, or when the number of references to that object drops to 384 zero. 385 386config NOCACHE_MEMORY 387 bool "Support for uncached memory" 388 depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT 389 help 390 Add a "nocache" read-write memory section that is configured to 391 not be cached. This memory section can be used to perform DMA 392 transfers when cache coherence issues are not optimal or can not 393 be solved using cache maintenance operations. 394 395menu "Interrupt Configuration" 396 397config DYNAMIC_INTERRUPTS 398 bool "Installation of IRQs at runtime" 399 help 400 Enable installation of interrupts at runtime, which will move some 401 interrupt-related data structures to RAM instead of ROM, and 402 on some architectures increase code size. 403 404config GEN_ISR_TABLES 405 bool "Use generated IRQ tables" 406 help 407 This option controls whether a platform uses the gen_isr_tables 408 script to generate its interrupt tables. This mechanism will create 409 an appropriate hardware vector table and/or software IRQ table. 410 411config GEN_IRQ_VECTOR_TABLE 412 bool "Generate an interrupt vector table" 413 default y 414 depends on GEN_ISR_TABLES 415 help 416 This option controls whether a platform using gen_isr_tables 417 needs an interrupt vector table created. Only disable this if the 418 platform does not use a vector table at all, or requires the vector 419 table to be in a format that is not an array of function pointers 420 indexed by IRQ line. In the latter case, the vector table must be 421 supplied by the application or architecture code. 422 423config ARCH_IRQ_VECTOR_TABLE_ALIGN 424 int "Alignment size of the interrupt vector table" 425 default 4 426 depends on GEN_IRQ_VECTOR_TABLE 427 help 428 This option controls alignment size of generated 429 _irq_vector_table. Some architecture needs an IRQ vector table 430 to be aligned to architecture specific size. The default 431 size is 0 for no alignment. 432 433choice IRQ_VECTOR_TABLE_TYPE 434 prompt "IRQ vector table type" 435 depends on GEN_IRQ_VECTOR_TABLE 436 default IRQ_VECTOR_TABLE_JUMP_BY_CODE if (RISCV && !RISCV_HAS_CLIC) 437 default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 438 439config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 440 bool "Jump by address" 441 help 442 The IRQ vector table contains the address of the interrupt handler. 443 444config IRQ_VECTOR_TABLE_JUMP_BY_CODE 445 bool "Jump by code" 446 help 447 The IRQ vector table contains the opcode of a jump instruction to the 448 interrupt handler address. 449 450endchoice 451 452config GEN_SW_ISR_TABLE 453 bool "Generate a software ISR table" 454 default y 455 depends on GEN_ISR_TABLES 456 help 457 This option controls whether a platform using gen_isr_tables 458 needs a software ISR table table created. This is an array of struct 459 _isr_table_entry containing the interrupt service routine and supplied 460 parameter. 461 462config ARCH_SW_ISR_TABLE_ALIGN 463 int "Alignment size of a software ISR table" 464 default 4 465 depends on GEN_SW_ISR_TABLE 466 help 467 This option controls alignment size of generated 468 _sw_isr_table. Some architecture needs a software ISR table 469 to be aligned to architecture specific size. The default 470 size is 0 for no alignment. 471 472config GEN_IRQ_START_VECTOR 473 int 474 default 0 475 depends on GEN_ISR_TABLES 476 help 477 On some architectures, part of the vector table may be reserved for 478 system exceptions and is declared separately from the tables 479 created by gen_isr_tables.py. When creating these tables, this value 480 will be subtracted from CONFIG_NUM_IRQS to properly size them. 481 This is a hidden option which needs to be set per architecture and 482 left alone. 483 484config IRQ_OFFLOAD 485 bool "IRQ offload" 486 depends on TEST 487 help 488 Enable irq_offload() API which allows functions to be synchronously 489 run in interrupt context. Only useful for test cases that need 490 to validate the correctness of kernel objects in IRQ context. 491 492config IRQ_OFFLOAD_NESTED 493 bool "irq_offload() supports nested IRQs" 494 depends on IRQ_OFFLOAD 495 help 496 When set by the arch layer, indicates that irq_offload() may 497 legally be called in interrupt context to cause a 498 synchronous nested interrupt on the current CPU. Not all 499 hardware is capable. 500 501config EXTRA_EXCEPTION_INFO 502 bool "Collect extra exception info" 503 depends on ARCH_HAS_EXTRA_EXCEPTION_INFO 504 help 505 This option enables the collection of extra information, such as 506 register state, when a fault occurs. This information can be useful 507 to collect for post-mortem analysis and debug of issues. 508 509config SIMPLIFIED_EXCEPTION_CODES 510 bool "Convert arch specific exception codes to K_ERR_CPU_EXCEPTION" 511 default y if ZTEST 512 help 513 The same piece of faulty code (NULL dereference, etc) can result in 514 a multitude of potential exception codes at the CPU level, depending 515 upon whether addresses exist, an MPU is configured, the particular 516 implementation of the CPU or any number of other reasons. Enabling 517 this option collapses all the architecture specific exception codes 518 down to the generic K_ERR_CPU_EXCEPTION, which makes testing code 519 much more portable. 520 521endmenu # Interrupt configuration 522 523config INIT_ARCH_HW_AT_BOOT 524 bool "Initialize internal architecture state at boot" 525 depends on ARCH_SUPPORTS_ARCH_HW_INIT 526 help 527 This option instructs Zephyr to force the initialization 528 of the internal architectural state (for example ARCH-level 529 HW registers and system control blocks) during boot to 530 the reset values as specified by the corresponding 531 architecture manual. The option is useful when the Zephyr 532 firmware image is chain-loaded, for example, by a debugger 533 or a bootloader, and we need to guarantee that the internal 534 states of the architecture core blocks are restored to the 535 reset values (as specified by the architecture). 536 537 Note: the functionality is architecture-specific. For the 538 implementation details refer to each architecture where 539 this feature is supported. 540 541endmenu 542 543# 544# Architecture Capabilities 545# 546 547config ARCH_HAS_SINGLE_THREAD_SUPPORT 548 bool 549 550config ARCH_HAS_TIMING_FUNCTIONS 551 bool 552 553config ARCH_HAS_TRUSTED_EXECUTION 554 bool 555 556config ARCH_HAS_STACK_PROTECTION 557 bool 558 559config ARCH_HAS_USERSPACE 560 bool 561 562config ARCH_HAS_EXECUTABLE_PAGE_BIT 563 bool 564 565config ARCH_HAS_NOCACHE_MEMORY_SUPPORT 566 bool 567 568config ARCH_HAS_RAMFUNC_SUPPORT 569 bool 570 571config ARCH_HAS_NESTED_EXCEPTION_DETECTION 572 bool 573 574config ARCH_SUPPORTS_COREDUMP 575 bool 576 577config ARCH_SUPPORTS_ARCH_HW_INIT 578 bool 579 580config ARCH_HAS_EXTRA_EXCEPTION_INFO 581 bool 582 583config ARCH_HAS_GDBSTUB 584 bool 585 586config ARCH_HAS_COHERENCE 587 bool 588 help 589 When selected, the architecture supports the 590 arch_mem_coherent() API and can link into incoherent/cached 591 memory using the ".cached" linker section. 592 593config ARCH_HAS_THREAD_LOCAL_STORAGE 594 bool 595 596config ARCH_HAS_SUSPEND_TO_RAM 597 bool 598 help 599 When selected, the architecture supports suspend-to-RAM (S2RAM). 600 601# 602# Other architecture related options 603# 604 605config ARCH_HAS_THREAD_ABORT 606 bool 607 608config ARCH_HAS_CODE_DATA_RELOCATION 609 bool 610 help 611 When selected, the architecture/SoC implements support for 612 CODE_DATA_RELOCATION in its linker scripts. 613 614# 615# Hidden CPU family configs 616# 617 618config CPU_HAS_TEE 619 bool 620 help 621 This option is enabled when the CPU has support for Trusted 622 Execution Environment (e.g. when it has a security attribution 623 unit). 624 625config CPU_HAS_DCLS 626 bool 627 help 628 This option is enabled when the processor hardware has support for 629 Dual-redundant Core Lock-step (DCLS) topology. 630 631config CPU_HAS_FPU 632 bool 633 help 634 This option is enabled when the CPU has hardware floating point 635 unit. 636 637config CPU_HAS_FPU_DOUBLE_PRECISION 638 bool 639 select CPU_HAS_FPU 640 help 641 When enabled, this indicates that the CPU has a double floating point 642 precision unit. 643 644config CPU_HAS_MPU 645 bool 646 help 647 This option is enabled when the CPU has a Memory Protection Unit (MPU). 648 649config CPU_HAS_MMU 650 bool 651 help 652 This hidden option is selected when the CPU has a Memory Management Unit 653 (MMU). 654 655config ARCH_HAS_DEMAND_PAGING 656 bool 657 help 658 This hidden configuration should be selected by the architecture if 659 demand paging is supported. 660 661config ARCH_HAS_RESERVED_PAGE_FRAMES 662 bool 663 help 664 This hidden configuration should be selected by the architecture if 665 certain RAM page frames need to be marked as reserved and never used for 666 memory mappings. The architecture will need to implement 667 arch_reserved_pages_update(). 668 669config CPU_HAS_DCACHE 670 bool 671 help 672 This hidden configuration should be selected when the CPU has a d-cache. 673 674config CPU_HAS_ICACHE 675 bool 676 help 677 This hidden configuration should be selected when the CPU has an i-cache. 678 679config ARCH_MAPS_ALL_RAM 680 bool 681 help 682 This hidden option is selected by the architecture to inform the kernel 683 that all RAM is mapped at boot, and not just the bounds of the Zephyr image. 684 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL 685 pointer dereferences. With this enabled, the kernel will not assume that 686 virtual memory addresses past the kernel image are available for mappings, 687 but instead takes into account an entire RAM mapping instead. 688 689 This is typically set by architectures which need direct access to all memory. 690 It is the architecture's responsibility to mark reserved memory regions 691 as such in arch_reserved_pages_update(). 692 693 Although the kernel will not disturb this RAM mapping by re-mapping the associated 694 virtual addresses elsewhere, this is limited to only management of the 695 virtual address space. The kernel's page frame ontology will not consider 696 this mapping at all; non-kernel pages will be considered free (unless marked 697 as reserved) and Z_PAGE_FRAME_MAPPED will not be set. 698 699config DCLS 700 bool "Processor is configured in DCLS mode" 701 depends on CPU_HAS_DCLS 702 default y 703 help 704 This option is enabled when the processor hardware is configured in 705 Dual-redundant Core Lock-step (DCLS) topology. For the processor that 706 supports DCLS, but is configured in split-lock mode (by default or 707 changed at flash time), this option should be disabled. 708 709menuconfig MPU 710 bool "MPU features" 711 depends on CPU_HAS_MPU 712 help 713 This option, when enabled, indicates to the core kernel that an MPU 714 is enabled. 715 716if MPU 717module = MPU 718module-str = mpu 719source "subsys/logging/Kconfig.template.log_config" 720 721config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT 722 bool 723 help 724 This option is enabled when the MPU requires a power of two alignment 725 and size for MPU regions. 726 727config MPU_REQUIRES_NON_OVERLAPPING_REGIONS 728 bool 729 help 730 This option is enabled when the MPU requires the active (i.e. enabled) 731 MPU regions to be non-overlapping with each other. 732 733config MPU_GAP_FILLING 734 bool "Force MPU to be filling in background memory regions" 735 depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS 736 default y if !USERSPACE 737 help 738 This Kconfig option instructs the MPU driver to enforce 739 a full kernel SRAM partitioning, when it programs the 740 dynamic MPU regions (user thread stack, PRIV stack guard 741 and application memory domains) during context-switch. We 742 allow this to be a configurable option, in order to be able 743 to switch the option off and have an increased number of MPU 744 regions available for application memory domain programming. 745 746 Notes: 747 An increased number of MPU regions should only be required, 748 when building with USERSPACE support. As a result, when we 749 build without USERSPACE support, gap filling should always 750 be required. 751 752 When the option is switched off, access to memory areas not 753 covered by explicit MPU regions is restricted to privileged 754 code on an ARCH-specific basis. Refer to ARCH-specific 755 documentation for more information on how this option is 756 used. 757 758endif # MPU 759 760config SRAM_REGION_PERMISSIONS 761 bool "Assign appropriate permissions to kernel areas in SRAM" 762 depends on MMU || MPU 763 default y 764 help 765 This option indicates that memory protection hardware 766 is present, enabled, and regions have been configured at boot for memory 767 ranges within the kernel image. 768 769 If this option is turned on, certain areas of the kernel image will 770 have the following access policies applied for all threads, including 771 supervisor threads: 772 773 1) All program text will be have read-only, execute memory permission 774 2) All read-only data will have read-only permission, and execution 775 disabled if the hardware supports it. 776 3) All other RAM addresses will have read-write permission, and 777 execution disabled if the hardware supports it. 778 779 Options such as USERSPACE or HW_STACK_PROTECTION may additionally 780 impose additional policies on the memory map, which may be global 781 or local to the current running thread. 782 783 This option may consume additional memory to satisfy memory protection 784 hardware alignment constraints. 785 786 If this option is disabled, the entire kernel will have default memory 787 access permissions set, typically read/write/execute. It may be desirable 788 to turn this off on MMU systems which are using the MMU for demand 789 paging, do not need memory protection, and would rather not use up 790 RAM for the alignment between regions. 791 792config CODE_DATA_RELOCATION 793 bool "Support code/data section relocation" 794 depends on ARCH_HAS_CODE_DATA_RELOCATION 795 help 796 Enable support for relocating .text, data and .bss sections from specified 797 files and placing them in a chosen memory region. Files to relocate and 798 the target regions should be specified in CMakeLists.txt using 799 zephyr_code_relocate(). 800 801menu "Floating Point Options" 802 803config FPU 804 bool "Floating point unit (FPU)" 805 depends on CPU_HAS_FPU 806 help 807 This option enables the hardware Floating Point Unit (FPU), in order to 808 support using the floating point registers and instructions. 809 810 When this option is enabled, by default, threads may use the floating 811 point registers only in an exclusive manner, and this usually means that 812 only one thread may perform floating point operations. 813 814 If it is necessary for multiple threads to perform concurrent floating 815 point operations, the "FPU register sharing" option must be enabled to 816 preserve the floating point registers across context switches. 817 818 Note that this option cannot be selected for the platforms that do not 819 include a hardware floating point unit; the floating point support for 820 those platforms is dependent on the availability of the toolchain- 821 provided software floating point library. 822 823config FPU_SHARING 824 bool "FPU register sharing" 825 depends on FPU && MULTITHREADING 826 help 827 This option enables preservation of the hardware floating point registers 828 across context switches to allow multiple threads to perform concurrent 829 floating point operations. 830 831 Note that some compiler configurations may activate a floating point 832 context by generating FP instructions for any thread, and that 833 context must be preserved when switching such threads in and out. 834 The developers can still disable the FP sharing mode in their 835 application projects, and switch to Unshared FP registers mode, 836 if it is guaranteed that the image code does not generate FP 837 instructions outside the single thread context that is allowed 838 to do so. 839 840endmenu 841 842menu "Cache Options" 843 844config DCACHE 845 bool "Data cache (d-cache) support" 846 depends on CPU_HAS_DCACHE 847 default y 848 help 849 This option enables the support for the data cache (d-cache). 850 851config ICACHE 852 bool "Instruction cache (i-cache) support" 853 depends on CPU_HAS_ICACHE 854 default y 855 help 856 This option enables the support for the instruction cache (i-cache). 857 858config CACHE_MANAGEMENT 859 bool "Cache management features" 860 depends on DCACHE || ICACHE 861 help 862 This option enables the cache management functions backed by arch or 863 driver code. 864 865config DCACHE_LINE_SIZE_DETECT 866 bool "Detect d-cache line size at runtime" 867 depends on CACHE_MANAGEMENT && DCACHE 868 help 869 This option enables querying some architecture-specific hardware for 870 finding the d-cache line size at the expense of taking more memory and 871 code and a slightly increased boot time. 872 873 If the CPU's d-cache line size is known in advance, disable this option and 874 manually enter the value for DCACHE_LINE_SIZE or set it in the DT 875 using the 'd-cache-line-size' property. 876 877config DCACHE_LINE_SIZE 878 int "d-cache line size" 879 depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT 880 default 0 881 help 882 Size in bytes of a CPU d-cache line. If this is set to 0 the value is 883 obtained from the 'd-cache-line-size' DT property instead if present. 884 885 886 Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. 887 888config ICACHE_LINE_SIZE_DETECT 889 bool "Detect i-cache line size at runtime" 890 depends on CACHE_MANAGEMENT && ICACHE 891 help 892 This option enables querying some architecture-specific hardware for 893 finding the i-cache line size at the expense of taking more memory and 894 code and a slightly increased boot time. 895 896 If the CPU's i-cache line size is known in advance, disable this option and 897 manually enter the value for ICACHE_LINE_SIZE or set it in the DT 898 using the 'i-cache-line-size' property. 899 900config ICACHE_LINE_SIZE 901 int "i-cache line size" 902 depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT 903 default 0 904 help 905 Size in bytes of a CPU i-cache line. If this is set to 0 the value is 906 obtained from the 'i-cache-line-size' DT property instead if present. 907 908 Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. 909 910choice CACHE_TYPE 911 prompt "Cache type" 912 depends on CACHE_MANAGEMENT 913 default ARCH_CACHE 914 915config ARCH_CACHE 916 bool "Integrated cache controller" 917 help 918 Integrated on-core cache controller 919 920config EXTERNAL_CACHE 921 bool "External cache controller" 922 help 923 External cache controller 924 925endchoice 926 927endmenu 928 929config ARCH 930 string 931 help 932 System architecture string. 933 934config SOC 935 string 936 help 937 SoC name which can be found under soc/<arch>/<soc name>. 938 This option holds the directory name used by the build system to locate 939 the correct linker and header files for the SoC. 940 941config SOC_SERIES 942 string 943 help 944 SoC series name which can be found under soc/<arch>/<family>/<series>. 945 This option holds the directory name used by the build system to locate 946 the correct linker and header files. 947 948config SOC_FAMILY 949 string 950 help 951 SoC family name which can be found under soc/<arch>/<family>. 952 This option holds the directory name used by the build system to locate 953 the correct linker and header files. 954 955config TOOLCHAIN_HAS_BUILTIN_FFS 956 bool 957 default y if !(64BIT && RISCV) 958 help 959 Hidden option to signal that toolchain has __builtin_ffs*(). 960
