1# General architecture configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# Copyright (c) 2015 Intel Corporation 5# Copyright (c) 2016 Cadence Design Systems, Inc. 6# SPDX-License-Identifier: Apache-2.0 7 8# Include these first so that any properties (e.g. defaults) below can be 9# overridden (by defining symbols in multiple locations) 10 11# Note: $ARCH might be a glob pattern 12source "$(ARCH_DIR)/$(ARCH)/Kconfig" 13 14# Architecture symbols 15# 16# Should be 'select'ed by low-level symbols like SOC_SERIES_* or, lacking that, 17# by SOC_*. 18 19config ARC 20 bool 21 select ARCH_IS_SET 22 select HAS_DTS 23 imply XIP 24 select ARCH_HAS_THREAD_LOCAL_STORAGE 25 select ARCH_SUPPORTS_ROM_START 26 help 27 ARC architecture 28 29config ARM 30 bool 31 select ARCH_IS_SET 32 select ARCH_SUPPORTS_COREDUMP if CPU_CORTEX_M 33 select HAS_DTS 34 # FIXME: current state of the code for all ARM requires this, but 35 # is really only necessary for Cortex-M with ARM MPU! 36 select GEN_PRIV_STACKS 37 select ARCH_HAS_THREAD_LOCAL_STORAGE if CPU_AARCH32_CORTEX_R || CPU_CORTEX_M || CPU_AARCH32_CORTEX_A 38 select BARRIER_OPERATIONS_ARCH 39 help 40 ARM architecture 41 42config ARM64 43 bool 44 select ARCH_IS_SET 45 select 64BIT 46 select HAS_DTS 47 select ARCH_SUPPORTS_COREDUMP 48 select HAS_ARM_SMCCC 49 select ARCH_HAS_THREAD_LOCAL_STORAGE 50 select USE_SWITCH 51 select USE_SWITCH_SUPPORTED 52 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 53 select BARRIER_OPERATIONS_ARCH 54 help 55 ARM64 (AArch64) architecture 56 57config MIPS 58 bool 59 select ARCH_IS_SET 60 select ATOMIC_OPERATIONS_C 61 select HAS_DTS 62 help 63 MIPS architecture 64 65config SPARC 66 bool 67 select ARCH_IS_SET 68 select HAS_DTS 69 select USE_SWITCH 70 select USE_SWITCH_SUPPORTED 71 select BIG_ENDIAN 72 select ATOMIC_OPERATIONS_BUILTIN if SPARC_CASA 73 select ATOMIC_OPERATIONS_C if !SPARC_CASA 74 select ARCH_HAS_THREAD_LOCAL_STORAGE 75 select ARCH_HAS_EXTRA_EXCEPTION_INFO 76 help 77 SPARC architecture 78 79config X86 80 bool 81 select ARCH_IS_SET 82 select ATOMIC_OPERATIONS_BUILTIN 83 select HAS_DTS 84 select ARCH_SUPPORTS_COREDUMP 85 select ARCH_SUPPORTS_ROM_START if !X86_64 86 select CPU_HAS_MMU 87 select ARCH_MEM_DOMAIN_DATA if USERSPACE && !X86_COMMON_PAGE_TABLE 88 select ARCH_MEM_DOMAIN_SYNCHRONOUS_API if USERSPACE 89 select ARCH_HAS_GDBSTUB if !X86_64 90 select ARCH_HAS_TIMING_FUNCTIONS 91 select ARCH_HAS_THREAD_LOCAL_STORAGE 92 select ARCH_HAS_DEMAND_PAGING 93 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 94 select NEED_LIBC_MEM_PARTITION if USERSPACE && TIMING_FUNCTIONS \ 95 && !BOARD_HAS_TIMING_FUNCTIONS \ 96 && !SOC_HAS_TIMING_FUNCTIONS 97 select ARCH_HAS_STACK_CANARIES_TLS 98 help 99 x86 architecture 100 101config NIOS2 102 bool 103 select ARCH_IS_SET 104 select ATOMIC_OPERATIONS_C 105 select HAS_DTS 106 imply XIP 107 select ARCH_HAS_TIMING_FUNCTIONS 108 help 109 Nios II Gen 2 architecture 110 111config RISCV 112 bool 113 select ARCH_IS_SET 114 select HAS_DTS 115 select ARCH_SUPPORTS_COREDUMP 116 select ARCH_SUPPORTS_ROM_START if !SOC_SERIES_ESP32C3 117 select ARCH_HAS_CODE_DATA_RELOCATION 118 select ARCH_HAS_THREAD_LOCAL_STORAGE 119 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 120 select USE_SWITCH_SUPPORTED 121 select USE_SWITCH 122 select SCHED_IPI_SUPPORTED if SMP 123 select BARRIER_OPERATIONS_BUILTIN 124 imply XIP 125 help 126 RISCV architecture 127 128config XTENSA 129 bool 130 select ARCH_IS_SET 131 select HAS_DTS 132 select USE_SWITCH 133 select USE_SWITCH_SUPPORTED 134 select IRQ_OFFLOAD_NESTED if IRQ_OFFLOAD 135 select ARCH_HAS_CODE_DATA_RELOCATION 136 select ARCH_HAS_TIMING_FUNCTIONS 137 imply ATOMIC_OPERATIONS_ARCH 138 help 139 Xtensa architecture 140 141config ARCH_POSIX 142 bool 143 select ARCH_IS_SET 144 select HAS_DTS 145 select ATOMIC_OPERATIONS_BUILTIN 146 select ARCH_HAS_CUSTOM_SWAP_TO_MAIN 147 select ARCH_HAS_CUSTOM_BUSY_WAIT 148 select ARCH_HAS_THREAD_ABORT 149 select NATIVE_BUILD 150 select HAS_COVERAGE_SUPPORT 151 select BARRIER_OPERATIONS_BUILTIN 152 help 153 POSIX (native) architecture 154 155config ARCH_IS_SET 156 bool 157 help 158 Helper symbol to detect SoCs forgetting to select one of the arch 159 symbols above. See the top-level CMakeLists.txt. 160 161menu "General Architecture Options" 162 163source "arch/common/Kconfig" 164 165module = ARCH 166module-str = arch 167source "subsys/logging/Kconfig.template.log_config" 168 169config BIG_ENDIAN 170 bool 171 help 172 This option tells the build system that the target system is big-endian. 173 Little-endian architecture is the default and should leave this option 174 unselected. This option is selected by arch/$ARCH/Kconfig, 175 soc/**/Kconfig, or boards/**/Kconfig and the user should generally avoid 176 modifying it. The option is used to select linker script OUTPUT_FORMAT 177 and command line option for gen_isr_tables.py. 178 179config LITTLE_ENDIAN 180 # Hidden Kconfig option representing the default little-endian architecture 181 # This is just the opposite of BIG_ENDIAN and is used for non-negative 182 # conditional compilation 183 bool 184 depends on !BIG_ENDIAN 185 default y 186 187config 64BIT 188 bool 189 help 190 This option tells the build system that the target system is 191 using a 64-bit address space, meaning that pointer and long types 192 are 64 bits wide. This option is selected by arch/$ARCH/Kconfig, 193 soc/**/Kconfig, or boards/**/Kconfig and the user should generally 194 avoid modifying it. 195 196# Workaround for not being able to have commas in macro arguments 197DT_CHOSEN_Z_SRAM := zephyr,sram 198 199config SRAM_SIZE 200 int "SRAM Size in kB" 201 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_SRAM),0,K) 202 help 203 The SRAM size in kB. The default value comes from /chosen/zephyr,sram in 204 devicetree. The user should generally avoid changing it via menuconfig or 205 in configuration files. 206 207config SRAM_BASE_ADDRESS 208 hex "SRAM Base Address" 209 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_SRAM)) 210 help 211 The SRAM base address. The default value comes from from 212 /chosen/zephyr,sram in devicetree. The user should generally avoid 213 changing it via menuconfig or in configuration files. 214 215if ARC || ARM || ARM64 || NIOS2 || X86 || RISCV 216 217# Workaround for not being able to have commas in macro arguments 218DT_CHOSEN_Z_FLASH := zephyr,flash 219 220config FLASH_SIZE 221 int "Flash Size in kB" 222 default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K) if (XIP && (ARM ||ARM64)) || !ARM 223 help 224 This option specifies the size of the flash in kB. It is normally set by 225 the board's defconfig file and the user should generally avoid modifying 226 it via the menu configuration. 227 228config FLASH_BASE_ADDRESS 229 hex "Flash Base Address" 230 default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) if (XIP && (ARM || ARM64)) || !ARM 231 help 232 This option specifies the base address of the flash on the board. It is 233 normally set by the board's defconfig file and the user should generally 234 avoid modifying it via the menu configuration. 235 236endif # ARM || ARM64 || ARC || NIOS2 || X86 || RISCV 237 238if ARCH_HAS_TRUSTED_EXECUTION 239 240config TRUSTED_EXECUTION_SECURE 241 bool "Trusted Execution: Secure firmware image" 242 help 243 Select this option to enable building a Secure firmware 244 image for a platform that supports Trusted Execution. A 245 Secure firmware image will execute in Secure state. It may 246 allow the CPU to execute in Non-Secure (Normal) state. 247 Therefore, a Secure firmware image shall be able to 248 configure security attributions of CPU resources (memory 249 areas, peripherals, interrupts, etc.) as well as to handle 250 faults, related to security violations. It may optionally 251 allow certain functions to be called from the Non-Secure 252 (Normal) domain. 253 254config TRUSTED_EXECUTION_NONSECURE 255 depends on !TRUSTED_EXECUTION_SECURE 256 bool "Trusted Execution: Non-Secure firmware image" 257 help 258 Select this option to enable building a Non-Secure 259 firmware image for a platform that supports Trusted 260 Execution. A Non-Secure firmware image will execute 261 in Non-Secure (Normal) state. Therefore, it shall not 262 access CPU resources (memory areas, peripherals, 263 interrupts etc.) belonging to the Secure domain. 264 265endif # ARCH_HAS_TRUSTED_EXECUTION 266 267config HW_STACK_PROTECTION 268 bool "Hardware Stack Protection" 269 depends on ARCH_HAS_STACK_PROTECTION 270 help 271 Select this option to enable hardware-based platform features to 272 catch stack overflows when the system is running in privileged 273 mode. If CONFIG_USERSPACE is not enabled, the system is always 274 running in privileged mode. 275 276 Note that this does not necessarily prevent corruption and assertions 277 about the overall system state when a fault is triggered cannot be 278 made. 279 280config USERSPACE 281 bool "User mode threads" 282 depends on ARCH_HAS_USERSPACE 283 depends on RUNTIME_ERROR_CHECKS 284 depends on SRAM_REGION_PERMISSIONS 285 select THREAD_STACK_INFO 286 select LINKER_USE_NO_RELAX 287 help 288 When enabled, threads may be created or dropped down to user mode, 289 which has significantly restricted permissions and must interact 290 with the kernel via system calls. See Zephyr documentation for more 291 details about this feature. 292 293 If a user thread overflows its stack, this will be caught and the 294 kernel itself will be shielded from harm. Enabling this option 295 may or may not catch stack overflows when the system is in 296 privileged mode or handling a system call; to ensure these are always 297 caught, enable CONFIG_HW_STACK_PROTECTION. 298 299config PRIVILEGED_STACK_SIZE 300 int "Size of privileged stack" 301 default 2048 if EMUL 302 default 1024 303 depends on ARCH_HAS_USERSPACE 304 help 305 This option sets the privileged stack region size that will be used 306 in addition to the user mode thread stack. During normal execution, 307 this region will be inaccessible from user mode. During system calls, 308 this region will be utilized by the system call. This value must be 309 a multiple of the minimum stack alignment. 310 311config KOBJECT_TEXT_AREA 312 int "Size of kobject text area" 313 default 512 if COVERAGE_GCOV 314 default 512 if NO_OPTIMIZATIONS 315 default 512 if STACK_CANARIES && RISCV 316 default 256 317 depends on ARCH_HAS_USERSPACE 318 help 319 Size of kernel object text area. Used in linker script. 320 321config KOBJECT_DATA_AREA_RESERVE_EXTRA_PERCENT 322 int "Reserve extra kobject data area (in percentage)" 323 default 100 324 depends on ARCH_HAS_USERSPACE 325 help 326 Multiplication factor used to calculate the size of placeholder to 327 reserve space for kobject metadata hash table. The hash table is 328 generated via gperf is highly dependent on the absolute addresses of 329 kobjects which might change between prebuilts. To reserve enough 330 space for the hash table during final linking passes to keep 331 kobjects in same place, the size of reserved space is calculated 332 from the first prebuilt plus additional space calculated with 333 this percentage (of the kobject data area in first prebuilt). 334 335config KOBJECT_RODATA_AREA_EXTRA_BYTES 336 int "Reserve extra bytes for kobject rodata area" 337 default 16 338 depends on ARCH_HAS_USERSPACE 339 help 340 Reserve a few more bytes for the RODATA region for kobject metadata. 341 This is to account for the uncertainty of tables generated by gperf. 342 343config GEN_PRIV_STACKS 344 bool 345 help 346 Selected if the architecture requires that privilege elevation stacks 347 be allocated in a separate memory area. This is typical of arches 348 whose MPUs require regions to be power-of-two aligned/sized. 349 350 FIXME: This should be removed and replaced with checks against 351 CONFIG_MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT, but both ARM and ARC 352 changes will be necessary for this. 353 354config STACK_GROWS_UP 355 bool "Stack grows towards higher memory addresses" 356 help 357 Select this option if the architecture has upward growing thread 358 stacks. This is not common. 359 360config NO_UNUSED_STACK_INSPECTION 361 bool 362 help 363 Selected if the architecture will generate a fault if unused stack 364 memory is examined, which is the region between the current stack 365 pointer and the deepest available address in the current stack 366 region. 367 368config MAX_THREAD_BYTES 369 int "Bytes to use when tracking object thread permissions" 370 default 2 371 depends on USERSPACE 372 help 373 Every kernel object will have an associated bitfield to store 374 thread permissions for that object. This controls the size of the 375 bitfield (in bytes) and imposes a limit on how many threads can 376 be created in the system. 377 378config DYNAMIC_OBJECTS 379 bool "Allow kernel objects to be allocated at runtime" 380 depends on USERSPACE 381 help 382 Enabling this option allows for kernel objects to be requested from 383 the calling thread's resource pool, at a slight cost in performance 384 due to the supplemental run-time tables required to validate such 385 objects. 386 387 Objects allocated in this way can be freed with a supervisor-only 388 API call, or when the number of references to that object drops to 389 zero. 390 391config NOCACHE_MEMORY 392 bool "Support for uncached memory" 393 depends on ARCH_HAS_NOCACHE_MEMORY_SUPPORT 394 help 395 Add a "nocache" read-write memory section that is configured to 396 not be cached. This memory section can be used to perform DMA 397 transfers when cache coherence issues are not optimal or can not 398 be solved using cache maintenance operations. 399 400menu "Interrupt Configuration" 401 402config DYNAMIC_INTERRUPTS 403 bool "Installation of IRQs at runtime" 404 help 405 Enable installation of interrupts at runtime, which will move some 406 interrupt-related data structures to RAM instead of ROM, and 407 on some architectures increase code size. 408 409config SHARED_INTERRUPTS 410 bool "Set this to enable support for shared interrupts" 411 depends on GEN_SW_ISR_TABLE 412 select EXPERIMENTAL 413 help 414 Set this to enable support for shared interrupts. Use this with 415 caution as enabling this will increase the image size by a 416 non-negligible amount. 417 418config SHARED_IRQ_MAX_NUM_CLIENTS 419 int "Maximum number of clients allowed per shared interrupt" 420 default 2 421 depends on SHARED_INTERRUPTS 422 help 423 This option controls the maximum number of clients allowed 424 per shared interrupt. Set this according to your needs. 425 426config GEN_ISR_TABLES 427 bool "Use generated IRQ tables" 428 help 429 This option controls whether a platform uses the gen_isr_tables 430 script to generate its interrupt tables. This mechanism will create 431 an appropriate hardware vector table and/or software IRQ table. 432 433config GEN_IRQ_VECTOR_TABLE 434 bool "Generate an interrupt vector table" 435 default y 436 depends on GEN_ISR_TABLES 437 help 438 This option controls whether a platform using gen_isr_tables 439 needs an interrupt vector table created. Only disable this if the 440 platform does not use a vector table at all, or requires the vector 441 table to be in a format that is not an array of function pointers 442 indexed by IRQ line. In the latter case, the vector table must be 443 supplied by the application or architecture code. 444 445config ARCH_IRQ_VECTOR_TABLE_ALIGN 446 int "Alignment size of the interrupt vector table" 447 default 4 448 depends on GEN_IRQ_VECTOR_TABLE 449 help 450 This option controls alignment size of generated 451 _irq_vector_table. Some architecture needs an IRQ vector table 452 to be aligned to architecture specific size. The default 453 size is 0 for no alignment. 454 455choice IRQ_VECTOR_TABLE_TYPE 456 prompt "IRQ vector table type" 457 depends on GEN_IRQ_VECTOR_TABLE 458 default IRQ_VECTOR_TABLE_JUMP_BY_CODE if (RISCV && !RISCV_HAS_CLIC) 459 default IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 460 461config IRQ_VECTOR_TABLE_JUMP_BY_ADDRESS 462 bool "Jump by address" 463 help 464 The IRQ vector table contains the address of the interrupt handler. 465 466config IRQ_VECTOR_TABLE_JUMP_BY_CODE 467 bool "Jump by code" 468 help 469 The IRQ vector table contains the opcode of a jump instruction to the 470 interrupt handler address. 471 472endchoice 473 474config GEN_SW_ISR_TABLE 475 bool "Generate a software ISR table" 476 default y 477 depends on GEN_ISR_TABLES 478 help 479 This option controls whether a platform using gen_isr_tables 480 needs a software ISR table table created. This is an array of struct 481 _isr_table_entry containing the interrupt service routine and supplied 482 parameter. 483 484config ARCH_SW_ISR_TABLE_ALIGN 485 int "Alignment size of a software ISR table" 486 default 64 if RISCV_HAS_CLIC 487 default 4 488 depends on GEN_SW_ISR_TABLE 489 help 490 This option controls alignment size of generated 491 _sw_isr_table. Some architecture needs a software ISR table 492 to be aligned to architecture specific size. The default 493 size is 4. 494 495config GEN_IRQ_START_VECTOR 496 int 497 default 0 498 depends on GEN_ISR_TABLES 499 help 500 On some architectures, part of the vector table may be reserved for 501 system exceptions and is declared separately from the tables 502 created by gen_isr_tables.py. When creating these tables, this value 503 will be subtracted from CONFIG_NUM_IRQS to properly size them. 504 This is a hidden option which needs to be set per architecture and 505 left alone. 506 507config IRQ_OFFLOAD 508 bool "IRQ offload" 509 depends on TEST 510 help 511 Enable irq_offload() API which allows functions to be synchronously 512 run in interrupt context. Only useful for test cases that need 513 to validate the correctness of kernel objects in IRQ context. 514 515config IRQ_OFFLOAD_NESTED 516 bool "irq_offload() supports nested IRQs" 517 depends on IRQ_OFFLOAD 518 help 519 When set by the arch layer, indicates that irq_offload() may 520 legally be called in interrupt context to cause a 521 synchronous nested interrupt on the current CPU. Not all 522 hardware is capable. 523 524config EXTRA_EXCEPTION_INFO 525 bool "Collect extra exception info" 526 depends on ARCH_HAS_EXTRA_EXCEPTION_INFO 527 help 528 This option enables the collection of extra information, such as 529 register state, when a fault occurs. This information can be useful 530 to collect for post-mortem analysis and debug of issues. 531 532config SIMPLIFIED_EXCEPTION_CODES 533 bool "Convert arch specific exception codes to K_ERR_CPU_EXCEPTION" 534 default y if ZTEST 535 help 536 The same piece of faulty code (NULL dereference, etc) can result in 537 a multitude of potential exception codes at the CPU level, depending 538 upon whether addresses exist, an MPU is configured, the particular 539 implementation of the CPU or any number of other reasons. Enabling 540 this option collapses all the architecture specific exception codes 541 down to the generic K_ERR_CPU_EXCEPTION, which makes testing code 542 much more portable. 543 544endmenu # Interrupt configuration 545 546config INIT_ARCH_HW_AT_BOOT 547 bool "Initialize internal architecture state at boot" 548 depends on ARCH_SUPPORTS_ARCH_HW_INIT 549 help 550 This option instructs Zephyr to force the initialization 551 of the internal architectural state (for example ARCH-level 552 HW registers and system control blocks) during boot to 553 the reset values as specified by the corresponding 554 architecture manual. The option is useful when the Zephyr 555 firmware image is chain-loaded, for example, by a debugger 556 or a bootloader, and we need to guarantee that the internal 557 states of the architecture core blocks are restored to the 558 reset values (as specified by the architecture). 559 560 Note: the functionality is architecture-specific. For the 561 implementation details refer to each architecture where 562 this feature is supported. 563 564endmenu 565 566# 567# Architecture Capabilities 568# 569 570config ARCH_HAS_SINGLE_THREAD_SUPPORT 571 bool 572 573config ARCH_HAS_TIMING_FUNCTIONS 574 bool 575 576config ARCH_HAS_TRUSTED_EXECUTION 577 bool 578 579config ARCH_HAS_STACK_PROTECTION 580 bool 581 582config ARCH_HAS_USERSPACE 583 bool 584 585config ARCH_HAS_EXECUTABLE_PAGE_BIT 586 bool 587 588config ARCH_HAS_NOCACHE_MEMORY_SUPPORT 589 bool 590 591config ARCH_HAS_RAMFUNC_SUPPORT 592 bool 593 594config ARCH_HAS_NESTED_EXCEPTION_DETECTION 595 bool 596 597config ARCH_SUPPORTS_COREDUMP 598 bool 599 600config ARCH_SUPPORTS_ARCH_HW_INIT 601 bool 602 603config ARCH_SUPPORTS_ROM_START 604 bool 605 606config ARCH_HAS_EXTRA_EXCEPTION_INFO 607 bool 608 609config ARCH_HAS_GDBSTUB 610 bool 611 612config ARCH_HAS_COHERENCE 613 bool 614 help 615 When selected, the architecture supports the 616 arch_mem_coherent() API and can link into incoherent/cached 617 memory using the ".cached" linker section. 618 619config ARCH_HAS_THREAD_LOCAL_STORAGE 620 bool 621 622config ARCH_HAS_SUSPEND_TO_RAM 623 bool 624 help 625 When selected, the architecture supports suspend-to-RAM (S2RAM). 626 627config ARCH_HAS_STACK_CANARIES_TLS 628 bool 629 630# 631# Other architecture related options 632# 633 634config ARCH_HAS_THREAD_ABORT 635 bool 636 637config ARCH_HAS_CODE_DATA_RELOCATION 638 bool 639 help 640 When selected, the architecture/SoC implements support for 641 CODE_DATA_RELOCATION in its linker scripts. 642 643# 644# Hidden CPU family configs 645# 646 647config CPU_HAS_TEE 648 bool 649 help 650 This option is enabled when the CPU has support for Trusted 651 Execution Environment (e.g. when it has a security attribution 652 unit). 653 654config CPU_HAS_DCLS 655 bool 656 help 657 This option is enabled when the processor hardware has support for 658 Dual-redundant Core Lock-step (DCLS) topology. 659 660config CPU_HAS_FPU 661 bool 662 help 663 This option is enabled when the CPU has hardware floating point 664 unit. 665 666config CPU_HAS_FPU_DOUBLE_PRECISION 667 bool 668 select CPU_HAS_FPU 669 help 670 When enabled, this indicates that the CPU has a double floating point 671 precision unit. 672 673config CPU_HAS_MPU 674 bool 675 help 676 This option is enabled when the CPU has a Memory Protection Unit (MPU). 677 678config CPU_HAS_MMU 679 bool 680 help 681 This hidden option is selected when the CPU has a Memory Management Unit 682 (MMU). 683 684config ARCH_HAS_DEMAND_PAGING 685 bool 686 help 687 This hidden configuration should be selected by the architecture if 688 demand paging is supported. 689 690config ARCH_HAS_RESERVED_PAGE_FRAMES 691 bool 692 help 693 This hidden configuration should be selected by the architecture if 694 certain RAM page frames need to be marked as reserved and never used for 695 memory mappings. The architecture will need to implement 696 arch_reserved_pages_update(). 697 698config CPU_HAS_DCACHE 699 bool 700 help 701 This hidden configuration should be selected when the CPU has a d-cache. 702 703config CPU_HAS_ICACHE 704 bool 705 help 706 This hidden configuration should be selected when the CPU has an i-cache. 707 708config ARCH_MAPS_ALL_RAM 709 bool 710 help 711 This hidden option is selected by the architecture to inform the kernel 712 that all RAM is mapped at boot, and not just the bounds of the Zephyr image. 713 If RAM starts at 0x0, the first page must remain un-mapped to catch NULL 714 pointer dereferences. With this enabled, the kernel will not assume that 715 virtual memory addresses past the kernel image are available for mappings, 716 but instead takes into account an entire RAM mapping instead. 717 718 This is typically set by architectures which need direct access to all memory. 719 It is the architecture's responsibility to mark reserved memory regions 720 as such in arch_reserved_pages_update(). 721 722 Although the kernel will not disturb this RAM mapping by re-mapping the associated 723 virtual addresses elsewhere, this is limited to only management of the 724 virtual address space. The kernel's page frame ontology will not consider 725 this mapping at all; non-kernel pages will be considered free (unless marked 726 as reserved) and Z_PAGE_FRAME_MAPPED will not be set. 727 728config DCLS 729 bool "Processor is configured in DCLS mode" 730 depends on CPU_HAS_DCLS 731 default y 732 help 733 This option is enabled when the processor hardware is configured in 734 Dual-redundant Core Lock-step (DCLS) topology. For the processor that 735 supports DCLS, but is configured in split-lock mode (by default or 736 changed at flash time), this option should be disabled. 737 738menuconfig MPU 739 bool "MPU features" 740 depends on CPU_HAS_MPU 741 help 742 This option, when enabled, indicates to the core kernel that an MPU 743 is enabled. 744 745if MPU 746module = MPU 747module-str = mpu 748source "subsys/logging/Kconfig.template.log_config" 749 750config MPU_REQUIRES_POWER_OF_TWO_ALIGNMENT 751 bool 752 help 753 This option is enabled when the MPU requires a power of two alignment 754 and size for MPU regions. 755 756config MPU_REQUIRES_NON_OVERLAPPING_REGIONS 757 bool 758 help 759 This option is enabled when the MPU requires the active (i.e. enabled) 760 MPU regions to be non-overlapping with each other. 761 762config MPU_GAP_FILLING 763 bool "Force MPU to be filling in background memory regions" 764 depends on MPU_REQUIRES_NON_OVERLAPPING_REGIONS 765 default y if !USERSPACE 766 help 767 This Kconfig option instructs the MPU driver to enforce 768 a full kernel SRAM partitioning, when it programs the 769 dynamic MPU regions (user thread stack, PRIV stack guard 770 and application memory domains) during context-switch. We 771 allow this to be a configurable option, in order to be able 772 to switch the option off and have an increased number of MPU 773 regions available for application memory domain programming. 774 775 Notes: 776 An increased number of MPU regions should only be required, 777 when building with USERSPACE support. As a result, when we 778 build without USERSPACE support, gap filling should always 779 be required. 780 781 When the option is switched off, access to memory areas not 782 covered by explicit MPU regions is restricted to privileged 783 code on an ARCH-specific basis. Refer to ARCH-specific 784 documentation for more information on how this option is 785 used. 786 787endif # MPU 788 789config SRAM_REGION_PERMISSIONS 790 bool "Assign appropriate permissions to kernel areas in SRAM" 791 depends on MMU || MPU 792 default y 793 help 794 This option indicates that memory protection hardware 795 is present, enabled, and regions have been configured at boot for memory 796 ranges within the kernel image. 797 798 If this option is turned on, certain areas of the kernel image will 799 have the following access policies applied for all threads, including 800 supervisor threads: 801 802 1) All program text will be have read-only, execute memory permission 803 2) All read-only data will have read-only permission, and execution 804 disabled if the hardware supports it. 805 3) All other RAM addresses will have read-write permission, and 806 execution disabled if the hardware supports it. 807 808 Options such as USERSPACE or HW_STACK_PROTECTION may additionally 809 impose additional policies on the memory map, which may be global 810 or local to the current running thread. 811 812 This option may consume additional memory to satisfy memory protection 813 hardware alignment constraints. 814 815 If this option is disabled, the entire kernel will have default memory 816 access permissions set, typically read/write/execute. It may be desirable 817 to turn this off on MMU systems which are using the MMU for demand 818 paging, do not need memory protection, and would rather not use up 819 RAM for the alignment between regions. 820 821config CODE_DATA_RELOCATION 822 bool "Support code/data section relocation" 823 depends on ARCH_HAS_CODE_DATA_RELOCATION 824 help 825 Enable support for relocating .text, data and .bss sections from specified 826 files and placing them in a chosen memory region. Files to relocate and 827 the target regions should be specified in CMakeLists.txt using 828 zephyr_code_relocate(). 829 830menu "Floating Point Options" 831 832config FPU 833 bool "Floating point unit (FPU)" 834 depends on CPU_HAS_FPU 835 help 836 This option enables the hardware Floating Point Unit (FPU), in order to 837 support using the floating point registers and instructions. 838 839 When this option is enabled, by default, threads may use the floating 840 point registers only in an exclusive manner, and this usually means that 841 only one thread may perform floating point operations. 842 843 If it is necessary for multiple threads to perform concurrent floating 844 point operations, the "FPU register sharing" option must be enabled to 845 preserve the floating point registers across context switches. 846 847 Note that this option cannot be selected for the platforms that do not 848 include a hardware floating point unit; the floating point support for 849 those platforms is dependent on the availability of the toolchain- 850 provided software floating point library. 851 852config FPU_SHARING 853 bool "FPU register sharing" 854 depends on FPU && MULTITHREADING 855 help 856 This option enables preservation of the hardware floating point registers 857 across context switches to allow multiple threads to perform concurrent 858 floating point operations. 859 860 Note that some compiler configurations may activate a floating point 861 context by generating FP instructions for any thread, and that 862 context must be preserved when switching such threads in and out. 863 The developers can still disable the FP sharing mode in their 864 application projects, and switch to Unshared FP registers mode, 865 if it is guaranteed that the image code does not generate FP 866 instructions outside the single thread context that is allowed 867 to do so. 868 869endmenu 870 871menu "Cache Options" 872 873config DCACHE 874 bool "Data cache (d-cache) support" 875 depends on CPU_HAS_DCACHE 876 default y 877 help 878 This option enables the support for the data cache (d-cache). 879 880config ICACHE 881 bool "Instruction cache (i-cache) support" 882 depends on CPU_HAS_ICACHE 883 default y 884 help 885 This option enables the support for the instruction cache (i-cache). 886 887config CACHE_MANAGEMENT 888 bool "Cache management features" 889 depends on DCACHE || ICACHE 890 help 891 This option enables the cache management functions backed by arch or 892 driver code. 893 894config DCACHE_LINE_SIZE_DETECT 895 bool "Detect d-cache line size at runtime" 896 depends on CACHE_MANAGEMENT && DCACHE 897 help 898 This option enables querying some architecture-specific hardware for 899 finding the d-cache line size at the expense of taking more memory and 900 code and a slightly increased boot time. 901 902 If the CPU's d-cache line size is known in advance, disable this option and 903 manually enter the value for DCACHE_LINE_SIZE or set it in the DT 904 using the 'd-cache-line-size' property. 905 906config DCACHE_LINE_SIZE 907 int "d-cache line size" 908 depends on CACHE_MANAGEMENT && DCACHE && !DCACHE_LINE_SIZE_DETECT 909 default 0 910 help 911 Size in bytes of a CPU d-cache line. If this is set to 0 the value is 912 obtained from the 'd-cache-line-size' DT property instead if present. 913 914 915 Detect automatically at runtime by selecting DCACHE_LINE_SIZE_DETECT. 916 917config ICACHE_LINE_SIZE_DETECT 918 bool "Detect i-cache line size at runtime" 919 depends on CACHE_MANAGEMENT && ICACHE 920 help 921 This option enables querying some architecture-specific hardware for 922 finding the i-cache line size at the expense of taking more memory and 923 code and a slightly increased boot time. 924 925 If the CPU's i-cache line size is known in advance, disable this option and 926 manually enter the value for ICACHE_LINE_SIZE or set it in the DT 927 using the 'i-cache-line-size' property. 928 929config ICACHE_LINE_SIZE 930 int "i-cache line size" 931 depends on CACHE_MANAGEMENT && ICACHE && !ICACHE_LINE_SIZE_DETECT 932 default 0 933 help 934 Size in bytes of a CPU i-cache line. If this is set to 0 the value is 935 obtained from the 'i-cache-line-size' DT property instead if present. 936 937 Detect automatically at runtime by selecting ICACHE_LINE_SIZE_DETECT. 938 939choice CACHE_TYPE 940 prompt "Cache type" 941 depends on CACHE_MANAGEMENT 942 default ARCH_CACHE 943 944config ARCH_CACHE 945 bool "Integrated cache controller" 946 help 947 Integrated on-core cache controller 948 949config EXTERNAL_CACHE 950 bool "External cache controller" 951 help 952 External cache controller 953 954endchoice 955 956endmenu 957 958config ARCH 959 string 960 help 961 System architecture string. 962 963config SOC 964 string 965 help 966 SoC name which can be found under soc/<arch>/<soc name>. 967 This option holds the directory name used by the build system to locate 968 the correct linker and header files for the SoC. 969 970config SOC_SERIES 971 string 972 help 973 SoC series name which can be found under soc/<arch>/<family>/<series>. 974 This option holds the directory name used by the build system to locate 975 the correct linker and header files. 976 977config SOC_FAMILY 978 string 979 help 980 SoC family name which can be found under soc/<arch>/<family>. 981 This option holds the directory name used by the build system to locate 982 the correct linker and header files. 983 984config TOOLCHAIN_HAS_BUILTIN_FFS 985 bool 986 default y if !(64BIT && RISCV) 987 help 988 Hidden option to signal that toolchain has __builtin_ffs*(). 989
