1# SPDX-License-Identifier: BSD-3-Clause 2 3menu "Platform" 4 5choice 6 prompt "Platform" 7 default ZEPHYR_POSIX if ARCH_POSIX 8 default TIGERLAKE 9 10config TIGERLAKE 11 bool "Build for Tigerlake" 12 select XT_BOOT_LOADER 13 select XT_IRQ_MAP 14 select DMA_GW 15 select DW 16 select DW_DMA if !ZEPHYR_NATIVE_DRIVERS 17 select MEM_WND 18 select DMA_HW_LLI 19 select DW_DMA_AGGREGATED_IRQ 20 select DMA_FIFO_PARTITION 21 select CAVS 22 select CAVS_VERSION_2_5 23 select XT_WAITI_DELAY 24 select NO_SECONDARY_CORE_ROM 25 select CAVS_USE_LPRO_IN_WAITI 26 help 27 Select if your target platform is Tigerlake-compatible 28 29 30config METEORLAKE 31 bool "Build for Meteorlake" 32 select ACE 33 select ACE_VERSION_1_5 34 help 35 Select if your target platform is Meteorlake-compatible 36 37config LIBRARY 38 bool "Build Library" 39 help 40 Select if you want to build a library. 41 It is generic/mock configuration not tied to some specific platform. 42 Library builds are not intended to be run on DSP, but to be used by 43 user-space applications. 44 45config LIBRARY_STATIC 46 bool "Build Library as static archive" 47 depends on LIBRARY 48 help 49 Select if you want to build a static library otherwise a dynamic 50 shared library will be built. 51 52config ZEPHYR_POSIX 53 bool "Build for Zephyr native_posix board" 54 help 55 Select if you are building a host unit test using 56 native_posix. This is similar to LIBRARY in that it builds 57 host binaries, but is tied to the Zephyr posix architecture 58 and thus able to instrument and test the whole OS 59 environment. 60 61config IMX8 62 bool "Build for NXP i.MX8" 63 select XT_HAVE_RESET_VECTOR_ROM 64 select XT_INTERRUPT_LEVEL_1 65 select XT_INTERRUPT_LEVEL_2 66 select XT_INTERRUPT_LEVEL_3 67 select HOST_PTABLE 68 select DUMMY_DMA 69 select XT_WAITI_DELAY 70 select IMX 71 select IMX_EDMA 72 select IMX_ESAI 73 select SCHEDULE_DMA_MULTI_CHANNEL 74 select IMX_INTERRUPT_IRQSTEER 75 help 76 Select if your target platform is imx8-compatible 77 78config IMX8X 79 bool "Build for NXP i.MX8X" 80 select XT_HAVE_RESET_VECTOR_ROM 81 select XT_INTERRUPT_LEVEL_1 82 select XT_INTERRUPT_LEVEL_2 83 select XT_INTERRUPT_LEVEL_3 84 select HOST_PTABLE 85 select DUMMY_DMA 86 select XT_WAITI_DELAY 87 select IMX 88 select IMX_EDMA 89 select IMX_ESAI 90 select SCHEDULE_DMA_MULTI_CHANNEL 91 select IMX_INTERRUPT_IRQSTEER 92 help 93 Select if your target platform is imx8x-compatible 94 95config IMX8M 96 bool "Build for NXP i.MX8M" 97 select XT_HAVE_RESET_VECTOR_ROM 98 select XT_INTERRUPT_LEVEL_1 99 select XT_INTERRUPT_LEVEL_2 100 select XT_INTERRUPT_LEVEL_3 101 select HOST_PTABLE 102 select DUMMY_DMA 103 select XT_WAITI_DELAY 104 select IMX 105 select IMX_SDMA 106 select SCHEDULE_DMA_MULTI_CHANNEL 107 select IMX_INTERRUPT_IRQSTEER 108 help 109 Select if your target platform is imx8m-compatible 110 111config IMX8ULP 112 bool "Build for NXP i.MX8ULP" 113 select XT_HAVE_RESET_VECTOR_ROM 114 select XT_INTERRUPT_LEVEL_1 115 select XT_INTERRUPT_LEVEL_2 116 select XT_INTERRUPT_LEVEL_3 117 select HOST_PTABLE 118 select DUMMY_DMA 119 select XT_WAITI_DELAY 120 select IMX 121 select IMX_EDMA 122 select IMX_INTERRUPT_GENERIC 123 select SCHEDULE_DMA_MULTI_CHANNEL 124 help 125 Select if your target platform is imx8ulp-compatible. 126 imx.8ulp support dsp. 127 128config RENOIR 129 bool "Build for Renoir" 130 select XT_INTERRUPT_LEVEL_5 131 select XT_INTERRUPT_LEVEL_3 132 select XT_INTERRUPT_LEVEL_1 133 select XT_INTERRUPT_LEVEL_4 134 select XT_WAITI_DELAY 135 select SCHEDULE_DMA_MULTI_CHANNEL 136 help 137 Select if your target platform is renoir-compatible 138 139config REMBRANDT 140 bool "Build for Rembrandt" 141 select XT_INTERRUPT_LEVEL_5 142 select XT_INTERRUPT_LEVEL_3 143 select XT_INTERRUPT_LEVEL_1 144 select XT_INTERRUPT_LEVEL_4 145 select XT_WAITI_DELAY 146 select XTENSA_EXCLUSIVE 147 select SCHEDULE_DMA_MULTI_CHANNEL 148 help 149 Select if your target platform is rembrandt-compatible 150 151config MT8186 152 bool "Build for MTK MT8186" 153 select XT_INTERRUPT_LEVEL_1 154 select XT_INTERRUPT_LEVEL_2 155 select XT_INTERRUPT_LEVEL_3 156 select XT_INTERRUPT_LEVEL_4 157 select DUMMY_DMA 158 select HOST_PTABLE 159 select XT_WAITI_DELAY 160 select MEDIATEK 161 select XTENSA_EXCLUSIVE 162 select SCHEDULE_DMA_MULTI_CHANNEL 163 help 164 Select if your target platform is mt8186-compatible 165 166config MT8188 167 bool "Build for MTK MT8188" 168 select XT_INTERRUPT_LEVEL_1 169 select XT_INTERRUPT_LEVEL_2 170 select XT_INTERRUPT_LEVEL_3 171 select XT_INTERRUPT_LEVEL_4 172 select DUMMY_DMA 173 select HOST_PTABLE 174 select XT_WAITI_DELAY 175 select MEDIATEK 176 select XTENSA_EXCLUSIVE 177 select SCHEDULE_DMA_MULTI_CHANNEL 178 help 179 Select if your target platform is mt8188-compatible. 180 181config MT8195 182 bool "Build for MTK MT8195" 183 select XT_INTERRUPT_LEVEL_1 184 select XT_INTERRUPT_LEVEL_2 185 select XT_INTERRUPT_LEVEL_3 186 select DUMMY_DMA 187 select HOST_PTABLE 188 select MEDIATEK 189 select XTENSA_EXCLUSIVE 190 select SCHEDULE_DMA_MULTI_CHANNEL 191 help 192 Select if your target platform is mt8195-compatible 193 194endchoice 195 196config MAX_CORE_COUNT 197 int 198 default 4 if TIGERLAKE 199 default 3 if METEORLAKE 200 default 1 201 help 202 Maximum number of cores per configuration 203 204config CORE_COUNT 205 int "Number of cores" 206 default MP_NUM_CPUS if KERNEL_BIN_NAME = "zephyr" 207 default MAX_CORE_COUNT 208 range 1 MAX_CORE_COUNT 209 help 210 Number of used cores 211 Lowering available core count could result in lower power consumption 212 213config MULTICORE 214 bool 215 default CORE_COUNT > 1 216 help 217 Indicates that architecture uses multiple cores 218 219config INTEL 220 bool 221 default n 222 help 223 This has to be selected for every Intel platform. 224 It enables Intel platforms-specific features. 225 226config HOST 227 bool 228 default n 229 help 230 This has to be selected for building linux test targets. 231 232config IMX 233 bool 234 default n 235 select COMPILER_WORKAROUND_CACHE_ATTR 236 help 237 This has to be selected for every i.MX NXP platform. 238 It enables NXP platforms-specific features. 239 240config MEDIATEK 241 bool 242 default n 243 help 244 This has to be selected for every MediaTek platform. 245 It enables MediaTek platforms-specific features. 246 247config CAVS 248 bool 249 default n 250 select INTEL 251 select XT_INTERRUPT_LEVEL_2 252 select XT_INTERRUPT_LEVEL_5 253 select INTEL_HDA if !ZEPHYR_NATIVE_DRIVERS 254 select INTEL_MN 255 select WAKEUP_HOOK 256 select SCHEDULE_DMA_SINGLE_CHANNEL 257 258config CAVS_VERSION_2_5 259 depends on CAVS 260 bool 261 help 262 Select for CAVS version 2.5 263 264config ACE 265 bool 266 default n 267 select INTEL 268 269config ACE_VERSION_1_5 270 depends on ACE 271 bool 272 help 273 Select for ACE version 1.5 274 275config HP_MEMORY_BANKS 276 int "HP memory banks count" 277 depends on CAVS 278 default 8 279 help 280 Available memory banks count for High Performance memory 281 Lowering available banks could result in lower power consumption 282 Too low count should result in unresponsive/crashing image due to not 283 enough space for FW base image 284 Banks are 64kb in size. 285 286config LP_MEMORY_BANKS 287 int "LP memory banks count" 288 depends on CAVS 289 default 0 290 help 291 Available memory banks count for Low Power memory. 292 It can be used to turn ON/OFF LPSRAM bank/s. 293 Firmware will turn on only as many banks as are defined here. 294 295config LP_SRAM 296 bool 297 default LP_MEMORY_BANKS > 0 298 help 299 Indicates that platform uses LPSRAM. 300 301config L1_DRAM 302 bool "L1 DRAM memory support" 303 default n 304 help 305 Indicates that platform does support L1 DATA RAM. 306 307config L1_DRAM_MEMORY_BANKS 308 int "L1 DRAM memory banks count" 309 depends on L1_DRAM 310 default 0 311 help 312 Available memory banks count for L1 DATA RAM. 313 It can be used to turn ON/OFF L1 DRAM bank/s. 314 Firmware will turn on only as many banks as specified. 315 316config L1_DRAM_MEMORY_BANK_SIZE 317 int "L1 DRAM memory bank size" 318 depends on L1_DRAM 319 default 0 320 help 321 Specifies DRAM block size. 322 It can be used to calculate DRAM size. 323 324config CAVS_LPS 325 bool "Intel cAVS Low Power Sequencer for Power Management" 326 depends on CAVS 327 default n 328 help 329 Select this to enable Intel cAVS Low Power Sequencer. 330 This option is required to support S0ix/D0ix mode 331 on cAVS platforms. 332 333config CAVS_LPRO_ONLY 334 bool "Use low power ring oscillator always" 335 default n 336 depends on CAVS 337 help 338 Select if you want to use only the 120MHz LPRO as the DSP clock source. 339 This option is for debugging only at the moment, choose n if unclear. 340 341config CAVS_USE_LPRO_IN_WAITI 342 bool "Use low power ring oscillator in WFI" 343 default n 344 depends on CAVS && !CAVS_LPRO_ONLY 345 help 346 Select if we want to use LPRO clock in waiti. 347 After waiti exit clock source will be restored. 348 Choose n if unclear. 349 350config L3_HEAP 351 bool "Use L3 memory heap" 352 default n 353 help 354 Select this if L3 memory is supported on the platform and 355 it is intended to be used for dynamic allocations. 356 For Intel ACE platform the L3 memory is called 357 IMR (Isolated Memory Region). Feature has been 358 only tested on ACE platform. 359 Choose n if unclear. 360 361config CAVS_IMR_D3_PERSISTENT 362 bool "Intel IMR content persistent on DSP in D3" 363 depends on CAVS 364 default y 365 help 366 Select this if the Intel cAVS platform can keep the 367 IMR (Isolated Memory Region) content persistent when 368 the DSP is in power off (D3) mode, which means we 369 don't need to re-downloading firmware binary to DSP 370 SRAM so fast D3->D0 transition can be supported. 371 Choose n if unclear. 372 373# TODO: it should just take manifest version and offsets 374config RIMAGE_SIGNING_SCHEMA 375 string "Rimage firmware signing schema name" 376 default "tgl" if TIGERLAKE 377 default "imx8" if IMX8 378 default "imx8x" if IMX8X 379 default "imx8m" if IMX8M 380 default "imx8ulp" if IMX8ULP 381 default "rn" if RENOIR 382 default "mt8186" if MT8186 383 default "mt8188" if MT8188 384 default "mt8195" if MT8195 385 default "" 386 help 387 Signing schema name used by rimage to decide how to build final binary 388 389config SYSTICK_PERIOD 390 int "System tick period in microseconds" 391 default 1000 392 help 393 Defines platform system tick period. It is used 394 as a timeout check value for system agent. 395 Value should be provided in microseconds. 396 397config HAVE_AGENT 398 bool "Enable system agent" 399 default y 400 help 401 Enables system agent. It can be disabled on systems 402 which are still unstable and cannot assure that 403 system agent will always execute on time or systems 404 with DMA based scheduling, where asynchronous interrupts 405 can potentially starve the agent. 406 407config AMS 408 bool "Enable Async Messaging Service" 409 default n 410 help 411 Enables Async Messaging Service. 412 Async messages are used to send messages between modules. 413 414config AGENT_PANIC_ON_DELAY 415 bool "Enable system agent time verification panic" 416 default n 417 depends on HAVE_AGENT 418 help 419 Enables system agent time verification panic. 420 If scheduler timing verification fails, SA will 421 call a DSP panic. 422 423config XTENSA_EXCLUSIVE 424 bool 425 default n 426 help 427 This has to be selected for xtensa exclusive instructions. 428 There is a definition for EXCLUSIVE option in xtensa-config.h 429 430config FORCE_DMA_COPY_WHOLE_BLOCK 431 bool 432 default y if MT8195 433 default n 434 depends on HOST_PTABLE 435 help 436 The host component forces DMA to copy the block size to avoid 437 copying byte jitter between the components of the same pipeline. 438 439config SOF_STACK_SIZE 440 int "Primary core SOF stack size" 441 default 4096 442 help 443 Size of the primary core stack. This is the stack used by all 444 IPC calls. Increasing it allows deeper call stack on those IPC 445 and might be useful when creating more complex audio processing 446 components. 447 448config SECONDARY_CORE_DISABLING_TIMEOUT 449 int 450 default 5000 451 depends on MULTICORE 452 help 453 Timeout value (in ms) for secondary core to enter D3 state. 454 455if XTENSA 456 457config INCOHERENT 458 bool "Enable cached data access via the Coherent API" 459 default y if TIGERLAKE 460 default y if METEORLAKE 461 default n 462 help 463 The architecture is cache incoherent. i.e FW has to manually manage 464 cache coherency amongst objects that are used on multiple cores. 465 This setting should only be disabled for cache incoherent 466 architectures for testing without cached access to shared data. 467 468endif 469 470config LL_WATCHDOG 471 bool "Enable watchdog support in ll scheduler" 472 default n 473 depends on ACE 474 help 475 Select if you want to protect ll scheduler with a watchdog timer. 476 The watchdog is enabled after creating a ll thread for specified 477 core. When all tasks are finished, the watchdog will be disabled 478 before stopping the thread. Periodically, after each tick has been 479 handled, the watchdog counter is reseted. 480 481endmenu 482
