1# ARC options 2 3# Copyright (c) 2014, 2019 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "ARC Options" 7 depends on ARC 8 9config ARCH 10 default "arc" 11 12 13config CPU_ARCEM 14 bool 15 select ATOMIC_OPERATIONS_C 16 help 17 This option signifies the use of an ARC EM CPU 18 19config CPU_ARCHS 20 bool 21 select ATOMIC_OPERATIONS_BUILTIN 22 help 23 This option signifies the use of an ARC HS CPU 24 25 26choice 27 prompt "ARC Instruction Set" 28 default ISA_ARCV2 29 30config ISA_ARCV2 31 bool "ARC ISA v2" 32 select ARCH_HAS_STACK_PROTECTION if ARC_HAS_STACK_CHECKING || (ARC_MPU && ARC_MPU_VER !=2) 33 select ARCH_HAS_USERSPACE if ARC_MPU 34 select ARCH_HAS_SINGLE_THREAD_SUPPORT if !SMP 35 select USE_SWITCH 36 select USE_SWITCH_SUPPORTED 37 help 38 v2 ISA for the ARC-HS & ARC-EM cores 39 40config ISA_ARCV3 41 bool "ARC ISA v3" 42 select ARCH_HAS_SINGLE_THREAD_SUPPORT if !SMP 43 select USE_SWITCH 44 select USE_SWITCH_SUPPORTED 45 46endchoice 47 48if ISA_ARCV2 49 50config CPU_EM4 51 bool 52 select CPU_ARCEM 53 help 54 If y, the SoC uses an ARC EM4 CPU 55 56config CPU_EM4_DMIPS 57 bool 58 select CPU_ARCEM 59 help 60 If y, the SoC uses an ARC EM4 DMIPS CPU 61 62config CPU_EM4_FPUS 63 bool 64 select CPU_ARCEM 65 help 66 If y, the SoC uses an ARC EM4 DMIPS CPU with the single-precision 67 floating-point extension 68 69config CPU_EM4_FPUDA 70 bool 71 select CPU_ARCEM 72 help 73 If y, the SoC uses an ARC EM4 DMIPS CPU with single-precision 74 floating-point and double assist instructions 75 76config CPU_EM6 77 bool 78 select CPU_ARCEM 79 select CPU_HAS_DCACHE 80 select CPU_HAS_ICACHE 81 help 82 If y, the SoC uses an ARC EM6 CPU 83 84config CPU_HS3X 85 bool 86 select CPU_ARCHS 87 select CPU_HAS_DCACHE 88 select CPU_HAS_ICACHE 89 help 90 If y, the SoC uses an ARC HS3x CPU 91 92config CPU_HS4X 93 bool 94 select CPU_ARCHS 95 select CPU_HAS_DCACHE 96 select CPU_HAS_ICACHE 97 help 98 If y, the SoC uses an HS4X CPU 99 100endif #ISA_ARCV2 101 102if ISA_ARCV3 103 104config CPU_HS5X 105 bool 106 select CPU_ARCHS 107 select CPU_HAS_DCACHE 108 select CPU_HAS_ICACHE 109 help 110 If y, the SoC uses an ARC HS6x CPU 111 112config CPU_HS6X 113 bool 114 select CPU_ARCHS 115 select 64BIT 116 select CPU_HAS_DCACHE 117 select CPU_HAS_ICACHE 118 help 119 If y, the SoC uses an ARC HS6x CPU 120 121endif #ISA_ARCV3 122 123config FP_FPU_DA 124 bool 125 126menu "ARC CPU Options" 127 128config ARC_HAS_ZOL 129 bool 130 depends on ISA_ARCV2 131 default y 132 help 133 ARCv2 CPUs have ZOL hardware loop mechanism which the ARCv3 ISA drops. 134 Architecturally ZOL provides 135 - LPcc instruction 136 - LP_COUNT core reg 137 - LP_START, LP_END aux regs 138 Disabling this option removes usage of ZOL regs from code 139 140config NUM_IRQ_PRIO_LEVELS 141 int "Number of supported interrupt priority levels" 142 range 1 16 143 help 144 Interrupt priorities available will be 0 to NUM_IRQ_PRIO_LEVELS-1. 145 The minimum value is 1. 146 147 The BSP must provide a valid default for proper operation. 148 149config NUM_IRQS 150 int "Upper limit of interrupt numbers/IDs used" 151 range 17 256 152 help 153 Interrupts available will be 0 to NUM_IRQS-1. 154 The minimum value is 17 as the first 16 entries in the vector 155 table are for CPU exceptions. 156 157 The BSP must provide a valid default. This drives the size of the 158 vector table. 159 160config RGF_NUM_BANKS 161 int "Number of General Purpose Register Banks" 162 depends on ARC_FIRQ 163 depends on NUM_IRQ_PRIO_LEVELS > 1 164 range 1 2 165 default 2 166 help 167 The ARC CPU can be configured to have more than one register 168 bank. If fast interrupts are supported (FIRQ), the 2nd 169 register bank, in the set, will be used by FIRQ interrupts. 170 If fast interrupts are supported but there is only 1 171 register bank, the fast interrupt handler must save 172 and restore general purpose registers. 173 NOTE: it's required to have more than one interrupt priority level 174 to use second register bank - otherwise all interrupts will use 175 same register bank. Such configuration isn't supported in software 176 and it is not beneficial from the performance point of view. 177 178config ARC_FIRQ 179 bool "FIRQ enable" 180 depends on ISA_ARCV2 181 depends on NUM_IRQ_PRIO_LEVELS > 1 182 depends on !ARC_HAS_SECURE 183 default y 184 help 185 Fast interrupts are supported (FIRQ). If FIRQ enabled, for interrupts 186 with highest priority, status32 and pc will be saved in aux regs, 187 other regs will be saved according to the number of register bank; 188 If FIRQ is disabled, the handle of interrupts with highest priority 189 will be same with other interrupts. 190 NOTE: we don't allow the configuration with FIRQ enabled and only one 191 interrupt priority level (so all interrupts are FIRQ). Such 192 configuration isn't supported in software and it is not beneficial 193 from the performance point of view. 194 195config ARC_FIRQ_STACK 196 bool "Separate firq stack" 197 depends on ARC_FIRQ && RGF_NUM_BANKS > 1 198 help 199 Use separate stack for FIRQ handing. When the fast irq is also a direct 200 irq, this will get the minimal interrupt latency. 201 202config ARC_FIRQ_STACK_SIZE 203 int "FIRQ stack size" 204 depends on ARC_FIRQ_STACK 205 default 1024 206 help 207 The size of firq stack. 208 209config ARC_HAS_STACK_CHECKING 210 bool "ARC has STACK_CHECKING" 211 depends on ISA_ARCV2 212 default y 213 help 214 ARC is configured with STACK_CHECKING which is a mechanism for 215 checking stack accesses and raising an exception when a stack 216 overflow or underflow is detected. 217 218config ARC_CONNECT 219 bool "ARC has ARC connect" 220 select SCHED_IPI_SUPPORTED 221 help 222 ARC is configured with ARC CONNECT which is a hardware for connecting 223 multi cores. 224 225config ARC_STACK_CHECKING 226 bool 227 select NO_UNUSED_STACK_INSPECTION 228 help 229 Use ARC STACK_CHECKING to do stack protection 230 231config ARC_STACK_PROTECTION 232 bool 233 default y if HW_STACK_PROTECTION 234 select ARC_STACK_CHECKING if ARC_HAS_STACK_CHECKING 235 select MPU_STACK_GUARD if (!ARC_STACK_CHECKING && ARC_MPU && ARC_MPU_VER !=2) 236 select THREAD_STACK_INFO 237 help 238 This option enables either: 239 - The ARC stack checking, or 240 - the MPU-based stack guard 241 to cause a system fatal error 242 if the bounds of the current process stack are overflowed. 243 The two stack guard options are mutually exclusive. The 244 selection of the ARC stack checking is 245 prioritized over the MPU-based stack guard. 246 247config ARC_USE_UNALIGNED_MEM_ACCESS 248 bool "Unaligned access in HW" 249 default y if CPU_ARCHS 250 depends on (CPU_ARCEM && !ARC_HAS_SECURE) || CPU_ARCHS 251 help 252 ARC EM cores w/o secure shield 2+2 mode support might be configured 253 to support unaligned memory access which is then disabled by default. 254 Enable unaligned access in hardware and make software to use it. 255 256config ARC_CURRENT_THREAD_USE_NO_TLS 257 bool 258 select CURRENT_THREAD_USE_NO_TLS 259 default y if (RGF_NUM_BANKS > 1) || ("$(ZEPHYR_TOOLCHAIN_VARIANT)" = "arcmwdt") 260 help 261 Disable current Thread Local Storage for ARC. For cores with more then one 262 RGF_NUM_BANKS the parameter is disabled by-default because banks syncronization 263 requires significant time, and it slows down performance. 264 ARCMWDT works with tls pointer in different way then GCC. Optimized access to 265 TLS pointer via _current variable does not provide significant advantages 266 in case of MetaWare. 267 268config GEN_ISR_TABLES 269 default y 270 271config GEN_IRQ_START_VECTOR 272 default 16 273 274config HARVARD 275 bool "Harvard Architecture" 276 help 277 The ARC CPU can be configured to have two busses; 278 one for instruction fetching and another that serves as a data bus. 279 280config CODE_DENSITY 281 bool "Code Density Option" 282 help 283 Enable code density option to get better code density 284 285config ARC_HAS_ACCL_REGS 286 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)" 287 default y if CPU_HS3X || CPU_HS4X || CPU_HS5X || CPU_HS6X 288 help 289 Depending on the configuration, CPU can contain accumulator reg-pair 290 (also referred to as r58:r59). These can also be used by gcc as GPR so 291 kernel needs to save/restore per process 292 293config ARC_HAS_SECURE 294 bool "ARC has SecureShield" 295 depends on ISA_ARCV2 296 select CPU_HAS_TEE 297 select ARCH_HAS_TRUSTED_EXECUTION 298 help 299 This option is enabled when ARC core supports secure mode 300 301config SJLI_TABLE_SIZE 302 int "SJLI table size" 303 depends on ARC_SECURE_FIRMWARE 304 default 8 305 help 306 The size of sjli (Secure Jump and Link Indexed) table. The 307 code in normal mode call secure services in secure mode through 308 sjli instruction. 309 310config ARC_SECURE_FIRMWARE 311 bool "Generate Secure Firmware" 312 depends on ARC_HAS_SECURE 313 default y if TRUSTED_EXECUTION_SECURE 314 help 315 This option indicates that we are building a Zephyr image that 316 is intended to execute in secure mode. The option is only 317 applicable to ARC processors that implement the SecureShield. 318 319 This option enables Zephyr to include code that executes in 320 secure mode, as well as to exclude code that is designed to 321 execute only in normal mode. 322 323 Code executing in secure mode has access to both the secure 324 and normal resources of the ARC processors. 325 326config ARC_NORMAL_FIRMWARE 327 bool "Generate Normal Firmware" 328 depends on !ARC_SECURE_FIRMWARE 329 depends on ARC_HAS_SECURE 330 default y if TRUSTED_EXECUTION_NONSECURE 331 help 332 This option indicates that we are building a Zephyr image that 333 is intended to execute in normal mode. Execution of this 334 image is triggered by secure firmware that executes in secure 335 mode. The option is only applicable to ARC processors that 336 implement the SecureShield. 337 338 This option enables Zephyr to include code that executes in 339 normal mode only, as well as to exclude code that is 340 designed to execute only in secure mode. 341 342 Code executing in normal mode has no access to secure 343 resources of the ARC processors, and, therefore, it shall avoid 344 accessing them. 345 346source "arch/arc/core/dsp/Kconfig" 347 348menu "ARC MPU Options" 349depends on CPU_HAS_MPU 350 351config ARC_MPU_ENABLE 352 bool "Memory Protection Unit (MPU)" 353 select ARC_MPU 354 help 355 Enable MPU 356 357source "arch/arc/core/mpu/Kconfig" 358 359endmenu 360 361config DCACHE_LINE_SIZE 362 default 32 363 364config ARC_EXCEPTION_STACK_SIZE 365 int "ARC exception handling stack size" 366 default 768 if !64BIT 367 default 2048 if 64BIT 368 help 369 Size in bytes of exception handling stack which is at the top of 370 interrupt stack to get smaller memory footprint because exception 371 is not frequent. To reduce the impact on interrupt handling, 372 especially nested interrupt, it cannot be too large. 373 374endmenu 375 376config ARC_EARLY_SOC_INIT 377 bool "Make early stage SoC-specific initialization" 378 help 379 Call SoC per-core setup code on early stage initialization 380 (before C runtime initialization). Setup code is called in form of 381 soc_early_asm_init_percpu assembler macro. 382 383endmenu 384 385config MAIN_STACK_SIZE 386 default 4096 if 64BIT 387 388config ISR_STACK_SIZE 389 default 4096 if 64BIT 390 391config SYSTEM_WORKQUEUE_STACK_SIZE 392 default 4096 if 64BIT 393 394config IDLE_STACK_SIZE 395 default 1024 if 64BIT 396 397config IPM_CONSOLE_STACK_SIZE 398 default 2048 if 64BIT 399 400config TEST_EXTRA_STACK_SIZE 401 default 2048 if 64BIT 402 403config CMSIS_THREAD_MAX_STACK_SIZE 404 default 2048 if 64BIT 405 406config CMSIS_V2_THREAD_MAX_STACK_SIZE 407 default 2048 if 64BIT 408 409config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE 410 default 2048 if 64BIT 411
