1# x86 general configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6menu "X86 Architecture Options" 7 depends on X86 8 9config ARCH 10 default "x86" 11 12# 13# CPU Families - the SoC configuration should select the right one. 14# 15 16config CPU_ATOM 17 bool 18 select CPU_HAS_FPU 19 select ARCH_HAS_STACK_PROTECTION if X86_MMU 20 select ARCH_HAS_USERSPACE if X86_MMU 21 select X86_CPU_HAS_MMX 22 select X86_CPU_HAS_SSE 23 select X86_CPU_HAS_SSE2 24 select X86_CPU_HAS_SSE3 25 select CPU_HAS_DCACHE 26 help 27 This option signifies the use of a CPU from the Atom family. 28 29config CPU_APOLLO_LAKE 30 bool 31 select CPU_HAS_FPU 32 select ARCH_HAS_STACK_PROTECTION if X86_MMU 33 select ARCH_HAS_USERSPACE if X86_MMU 34 select X86_MMU 35 select X86_CPU_HAS_MMX 36 select X86_CPU_HAS_SSE 37 select X86_CPU_HAS_SSE2 38 select X86_CPU_HAS_SSE3 39 select X86_CPU_HAS_SSSE3 40 select X86_CPU_HAS_SSE41 41 select X86_CPU_HAS_SSE42 42 select CPU_HAS_DCACHE 43 help 44 This option signifies the use of a CPU from the Apollo Lake family. 45 46config CPU_LAKEMONT_VALUE 47 bool 48 select CPU_HAS_FPU 49 select ARCH_HAS_STACK_PROTECTION if X86_MMU 50 select ARCH_HAS_USERSPACE if X86_MMU 51 select CPU_HAS_DCACHE 52 help 53 This option signifies the use of a CPU from the Lakemont Value family. 54 55config CPU_LAKEMONT_PERF 56 bool 57 select CPU_HAS_FPU 58 select ARCH_HAS_STACK_PROTECTION if X86_MMU 59 select ARCH_HAS_USERSPACE if X86_MMU 60 select X86_CPU_HAS_MMX 61 select X86_CPU_HAS_SSE 62 select X86_CPU_HAS_SSE2 63 select X86_CPU_HAS_SSE3 64 select X86_CPU_HAS_SSSE3 65 select CPU_HAS_DCACHE 66 help 67 This option signifies the use of a CPU from the Lakemont Performance family. 68 69# 70# Configuration common to both IA32 and Intel64 sub-architectures. 71# 72 73config X86_64 74 bool "Run in 64-bit mode" 75 select 64BIT 76 select USE_SWITCH 77 select USE_SWITCH_SUPPORTED 78 select SCHED_IPI_SUPPORTED 79 select X86_MMU 80 select X86_CPU_HAS_MMX 81 select X86_CPU_HAS_SSE 82 select X86_CPU_HAS_SSE2 83 select X86_MMX 84 select X86_SSE 85 select X86_SSE2 86 select ARCH_HAS_DIRECTED_IPIS if !X2APIC 87 88menu "x86 Features" 89 90config X86_CPU_HAS_MMX 91 bool 92 93config X86_CPU_HAS_SSE 94 bool 95 96config X86_CPU_HAS_SSE2 97 bool 98 99config X86_CPU_HAS_SSE3 100 bool 101 102config X86_CPU_HAS_SSSE3 103 bool 104 105config X86_CPU_HAS_SSE41 106 bool 107 108config X86_CPU_HAS_SSE42 109 bool 110 111config X86_CPU_HAS_SSE4A 112 bool 113 114if FPU || X86_64 115 116config X86_MMX 117 bool "MMX Support" 118 depends on X86_CPU_HAS_MMX 119 help 120 This option enables MMX support, and the use of MMX registers 121 by threads. 122 123config X86_SSE 124 bool "SSE Support" 125 depends on X86_CPU_HAS_SSE 126 help 127 This option enables SSE support, and the use of SSE registers 128 by threads. 129 130config X86_SSE2 131 bool "SSE2 Support" 132 depends on X86_CPU_HAS_SSE2 133 select X86_SSE 134 help 135 This option enables SSE2 support. 136 137config X86_SSE3 138 bool "SSE3 Support" 139 depends on X86_CPU_HAS_SSE3 140 select X86_SSE 141 help 142 This option enables SSE3 support. 143 144config X86_SSSE3 145 bool "SSSE3 (Supplemental SSE3) Support" 146 depends on X86_CPU_HAS_SSSE3 147 select X86_SSE 148 help 149 This option enables Supplemental SSE3 support. 150 151config X86_SSE41 152 bool "SSE4.1 Support" 153 depends on X86_CPU_HAS_SSE41 154 select X86_SSE 155 help 156 This option enables SSE4.1 support. 157 158config X86_SSE42 159 bool "SSE4.2 Support" 160 depends on X86_CPU_HAS_SSE42 161 select X86_SSE 162 help 163 This option enables SSE4.2 support. 164 165config X86_SSE4A 166 bool "SSE4A Support" 167 depends on X86_CPU_HAS_SSE4A 168 select X86_SSE 169 help 170 This option enables SSE4A support. 171 172config X86_SSE_FP_MATH 173 bool "Compiler-generated SSEx instructions for floating point math" 174 depends on X86_SSE 175 help 176 This option allows the compiler to generate SSEx instructions for 177 performing floating point math. This can greatly improve performance 178 when exactly the same operations are to be performed on multiple 179 data objects; however, it can also significantly reduce performance 180 when preemptive task switches occur because of the larger register 181 set that must be saved and restored. 182 183 Disabling this option means that the compiler utilizes only the 184 x87 instruction set for floating point operations. 185 186endif # FPU || X86_64 187 188endmenu 189 190config SRAM_OFFSET 191 default 0x100000 if X86_PC_COMPATIBLE 192 help 193 A lot of x86 that resemble PCs have many reserved physical memory 194 regions within the first megabyte. Specify an offset from the 195 beginning of RAM to load the kernel in physical memory, avoiding these 196 regions. 197 198 Note that this does not include the "locore" which contains real mode 199 bootstrap code within the first 64K of physical memory. 200 201 This value normally need to be page-aligned. 202 203config KERNEL_VM_OFFSET 204 default 0x100000 if MMU 205 206config MAX_IRQ_LINES 207 int "Number of IRQ lines" 208 default 128 209 range 0 224 210 help 211 This option specifies the number of IRQ lines in the system. It 212 determines the size of the _irq_to_interrupt_vector_table, which 213 is used to track the association between vectors and IRQ numbers. 214 215config IRQ_OFFLOAD_VECTOR 216 int "IDT vector to use for IRQ offload" 217 default 33 218 range 32 $(UINT8_MAX) 219 depends on IRQ_OFFLOAD 220 221config PIC_DISABLE 222 bool "Disable PIC" 223 help 224 This option disables all interrupts on the legacy i8259 PICs at boot. 225 226choice 227 prompt "Reboot implementation" 228 depends on REBOOT 229 default REBOOT_RST_CNT 230 231 config REBOOT_RST_CNT 232 bool "Reboot via RST_CNT register" 233 help 234 Reboot via the RST_CNT register, going back to BIOS. 235endchoice 236 237config PCIE_MMIO_CFG 238 bool "Use MMIO PCI configuration space access" 239 select ACPI 240 help 241 Selects the use of the memory-mapped PCI Express Extended 242 Configuration Space instead of the traditional 0xCF8/0xCFC 243 IO Port registers. 244 245config KERNEL_VM_SIZE 246 default 0x40000000 if ACPI 247 248config X86_PC_COMPATIBLE 249 bool 250 default y 251 select ARCH_HAS_RESERVED_PAGE_FRAMES 252 select HAS_SRAM_OFFSET 253 help 254 Hidden option to signal building for PC-compatible platforms 255 with BIOS, ACPI, etc. 256 257config X86_MEMMAP 258 bool "Use memory map" 259 select ARCH_HAS_RESERVED_PAGE_FRAMES 260 help 261 Enable the use of memory map to identify regions of memory. 262 263 The memory map can be populated via Multiboot 264 (CONFIG_MULTIBOOT=y and CONFIG_MULTIBOOT_MEMMAP=y) or 265 can be manually defined via x86_memmap[]. 266 267config X86_MEMMAP_ENTRIES 268 int "Number of memory map entries" 269 depends on X86_MEMMAP 270 range 1 256 271 default 1 if !MULTIBOOT_MEMMAP 272 default 64 if MULTIBOOT_MEMMAP 273 help 274 Maximum number of memory regions to hold in the memory map. 275 276config MULTIBOOT 277 bool "Generate multiboot header" 278 depends on X86_PC_COMPATIBLE 279 default y 280 help 281 Embed a multiboot header in the output executable. This is used 282 by some boot loaders (e.g., GRUB) when loading Zephyr. It is safe 283 to leave this option on if you're not sure. It only expands the 284 text segment by 12-16 bytes and is typically ignored if not needed. 285 286if MULTIBOOT 287 288config MULTIBOOT_INFO 289 bool "Preserve multiboot information structure" 290 help 291 Multiboot passes a pointer to an information structure to the 292 kernel entry point. Some drivers (e.g., the multiboot framebuffer 293 display driver) need to refer to information in this structure, 294 and so set this option to preserve the data in a permanent location. 295 296config MULTIBOOT_MEMMAP 297 bool "Use multiboot memory map if provided" 298 select MULTIBOOT_INFO 299 select X86_MEMMAP 300 help 301 Use the multiboot memory map if the loader provides one. 302 303endif # MULTIBOOT 304 305config X86_VERY_EARLY_CONSOLE 306 bool "Support very early boot printk" 307 depends on PRINTK 308 help 309 Non-emulated X86 devices often require special hardware to attach 310 a debugger, which may not be easily available. This option adds a 311 very minimal serial driver which gets initialized at the very 312 beginning of z_cstart(), via arch_kernel_init(). This driver enables 313 printk to emit messages to the 16550 UART port 0 instance in device 314 tree. This mini-driver assumes I/O to the UART is done via ports. 315 316config X86_MMU 317 bool "Memory Management Unit" 318 select MMU 319 help 320 This options enables the memory management unit present in x86 321 and creates a set of page tables at boot time that is runtime- 322 mutable. 323 324config X86_COMMON_PAGE_TABLE 325 bool "Use a single page table for all threads" 326 default n 327 depends on USERSPACE 328 depends on !SMP 329 depends on !X86_KPTI 330 help 331 If this option is enabled, userspace memory domains will not have their 332 own page tables. Instead, context switching operations will modify 333 page tables in place. This is much slower, but uses much less RAM 334 for page tables. 335 336config X86_MAX_ADDITIONAL_MEM_DOMAINS 337 int "Maximum number of memory domains" 338 default 3 339 depends on X86_MMU && USERSPACE && !X86_COMMON_PAGE_TABLE 340 help 341 The initial page tables at boot are pre-allocated, and used for the 342 default memory domain. Instantiation of additional memory domains 343 if common page tables are in use requires a pool of free pinned 344 memory pages for constructing page tables. 345 346 Zephyr test cases assume 3 additional domains can be instantiated. 347 348config X86_EXTRA_PAGE_TABLE_PAGES 349 int "Reserve extra pages in page table" 350 default 1 if X86_PAE && (KERNEL_VM_BASE != SRAM_BASE_ADDRESS) 351 default 0 352 depends on X86_MMU 353 help 354 The whole page table is pre-allocated at build time and is 355 dependent on the range of address space. This allows reserving 356 extra pages (of size CONFIG_MMU_PAGE_SIZE) to the page table 357 so that gen_mmu.py can make use of these extra pages. 358 359 Says 0 unless absolutely sure that this is necessary. 360 361config X86_NO_MELTDOWN 362 bool 363 help 364 This hidden option should be set on a per-SOC basis to indicate that 365 a particular SOC is not vulnerable to the Meltdown CPU vulnerability, 366 as described in CVE-2017-5754. 367 368config X86_NO_SPECTRE_V1 369 bool 370 help 371 This hidden option should be set on a per-SOC basis to indicate that 372 a particular SOC is not vulnerable to the Spectre V1, V1.1, V1.2, and 373 swapgs CPU vulnerabilities as described in CVE-2017-5753, 374 CVE-2018-3693, and CVE-2019-1125. 375 376config X86_NO_SPECTRE_V2 377 bool 378 help 379 This hidden option should be set on a per-SOC basis to indicate that 380 a particular SOC is not vulnerable to the Spectre V2 CPU 381 vulnerability, as described in CVE-2017-5715. 382 383config X86_NO_SPECTRE_V4 384 bool 385 help 386 This hidden option should be set on a per-SOC basis to indicate that 387 a particular SOC is not vulnerable to the Spectre V4 CPU 388 vulnerability, as described in CVE-2018-3639. 389 390config X86_NO_LAZY_FP 391 bool 392 help 393 This hidden option should be set on a per-SOC basis to indicate 394 that a particular SOC is not vulnerable to the Lazy FP CPU 395 vulnerability, as described in CVE-2018-3665. 396 397config X86_NO_SPECULATIVE_VULNERABILITIES 398 bool 399 select X86_NO_MELTDOWN 400 select X86_NO_SPECTRE_V1 401 select X86_NO_SPECTRE_V2 402 select X86_NO_SPECTRE_V4 403 select X86_NO_LAZY_FP 404 help 405 This hidden option should be set on a per-SOC basis to indicate that 406 a particular SOC does not perform any kind of speculative execution, 407 or is a newer chip which is immune to the class of vulnerabilities 408 which exploit speculative execution side channel attacks. 409 410config X86_DISABLE_SSBD 411 bool "Disable Speculative Store Bypass" 412 depends on USERSPACE 413 default y if !X86_NO_SPECTRE_V4 414 help 415 This option will disable Speculative Store Bypass in order to 416 mitigate against certain kinds of side channel attacks. Quoting 417 the "Speculative Execution Side Channels" document, version 2.0: 418 419 When SSBD is set, loads will not execute speculatively 420 until the addresses of all older stores are known. This 421 ensure s that a load does not speculatively consume stale 422 data values due to bypassing an older store on the same 423 logical processor. 424 425 If enabled, this applies to all threads in the system. 426 427 Even if enabled, will have no effect on CPUs that do not 428 require this feature. 429 430config X86_ENABLE_EXTENDED_IBRS 431 bool "Extended IBRS" 432 depends on USERSPACE 433 default y if !X86_NO_SPECTRE_V2 434 help 435 This option will enable the Extended Indirect Branch Restricted 436 Speculation 'always on' feature. This mitigates Indirect Branch 437 Control vulnerabilities (aka Spectre V2). 438 439config X86_BOUNDS_CHECK_BYPASS_MITIGATION 440 bool 441 depends on USERSPACE 442 default y if !X86_NO_SPECTRE_V1 443 select BOUNDS_CHECK_BYPASS_MITIGATION 444 help 445 Hidden config to select arch-independent option to enable 446 Spectre V1 mitigations by default if the CPU is not known 447 to be immune to it. 448 449config X86_KPTI 450 bool "Kernel page table isolation" 451 default y 452 depends on USERSPACE 453 depends on !X86_NO_MELTDOWN 454 help 455 Implements kernel page table isolation to mitigate Meltdown exploits 456 to read Kernel RAM. Incurs a significant performance cost for 457 user thread interrupts and system calls, and significant footprint 458 increase for additional page tables and trampoline stacks. 459 460config X86_EFI 461 bool "EFI" 462 default y 463 depends on BUILD_OUTPUT_EFI 464 help 465 Enable EFI support. This means you build your image with zefi 466 support. See arch/x86/zefi/README.txt for more information. 467 468config X86_EFI_CONSOLE 469 bool 470 depends on X86_EFI && X86_64 && !X86_VERY_EARLY_CONSOLE 471 select EFI_CONSOLE 472 default y if !UART_CONSOLE 473 help 474 This enables the use of the UEFI console device as the 475 Zephyr printk handler. It requires that no interferences 476 with hardware used by the firmware console (e.g. a UART or 477 framebuffer) happens from Zephyr code, and that all memory 478 used by the firmware environment and its page tables be 479 separate and preserved. In general this is safe to assume, 480 but no automatic checking exists at runtime to verify. 481 Likewise be sure to disable any other console/printk 482 drivers! 483 484config PRIVILEGED_STACK_SIZE 485 # Must be multiple of CONFIG_MMU_PAGE_SIZE 486 default 4096 if X86_MMU 487 488source "arch/x86/core/Kconfig.ia32" 489source "arch/x86/core/Kconfig.intel64" 490 491endmenu 492
