1# SPDX-License-Identifier: Apache-2.0
2# Copyright (c) 2022, Intel Corporation
3
4config IPM_CALLBACK_ASYNC
5	bool "Deliver callbacks asynchronously"
6	default y if IPM_CAVS_HOST
7	help
8	  When selected, the driver supports "asynchronous" command
9	  delivery.  Commands will stay active after the ISR returns,
10	  until the application expressly "completes" the command
11	  later.
12
13config IPM_CAVS_HOST
14	bool "cAVS DSP/host communication"
15	select INTEL_ADSP_IPC
16	help
17	  Driver for host/DSP communication on intel_adsp devices
18
19if IPM_CAVS_HOST
20
21config IPM_CAVS_HOST_INBOX_OFFSET
22	hex "Byte offset of cAVS inbox window"
23	depends on INTEL_ADSP_IPC
24	default 0x6000
25	help
26	  Location of the host-writable inbox window within the
27	  HP_SRAM_RESERVE region.  This location must be synchronized
28	  with host driver and SOF source code (must match
29	  SRAM_INBOX_BASE).  Be careful.
30
31config IPM_CAVS_HOST_OUTBOX_OFFSET
32	hex "Byte offset of cAVS outbox memory"
33	depends on INTEL_ADSP_IPC
34	default 0x1000
35	help
36	  Location of the "outbox" region for SOF IPC3/4 message
37	  within the pre-existing window 0 (this is not the same as
38	  the HP_SRAM_RESERVE region used for INBOX_OFFSET).  This
39	  location must be synchronized with host driver and SOF
40	  source code (where it must equal SRAM_SW_REG_SIZE).  Be
41	  careful.
42
43config IPM_CAVS_HOST_REGWORD
44	bool "Store first 4 bytes in IPC register"
45	depends on INTEL_ADSP_IPC
46	help
47	  Protocol variant.  When true, the first four bytes of a
48	  message are passed in the cAVS IDR/TDR register pair instead
49	  of in the SRAM window.  Only available on cAVS 1.8+.
50
51endif # IPM_CAVS_HOST
52