1# Copyright 2019,2024 NXP
2# SPDX-License-Identifier: Apache-2.0
3
4config SOC_SERIES_LPC55XXX
5	select HAS_MCUX
6	select HAS_MCUX_FLEXCOMM
7	select HAS_MCUX_SYSCON
8	select HAS_MCUX_WWDT
9	select CPU_CORTEX_M_HAS_SYSTICK
10	select CPU_CORTEX_M_HAS_DWT
11	select SOC_RESET_HOOK
12
13config SOC_LPC55S06
14	select CPU_CORTEX_M33
15	select CPU_HAS_ARM_SAU
16	select CPU_HAS_ARM_MPU
17	select CPU_HAS_FPU
18	select ARMV8_M_DSP
19	select ARM_TRUSTZONE_M
20	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
21	select HAS_MCUX_RNG
22
23config SOC_LPC55S16
24	select CPU_CORTEX_M33
25	select CPU_HAS_ARM_SAU
26	select CPU_HAS_ARM_MPU
27	select CPU_HAS_FPU
28	select ARMV8_M_DSP
29	select ARM_TRUSTZONE_M
30	select HAS_MCUX_IAP if !TRUSTED_EXECUTION_NONSECURE
31	select HAS_MCUX_MCAN
32	select HAS_MCUX_RNG
33
34config SOC_LPC55S26
35	select CPU_CORTEX_M33
36	select CPU_HAS_ARM_SAU
37	select CPU_HAS_ARM_MPU
38	select CPU_HAS_FPU
39	select ARMV8_M_DSP
40	select HAS_MCUX_IAP
41	select HAS_MCUX_LPADC
42	select HAS_MCUX_LPC_DMA
43	select HAS_MCUX_RNG
44	select HAS_MCUX_SCTIMER
45
46config SOC_LPC55S28
47	select CPU_CORTEX_M33
48	select CPU_HAS_ARM_SAU
49	select CPU_HAS_ARM_MPU
50	select CPU_HAS_FPU
51	select ARMV8_M_DSP
52	select HAS_MCUX_IAP
53	select HAS_MCUX_LPADC
54	select HAS_MCUX_LPC_DMA
55	select HAS_MCUX_RNG
56	select HAS_MCUX_SCTIMER
57
58config SOC_LPC55S36
59	select CPU_CORTEX_M33
60	select CPU_HAS_ARM_SAU
61	select CPU_HAS_ARM_MPU
62	select CPU_HAS_FPU
63	select ARMV8_M_DSP
64	select ARM_TRUSTZONE_M
65	select HAS_MCUX_MCAN
66	select HAS_MCUX_PWM
67
68config SOC_LPC55S69
69	select CPU_CORTEX_M33
70
71config SOC_LPC55S69_CPU0
72	select CPU_HAS_ARM_SAU
73	select CPU_HAS_ARM_MPU
74	select CPU_HAS_FPU
75	select ARMV8_M_DSP
76	select ARM_TRUSTZONE_M
77	select HAS_MCUX_IAP
78	select HAS_MCUX_LPADC
79	select HAS_MCUX_LPC_DMA
80	select HAS_MCUX_USB_LPCIP3511
81	select HAS_MCUX_CTIMER
82	select HAS_MCUX_SCTIMER
83	select HAS_MCUX_RNG
84	select HAS_PM
85
86if SOC_SERIES_LPC55XXX
87
88config INIT_PLL0
89	bool "Initialize PLL0"
90
91config INIT_PLL1
92	bool "Initialize PLL1"
93	default "y"
94	depends on !(SOC_LPC55S06 || FLASH || BUILD_WITH_TFM)
95	help
96	  In the LPC55XXX Family, this is currently being used to set the
97	  core clock value at it's highest frequency which clocks at 150MHz.
98	  Note that flash programming operations are limited to 100MHz, and
99	  this PLL should not be used as the core clock in those cases.
100
101config SECOND_CORE_MCUX
102	bool "LPC55xxx's second core"
103
104config SECOND_CORE_BOOT_ADDRESS_MCUX
105	depends on SECOND_CORE_MCUX
106	hex "Address the second core will boot at"
107	default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_CODE_CPU1_PARTITION))
108	help
109	  This is the address the second core will boot from.
110
111config LPC55XXX_SRAM_CLOCKS
112	bool "CLock LPC SRAM banks"
113
114config LPC55XXX_USB_RAM
115	bool
116
117if SOC_LPC55S69
118
119config SOC_FLASH_MCUX
120	bool
121
122endif # SOC_LPC55S69
123
124config MCUX_CORE_SUFFIX
125	default "_cm33_core0" if SOC_LPC55S69_CPU0
126	default "_cm33_core1" if SOC_LPC55S69_CPU1
127
128endif # SOC_SERIES_LPC55XXX
129