1# Copyright 2024 NXP
2# Copyright (c) 2023 Google LLC.
3# SPDX-License-Identifier: Apache-2.0
4
5config SOC_MIMXRT595S_CM33
6	select CPU_CORTEX_M33
7	select CLOCK_CONTROL
8	select CPU_CORTEX_M_HAS_DWT
9	select ARM
10	select HAS_PM
11	select HAS_POWEROFF
12	select CPU_HAS_ARM_SAU
13	select CPU_HAS_ARM_MPU
14	select CPU_HAS_FPU
15	select SOC_RESET_HOOK
16	select ARMV8_M_DSP
17	select ARM_TRUSTZONE_M
18	select CPU_CORTEX_M_HAS_SYSTICK
19	select HAS_MCUX
20	select HAS_MCUX_SYSCON
21	select HAS_MCUX_FLEXCOMM
22	select HAS_MCUX_FLEXSPI
23	select HAS_MCUX_CACHE
24	select HAS_MCUX_LPC_DMA
25	select HAS_MCUX_LPADC
26	select HAS_MCUX_OS_TIMER
27	select HAS_MCUX_LPC_RTC
28	select HAS_MCUX_TRNG
29	select HAS_MCUX_SCTIMER
30	select HAS_MCUX_USDHC1
31	select HAS_MCUX_USDHC2
32	select HAS_MCUX_USB_LPCIP3511
33	select HAS_MCUX_CTIMER
34	select SOC_EARLY_INIT_HOOK
35
36config SOC_MIMXRT595S_F1
37	select XTENSA
38	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
39	select XTENSA_RESET_VECTOR
40	select XTENSA_USE_CORE_CRT1
41
42if SOC_SERIES_IMXRT5XX
43
44if NXP_IMXRT_BOOT_HEADER
45
46config IMAGE_VECTOR_TABLE_OFFSET
47	default 0x1000
48
49endif # NXP_IMXRT_BOOT_HEADER
50
51config IMXRT5XX_CODE_CACHE
52	bool "Code cache"
53	default y
54	help
55	  Enable code cache for FlexSPI region at boot. If this Kconfig is
56	  cleared, the CACHE64 controller will be disabled during SOC init
57
58choice FLEXCOMM0_CLK_SRC
59	prompt "Clock source for Flexcomm0"
60	default FLEXCOMM0_CLK_SRC_FRG
61
62config FLEXCOMM0_CLK_SRC_FRG
63	bool "FRG is source of Flexcomm0 clock"
64
65config FLEXCOMM0_CLK_SRC_FRO
66	bool "FRO_DIV4 is source of Flexcomm0 clock"
67
68endchoice
69
70choice MIPI_DPHY_CLK_SRC
71	prompt "Clock source for MIPI DPHY"
72	default MIPI_DPHY_CLK_SRC_AUX1_PLL
73
74config MIPI_DPHY_CLK_SRC_AUX1_PLL
75	bool "AUX1_PLL is source of MIPI_DPHY clock"
76
77config MIPI_DPHY_CLK_SRC_FRO
78	bool "FRO 192/96M is source of MIPI_DPHY clock"
79
80endchoice
81
82config MCUX_CORE_SUFFIX
83	default "_cm33" if SOC_MIMXRT595S_CM33
84	default "_dsp" if SOC_MIMXRT595S_F1
85
86endif # SOC_SERIES_IMXRT5XX
87