1# Copyright (c) 2024-2025 Espressif Systems (Shanghai) Co., Ltd. 2# SPDX-License-Identifier: Apache-2.0 3 4if SOC_FAMILY_ESPRESSIF_ESP32 5 6if MCUBOOT 7 8config EFUSE_VIRTUAL_OFFSET 9 hex 10 default 0x250000 if SOC_SERIES_ESP32 11 default 0x250000 if SOC_SERIES_ESP32S2 12 default 0x250000 if SOC_SERIES_ESP32S3 13 default 0x250000 if SOC_SERIES_ESP32C3 14 default 0x250000 if SOC_SERIES_ESP32C6 15 16config EFUSE_VIRTUAL_SIZE 17 hex 18 default 0x2000 if SOC_SERIES_ESP32 19 default 0x2000 if SOC_SERIES_ESP32S2 20 default 0x2000 if SOC_SERIES_ESP32S3 21 default 0x2000 if SOC_SERIES_ESP32C3 22 default 0x2000 if SOC_SERIES_ESP32C6 23 24config EFUSE_MAX_BLK_LEN 25 int 26 default 192 if SOC_SERIES_ESP32 27 default 256 if SOC_SERIES_ESP32S2 28 default 256 if SOC_SERIES_ESP32S3 29 default 256 if SOC_SERIES_ESP32C3 30 default 256 if SOC_SERIES_ESP32C6 31 32endif # MCUBOOT 33 34config BOOTLOADER_LOG_LEVEL 35 int 36 default 3 37 38config LOG_TIMESTAMP_SOURCE_RTOS 39 bool 40 default y 41 42config ESP32_DPORT_DIS_INTERRUPT_LVL 43 int 44 default 5 if SOC_SERIES_ESP32 || SOC_SERIES_ESP32S3 45 46config FREERTOS_UNICORE 47 bool 48 default y if !SMP 49 50config ESP_SYSTEM_SINGLE_CORE_MODE 51 bool 52 default y if SOC_SERIES_ESP32 53 54config IDF_FIRMWARE_CHIP_ID 55 hex 56 default 0x0000 if SOC_SERIES_ESP32 57 default 0x0002 if SOC_SERIES_ESP32S2 58 default 0x0009 if SOC_SERIES_ESP32S3 59 default 0x000C if SOC_SERIES_ESP32C2 60 default 0x0005 if SOC_SERIES_ESP32C3 61 default 0x000D if SOC_SERIES_ESP32C6 62 63config SPIRAM_ALLOW_BSS_SEG_EXTERNAL_MEMORY 64 bool 65 default y if SOC_SERIES_ESP32 66 default y if SOC_SERIES_ESP32S2 67 default y if SOC_SERIES_ESP32S3 68 69config SPIRAM_ALLOW_NOINIT_SEG_EXTERNAL_MEMORY 70 bool 71 default y if SOC_SERIES_ESP32 72 default y if SOC_SERIES_ESP32S2 73 default y if SOC_SERIES_ESP32S3 74 75config IDF_TARGET_ESP32 76 bool 77 default y if SOC_SERIES_ESP32 78 79config IDF_TARGET_ESP32S2 80 bool 81 default y if SOC_SERIES_ESP32S2 82 83config IDF_TARGET_ESP32S3 84 bool 85 default y if SOC_SERIES_ESP32S3 86 87config IDF_TARGET_ESP32C2 88 bool 89 default y if SOC_SERIES_ESP32C2 90 91config IDF_TARGET_ESP32C3 92 bool 93 default y if SOC_SERIES_ESP32C3 94 95config IDF_TARGET_ESP32C6 96 bool 97 default y if SOC_SERIES_ESP32C6 98 99menu "Sleep config" 100 101config ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY 102 int "Extra delay (in us) after flash powerdown sleep wakeup to wait flash ready" 103 default 2000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 104 default 0 105 range 0 5000 106 help 107 When the chip exits sleep, the CPU and the flash chip are powered on at the same time. 108 CPU will run rom code (deepsleep) or ram code (lightsleep) first, and then load or execute 109 code from flash. 110 111 Some flash chips need sufficient time to pass between power on and first read operation. 112 By default, without any extra delay, this time is approximately 900us, although 113 some flash chip types need more than that. 114 115 (!!! Please adjust this value according to the Data Sheet of SPI Flash used in your project.) 116 In Flash Data Sheet, the parameters that define the Flash ready timing after power-up (minimum 117 time from Vcc(min) to CS active) usually named tVSL in ELECTRICAL CHARACTERISTICS chapter, 118 and the configuration value here should be: 119 ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY = tVSL - 900 120 121 For esp32 and esp32s3, the default extra delay is set to 2000us. When optimizing startup time 122 for applications which require it, this value may be reduced. 123 124 If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset 125 on esp32, or triggered RTC_WDT/LP_WDT after lightsleep wakeup, try increasing this value. 126 (For esp32, the delay will be executed in both deep sleep and light sleep wake up flow. 127 For chips after esp32, the delay will be executed only in light sleep flow, the delay 128 controlled by the EFUSE_FLASH_TPUW in ROM will be executed in deepsleep wake up flow.) 129 130endmenu # Sleep config 131 132endif # SOC_FAMILY_ESPRESSIF_ESP32 133