1# Copyright (c) 2020 ITE Corporation. All Rights Reserved. 2# SPDX-License-Identifier: Apache-2.0 3 4config I2C_ITE_IT8XXX2 5 bool "ITE IT8XXX2 I2C driver" 6 default y 7 depends on DT_HAS_ITE_IT8XXX2_I2C_ENABLED 8 select PINCTRL 9 help 10 Enable I2C support on it8xxx2_evb. 11 Supported Speeds: 100kHz, 400kHz and 1MHz. 12 This driver supports repeated start. 13 14if I2C_ITE_IT8XXX2 15 16config I2C_IT8XXX2_FIFO_MODE 17 bool "IT8XXX2 I2C FIFO mode" 18 default y 19 help 20 This is an option to enable FIFO mode which can reduce 21 the time between each byte to improve the I2C bus clock 22 stretching during I2C transaction. 23 The I2C controller supports two 32-bytes FIFOs, 24 FIFO1 supports channel A. FIFO2 supports channel B. 25 I2C FIFO mode of it8xxx2 can support I2C APIs including: 26 i2c_write(), i2c_read(), i2c_burst_read. 27 28endif # I2C_ITE_IT8XXX2 29 30config I2C_ITE_ENHANCE 31 bool "ITE IT8XXX2 I2C enhance driver" 32 default y 33 depends on DT_HAS_ITE_ENHANCE_I2C_ENABLED 34 select PINCTRL 35 help 36 This option can enable the enhance I2C 37 of IT8XXX2 and support three channels. 38 39if I2C_ITE_ENHANCE 40 41config I2C_IT8XXX2_CQ_MODE 42 bool "IT8XXX2 I2C command queue mode" 43 default y 44 select SOC_IT8XXX2_CPU_IDLE_GATING 45 help 46 This is an option to enable command queue mode which can 47 reduce the time between each byte to improve the I2C bus 48 clock stretching during I2C transaction. 49 I2C command queue mode of it8xxx2 can support I2C APIs 50 including: i2c_write(), i2c_read(), i2c_burst_read. 51 52config I2C_CQ_MODE_MAX_PAYLOAD_SIZE 53 int "It is allowed to configure the size up to 2K bytes." 54 range 32 2048 55 default 64 56 help 57 This is the command queue mode payload size which size 58 up to 2k bytes. 59 60endif # I2C_ITE_ENHANCE 61 62if I2C_TARGET 63 64config I2C_TARGET_IT8XXX2_MAX_BUF_SIZE 65 int "It is allowed to configure the size up to 2044 bytes." 66 range 4 2044 67 default 256 68 69config I2C_TARGET_BUFFER_MODE 70 default y 71 72endif # I2C_TARGET 73