1# SPDX-License-Identifier: BSD-3-Clause 2 3menu "Platform" 4 5choice 6 prompt "Platform" 7 default APOLLOLAKE 8 9config BAYTRAIL 10 bool "Build for Baytrail" 11 select HOST_PTABLE 12 select DW_DMA_AGGREGATED_IRQ 13 select DMA_SUSPEND_DRAIN 14 select DMA_FIFO_PARTITION 15 select DW 16 select DW_DMA 17 select XT_HAVE_RESET_VECTOR_ROM 18 select XT_INTERRUPT_LEVEL_1 19 select XT_INTERRUPT_LEVEL_4 20 select XT_INTERRUPT_LEVEL_5 21 select INTEL 22 select SCHEDULE_DMA_MULTI_CHANNEL 23 help 24 Select if your target platform is Baytrail-compatible 25 26config CHERRYTRAIL 27 bool "Build for Cherrytrail" 28 select HOST_PTABLE 29 select DW_DMA_AGGREGATED_IRQ 30 select DMA_SUSPEND_DRAIN 31 select DMA_FIFO_PARTITION 32 select DW 33 select DW_DMA 34 select XT_HAVE_RESET_VECTOR_ROM 35 select XT_INTERRUPT_LEVEL_1 36 select XT_INTERRUPT_LEVEL_4 37 select XT_INTERRUPT_LEVEL_5 38 select INTEL 39 select SCHEDULE_DMA_MULTI_CHANNEL 40 help 41 Select if your target platform is Cherrytrail-compatible 42 43config HASWELL 44 bool "Build for Haswell" 45 select HOST_PTABLE 46 select DW_DMA_AGGREGATED_IRQ 47 select DW 48 select DW_DMA 49 select XT_HAVE_RESET_VECTOR_ROM 50 select XT_INTERRUPT_LEVEL_1 51 select XT_INTERRUPT_LEVEL_2 52 select XT_INTERRUPT_LEVEL_3 53 select INTEL 54 select SCHEDULE_DMA_MULTI_CHANNEL 55 help 56 Select if your target platform is Haswell-compatible 57 58config BROADWELL 59 bool "Build for Broadwell" 60 select HOST_PTABLE 61 select DW_DMA_AGGREGATED_IRQ 62 select DW 63 select DW_DMA 64 select XT_HAVE_RESET_VECTOR_ROM 65 select XT_INTERRUPT_LEVEL_1 66 select XT_INTERRUPT_LEVEL_2 67 select XT_INTERRUPT_LEVEL_3 68 select INTEL 69 select SCHEDULE_DMA_MULTI_CHANNEL 70 help 71 Select if your target platform is Broadwell-compatible 72 73config APOLLOLAKE 74 bool "Build for Apollolake" 75 select XT_BOOT_LOADER 76 select XT_IRQ_MAP 77 select DMA_GW 78 select DW 79 select DW_DMA 80 select MEM_WND 81 select DMA_HW_LLI 82 select DMA_FIFO_PARTITION 83 select CAVS 84 select CAVS_VERSION_1_5 85 help 86 Select if your target platform is Apollolake-compatible 87 88config CANNONLAKE 89 bool "Build for Cannonlake" 90 select XT_BOOT_LOADER 91 select XT_IRQ_MAP 92 select DMA_GW 93 select DW 94 select DW_DMA 95 select MEM_WND 96 select DMA_HW_LLI 97 select DW_DMA_AGGREGATED_IRQ 98 select DMA_FIFO_PARTITION 99 select CAVS 100 select CAVS_VERSION_1_8 101 select XT_WAITI_DELAY 102 select CAVS_USE_LPRO_IN_WAITI 103 help 104 Select if your target platform is Cannonlake-compatible 105 106config SUECREEK 107 bool "Build for Suecreek" 108 select XT_BOOT_LOADER 109 select XT_IRQ_MAP 110 select DW 111 select DW_DMA 112 select DW_SPI 113 select INTEL_IOMUX 114 select DW_GPIO 115 select DMA_HW_LLI 116 select DW_DMA_AGGREGATED_IRQ 117 select DMA_FIFO_PARTITION 118 select CAVS 119 select CAVS_VERSION_2_0 120 select XT_WAITI_DELAY 121 select CAVS_USE_LPRO_IN_WAITI 122 help 123 Select if your target platform is Suecreek-compatible 124 125config ICELAKE 126 bool "Build for Icelake" 127 select XT_BOOT_LOADER 128 select XT_IRQ_MAP 129 select DMA_GW 130 select DW 131 select DW_DMA 132 select MEM_WND 133 select DMA_HW_LLI 134 select DW_DMA_AGGREGATED_IRQ 135 select DMA_FIFO_PARTITION 136 select CAVS 137 select CAVS_VERSION_2_0 138 select XT_WAITI_DELAY 139 select CAVS_USE_LPRO_IN_WAITI 140 help 141 Select if your target platform is Icelake-compatible 142 143config TIGERLAKE 144 bool "Build for Tigerlake" 145 select XT_BOOT_LOADER 146 select XT_IRQ_MAP 147 select DMA_GW 148 select DW 149 select DW_DMA 150 select MEM_WND 151 select DMA_HW_LLI 152 select DW_DMA_AGGREGATED_IRQ 153 select DMA_FIFO_PARTITION 154 select CAVS 155 select CAVS_VERSION_2_5 156 select XT_WAITI_DELAY 157 select NO_SECONDARY_CORE_ROM 158 select CAVS_USE_LPRO_IN_WAITI 159 help 160 Select if your target platform is Tigerlake-compatible 161 162config LIBRARY 163 bool "Build Library" 164 help 165 Select if you want to build a library. 166 It is generic/mock configuration not tied to some specific platform. 167 Library builds are not intended to be run on DSP, but to be used by 168 user-space applications. 169 170config IMX8 171 bool "Build for NXP i.MX8" 172 select XT_HAVE_RESET_VECTOR_ROM 173 select XT_INTERRUPT_LEVEL_1 174 select XT_INTERRUPT_LEVEL_2 175 select XT_INTERRUPT_LEVEL_3 176 select HOST_PTABLE 177 select DUMMY_DMA 178 select XT_WAITI_DELAY 179 select IMX 180 select IMX_EDMA 181 select IMX_ESAI 182 select SCHEDULE_DMA_MULTI_CHANNEL 183 select IMX_INTERRUPT_IRQSTEER 184 help 185 Select if your target platform is imx8-compatible 186 187config IMX8X 188 bool "Build for NXP i.MX8X" 189 select XT_HAVE_RESET_VECTOR_ROM 190 select XT_INTERRUPT_LEVEL_1 191 select XT_INTERRUPT_LEVEL_2 192 select XT_INTERRUPT_LEVEL_3 193 select HOST_PTABLE 194 select DUMMY_DMA 195 select XT_WAITI_DELAY 196 select IMX 197 select IMX_EDMA 198 select IMX_ESAI 199 select SCHEDULE_DMA_MULTI_CHANNEL 200 select IMX_INTERRUPT_IRQSTEER 201 help 202 Select if your target platform is imx8x-compatible 203 204config IMX8M 205 bool "Build for NXP i.MX8M" 206 select XT_HAVE_RESET_VECTOR_ROM 207 select XT_INTERRUPT_LEVEL_1 208 select XT_INTERRUPT_LEVEL_2 209 select XT_INTERRUPT_LEVEL_3 210 select HOST_PTABLE 211 select DUMMY_DMA 212 select XT_WAITI_DELAY 213 select IMX 214 select IMX_SDMA 215 select SCHEDULE_DMA_MULTI_CHANNEL 216 select IMX_INTERRUPT_IRQSTEER 217 help 218 Select if your target platform is imx8m-compatible 219 220config IMX8ULP 221 bool "Build for NXP i.MX8ULP" 222 select XT_HAVE_RESET_VECTOR_ROM 223 select XT_INTERRUPT_LEVEL_1 224 select XT_INTERRUPT_LEVEL_2 225 select XT_INTERRUPT_LEVEL_3 226 select HOST_PTABLE 227 select DUMMY_DMA 228 select XT_WAITI_DELAY 229 select IMX 230 select IMX_EDMA 231 select IMX_INTERRUPT_GENERIC 232 select SCHEDULE_DMA_MULTI_CHANNEL 233 help 234 Select if your target platform is imx8ulp-compatible. 235 imx.8ulp support dsp. 236 237config RENOIR 238 bool "Build for Renoir" 239 select XT_INTERRUPT_LEVEL_5 240 select XT_INTERRUPT_LEVEL_3 241 select XT_INTERRUPT_LEVEL_1 242 select XT_INTERRUPT_LEVEL_4 243 select XT_WAITI_DELAY 244 select SCHEDULE_DMA_MULTI_CHANNEL 245 help 246 Select if your target platform is renoir-compatible 247 248endchoice 249 250config MAX_CORE_COUNT 251 int 252 default 2 if APOLLOLAKE 253 default 4 if ICELAKE || CANNONLAKE || SUECREEK || TIGERLAKE 254 default 1 255 help 256 Maximum number of cores per configuration 257 258config CORE_COUNT 259 int "Number of cores" 260 default MP_NUM_CPUS if KERNEL_BIN_NAME = "zephyr" 261 default MAX_CORE_COUNT 262 range 1 MAX_CORE_COUNT 263 help 264 Number of used cores 265 Lowering available core count could result in lower power consumption 266 267config MULTICORE 268 bool 269 default CORE_COUNT > 1 270 help 271 Indicates that architecture uses multiple cores 272 273config INTEL 274 bool 275 default n 276 help 277 This has to be selected for every Intel platform. 278 It enables Intel platforms-specific features. 279 280config HOST 281 bool 282 default n 283 help 284 This has to be selected for building linux test targets. 285 286config IMX 287 bool 288 default n 289 select COMPILER_WORKAROUND_CACHE_ATTR 290 help 291 This has to be selected for every i.MX NXP platform. 292 It enables NXP platforms-specific features. 293 294config CAVS 295 bool 296 default n 297 select INTEL 298 select XT_INTERRUPT_LEVEL_2 299 select XT_INTERRUPT_LEVEL_5 300 select INTEL_HDA 301 select INTEL_MN 302 select WAKEUP_HOOK 303 select SCHEDULE_DMA_SINGLE_CHANNEL 304 305config CAVS_VERSION_1_5 306 depends on CAVS 307 bool 308 help 309 Select for CAVS version 1.5 310 311config CAVS_VERSION_1_8 312 depends on CAVS && !CAVS_VERSION_1_5 313 bool 314 help 315 Select for CAVS version 1.8 316 317config CAVS_VERSION_2_0 318 depends on CAVS && !CAVS_VERSION_1_5 && !CAVS_VERSION_1_8 319 bool 320 help 321 Select for CAVS version 2.0 322 323config CAVS_VERSION_2_5 324 depends on CAVS && !CAVS_VERSION_1_5 && !CAVS_VERSION_1_8 \ 325 && !CAVS_VERSION_2_0 326 bool 327 help 328 Select for CAVS version 2.5 329 330config CONFIG_CHERRYTRAIL_EXTRA_DW_DMA 331 bool "Support Cherrytrail 3rd DMAC" 332 default n if !CHERRYTRAIL 333 depends on CHERRYTRAIL 334 help 335 Select if you need support for all 3 DMACs versus the default 2 used 336 in baytrail. 337 338config HP_MEMORY_BANKS 339 int "HP memory banks count" 340 depends on CAVS 341 default 8 342 help 343 Available memory banks count for High Performance memory 344 Lowering available banks could result in lower power consumption 345 Too low count should result in unresponsive/crashing image due to not 346 enough space for FW base image 347 Banks are 64kb in size. 348 349config LP_MEMORY_BANKS 350 int "LP memory banks count" 351 depends on CAVS 352 default 0 353 help 354 Available memory banks count for Low Power memory. 355 It can be used to turn ON/OFF LPSRAM bank/s. 356 Firmware will turn on only as many banks as are defined here. 357 358config LP_SRAM 359 bool 360 default LP_MEMORY_BANKS > 0 361 help 362 Indicates that platform uses LPSRAM. 363 364config L1_DRAM 365 bool "L1 DRAM memory support" 366 default n 367 help 368 Indicates that platform does support L1 DATA RAM. 369 370config L1_DRAM_MEMORY_BANKS 371 int "L1 DRAM memory banks count" 372 depends on L1_DRAM 373 default 0 374 help 375 Available memory banks count for L1 DATA RAM. 376 It can be used to turn ON/OFF L1 DRAM bank/s. 377 Firmware will turn on only as many banks as specified. 378 379config L1_DRAM_MEMORY_BANK_SIZE 380 int "L1 DRAM memory bank size" 381 depends on L1_DRAM 382 default 0 383 help 384 Specifies DRAM block size. 385 It can be used to calculate DRAM size. 386 387config CAVS_LPS 388 bool "Intel cAVS Low Power Sequencer for Power Management" 389 depends on CAVS 390 default n 391 help 392 Select this to enable Intel cAVS Low Power Sequencer. 393 This option is required to support S0ix/D0ix mode 394 on cAVS platforms. 395 396config CAVS_LPRO_ONLY 397 bool "Use low power ring oscillator always" 398 default n 399 depends on CAVS && !CAVS_VERSION_1_5 400 help 401 Select if you want to use only the 120MHz LPRO as the DSP clock source. 402 This option is for debugging only at the moment, choose n if unclear. 403 404config CAVS_USE_LPRO_IN_WAITI 405 bool "Use low power ring oscillator in WFI" 406 default n 407 depends on CAVS && !CAVS_LPRO_ONLY 408 help 409 Select if we want to use LPRO clock in waiti. 410 After waiti exit clock source will be restored. 411 Choose n if unclear. 412 413# TODO: it should just take manifest version and offsets 414config RIMAGE_SIGNING_SCHEMA 415 string "Rimage firmware signing schema name" 416 default "byt" if BAYTRAIL 417 default "cht" if CHERRYTRAIL 418 default "hsw" if HASWELL 419 default "bdw" if BROADWELL 420 default "apl" if APOLLOLAKE 421 default "cnl" if CANNONLAKE 422 default "sue" if SUECREEK 423 default "icl" if ICELAKE 424 default "tgl" if TIGERLAKE 425 default "imx8" if IMX8 426 default "imx8x" if IMX8X 427 default "imx8m" if IMX8M 428 default "imx8ulp" if IMX8ULP 429 default "rn" if RENOIR 430 default "" 431 help 432 Signing schema name used by rimage to decide how to build final binary 433 434config SYSTICK_PERIOD 435 int "System tick period in microseconds" 436 default 1000 437 help 438 Defines platform system tick period. It is used 439 as a timeout check value for system agent. 440 Value should be provided in microseconds. 441 442config HAVE_AGENT 443 bool "Enable system agent" 444 default y 445 help 446 Enables system agent. It can be disabled on systems 447 which are still unstable and cannot assure that 448 system agent will always execute on time or systems 449 with DMA based scheduling, where asynchronous interrupts 450 can potentially starve the agent. 451 452config AGENT_PANIC_ON_DELAY 453 bool "Enable system agent time verification panic" 454 default n 455 depends on HAVE_AGENT 456 help 457 Enables system agent time verification panic. 458 If scheduler timing verification fails, SA will 459 call a DSP panic. 460 461endmenu 462
