1# NPCX Flash driver configuration options
2
3# Copyright (c) 2023 Nuvoton Technology Corporation.
4# SPDX-License-Identifier: Apache-2.0
5
6config FLASH_NPCX_FIU_QSPI
7	bool "Nuvoton NPCX QSPI Bus Flash driver"
8	default y
9	depends on DT_HAS_NUVOTON_NPCX_FIU_QSPI_ENABLED
10	select PINCTRL
11	help
12	  This option enables the QSPI Bus Flash driver for NPCX family of
13	  processors.
14
15config FLASH_NPCX_FIU_NOR
16	bool "Nuvoton NPCX embedded controller (EC) QSPI NOR Flash driver"
17	default y
18	depends on DT_HAS_NUVOTON_NPCX_FIU_NOR_ENABLED
19	depends on FLASH_NPCX_FIU_QSPI
20	select FLASH_HAS_DRIVER_ENABLED
21	select FLASH_HAS_PAGE_LAYOUT
22	select FLASH_HAS_EXPLICIT_ERASE
23	select FLASH_JESD216
24	select FLASH_HAS_EX_OP
25	help
26	  This option enables the QSPI NOR Flash driver for NPCX family of
27	  processors.
28
29if FLASH_NPCX_FIU_QSPI
30
31config FLASH_NPCX_FIU_NOR_INIT
32	bool "QSPI NOR flash feature during driver initialization"
33	default y
34	depends on FLASH_NPCX_FIU_NOR
35	help
36	  This option enables the QSPI NOR Flash features such as Quad-Enable,
37	  4-byte address support and so on during driver initialization. Disable
38	  it if QSPI NOR devices are not ready during driver initialization.
39
40config FLASH_NPCX_FIU_DRA_V1
41	bool "Direct Read Access version 1 support"
42	default y if SOC_SERIES_NPCX9
43	help
44	  This option enables DRA V1 support.
45
46config FLASH_NPCX_FIU_DRA_V2
47	bool "Direct Read Access version 2 support"
48	default y if SOC_SERIES_NPCX4
49	help
50	  This option enables DRA V1 support.
51
52config FLASH_NPCX_FIU_SUPP_DRA_4B_ADDR
53	bool "4 byte address support in Direct Read Access mode"
54	default y if FLASH_NPCX_FIU_DRA_V1 || \
55		     FLASH_NPCX_FIU_DRA_V2
56	help
57	  Selected if NPCX series supports 4 byte address mode in Direct Read
58	  Access mode.
59
60config FLASH_NPCX_FIU_SUPP_DRA_2_DEV
61	bool "4 byte address support in Direct Read Access mode"
62	default y if FLASH_NPCX_FIU_DRA_V1 || \
63		     FLASH_NPCX_FIU_DRA_V2
64	help
65	  Selected if NPCX series supports two external SPI devices in Direct
66	  Read Access (DRA) on QSPI bus.
67
68endif #FLASH_NPCX_FIU_QSPI
69