1menu "Hardware Settings" 2 3 menu "Chip revision" 4 # Insert chip-specific HW config 5 orsource "./port/$IDF_TARGET/Kconfig.hw_support" 6 7 config ESP_REV_NEW_CHIP_TEST 8 bool "Internal test mode" 9 depends on IDF_CI_BUILD 10 default n 11 help 12 For internal chip testing, a small number of new versions chips didn't 13 update the version field in eFuse, you can enable this option to force the 14 software recognize the chip version based on the rev selected in menuconfig. 15 endmenu 16 17 orsource "./port/$IDF_TARGET/Kconfig.spiram" 18 19 menu "MAC Config" 20 config ESP_MAC_ADDR_UNIVERSE_WIFI_STA 21 bool 22 23 config ESP_MAC_ADDR_UNIVERSE_WIFI_AP 24 bool 25 26 config ESP_MAC_ADDR_UNIVERSE_BT 27 bool 28 29 config ESP_MAC_ADDR_UNIVERSE_ETH 30 bool 31 32 config ESP_MAC_ADDR_UNIVERSE_IEEE802154 33 bool 34 35 config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE 36 bool 37 38 config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO 39 bool 40 41 config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR 42 bool 43 44 # Insert chip-specific MAC config 45 orsource "./port/$IDF_TARGET/Kconfig.mac" 46 47 config ESP_MAC_IGNORE_MAC_CRC_ERROR 48 bool "Ignore MAC CRC error (not recommended)" 49 depends on IDF_TARGET_ESP32 50 default n 51 help 52 If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem 53 and you still want to use this chip, you can enable this option to bypass such an error. 54 This applies to both MAC_FACTORY and CUSTOM_MAC efuses. 55 endmenu 56 57 menu "Sleep Config" 58 # This is here since this option affect behavior of esp_light_sleep_start 59 # regardless of power management configuration. 60 config ESP_SLEEP_POWER_DOWN_FLASH 61 bool "Power down flash in light sleep when there is no SPIRAM" 62 depends on !SPIRAM 63 default n 64 help 65 If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs 66 more time when chip wakes up. Can only be enabled if there is no SPIRAM configured. 67 68 This option will power down flash under a strict but relatively safe condition. Also, it is possible to 69 power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO 70 to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer 71 `ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details. 72 73 config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND 74 bool "Pull-up Flash CS pin in light sleep" 75 depends on !APP_BUILD_TYPE_PURE_RAM_APP && !ESP_SLEEP_POWER_DOWN_FLASH 76 default y 77 help 78 All IOs will be set to isolate(floating) state by default during sleep. 79 Since the power supply of SPI Flash is not lost during lightsleep, if its CS pin is recognized as 80 low level(selected state) in the floating state, there will be a large current leakage, and the 81 data in Flash may be corrupted by random signals on other SPI pins. 82 Select this option will set the CS pin of Flash to PULL-UP state during sleep, but this will 83 increase the sleep current about 10 uA. 84 If you are developing with esp32xx modules, you must select this option, but if you are developing 85 with chips, you can also pull up the CS pin of SPI Flash in the external circuit to save power 86 consumption caused by internal pull-up during sleep. 87 (!!! Don't deselect this option if you don't have external SPI Flash CS pin pullups.) 88 89 config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND 90 bool "Pull-up PSRAM CS pin in light sleep" 91 depends on SPIRAM 92 default y 93 help 94 All IOs will be set to isolate(floating) state by default during sleep. 95 Since the power supply of PSRAM is not lost during lightsleep, if its CS pin is recognized as 96 low level(selected state) in the floating state, there will be a large current leakage, and the 97 data in PSRAM may be corrupted by random signals on other SPI pins. 98 Select this option will set the CS pin of PSRAM to PULL-UP state during sleep, but this will 99 increase the sleep current about 10 uA. 100 If you are developing with esp32xx modules, you must select this option, but if you are developing 101 with chips, you can also pull up the CS pin of PSRAM in the external circuit to save power 102 consumption caused by internal pull-up during sleep. 103 (!!! Don't deselect this option if you don't have external PSRAM CS pin pullups.) 104 105 config ESP_SLEEP_MSPI_NEED_ALL_IO_PU 106 bool "Pull-up all SPI pins in light sleep" 107 depends on !ESP_SLEEP_POWER_DOWN_FLASH \ 108 && (ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND) 109 default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3 110 help 111 To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin 112 during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up 113 all pins. It depends on the SPI Flash/RAM chip used. 114 115 config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND 116 bool 117 default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3 118 119 config ESP_SLEEP_GPIO_RESET_WORKAROUND 120 bool "light sleep GPIO reset workaround" 121 default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \ 122 IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2 123 select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE 124 help 125 esp32c2, esp32c3, esp32s3, esp32c6 and esp32h2 will reset at wake-up if GPIO is received 126 a small electrostatic pulse during light sleep, with specific condition 127 128 - GPIO needs to be configured as input-mode only 129 - The pin receives a small electrostatic pulse, and reset occurs when the pulse 130 voltage is higher than 6 V 131 132 For GPIO set to input mode only, it is not a good practice to leave it open/floating, 133 The hardware design needs to controlled it with determined supply or ground voltage 134 is necessary. 135 136 This option provides a software workaround for this issue. Configure to isolate all 137 GPIO pins in sleep state. 138 139 config ESP_SLEEP_DEEP_SLEEP_WAKEUP_DELAY 140 int "Extra delay in deep sleep wake stub (in us)" 141 depends on IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3 142 default 2000 143 range 0 5000 144 help 145 When the chip exits deep sleep, the CPU and the flash chip are powered on 146 at the same time. CPU will run deep sleep stub first, and then 147 proceed to load code from flash. Some flash chips need sufficient 148 time to pass between power on and first read operation. By default, 149 without any extra delay, this time is approximately 900us, although 150 some flash chip types need more than that. 151 152 By default extra delay is set to 2000us. When optimizing startup time 153 for applications which require it, this value may be reduced. 154 155 If you are seeing "flash read err, 1000" message printed to the 156 console after deep sleep reset, try increasing this value. 157 endmenu 158 159 menu "ESP_SLEEP_WORKAROUND" 160 # No visible menu/configs for workaround 161 visible if 0 162 config ESP_SLEEP_SYSTIMER_STALL_WORKAROUND 163 bool "ESP32C3 SYSTIMER Stall Issue Workaround" 164 depends on IDF_TARGET_ESP32C3 165 help 166 Its not able to stall ESP32C3 systimer in sleep. 167 To fix related RTOS TICK issue, select it to disable related systimer during sleep. 168 TODO: IDF-7036 169 endmenu 170 171 menu "RTC Clock Config" 172 orsource "./port/$IDF_TARGET/Kconfig.rtc" 173 endmenu 174 175 menu "Peripheral Control" 176 config PERIPH_CTRL_FUNC_IN_IRAM 177 bool "Place peripheral control functions into IRAM" 178 default n 179 help 180 Place peripheral control functions (e.g. periph_module_reset) into IRAM, 181 so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. 182 endmenu 183 184 menu "ETM Configuration" 185 depends on SOC_ETM_SUPPORTED 186 config ETM_ENABLE_DEBUG_LOG 187 bool "Enable debug log" 188 default n 189 help 190 Wether to enable the debug log message for ETM core driver. 191 Note that, this option only controls the ETM related driver log, won't affect other drivers. 192 endmenu # ETM Configuration 193 194 menu "GDMA Configuration" 195 depends on SOC_GDMA_SUPPORTED 196 config GDMA_CTRL_FUNC_IN_IRAM 197 bool "Place GDMA control functions into IRAM" 198 default n 199 help 200 Place GDMA control functions (like start/stop/append/reset) into IRAM, 201 so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context. 202 Enabling this option can improve driver performance as well. 203 204 config GDMA_ISR_IRAM_SAFE 205 bool "GDMA ISR IRAM-Safe" 206 default n 207 help 208 This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash 209 cache misses, and also be able to run whilst the cache is disabled. 210 (e.g. SPI Flash write). 211 endmenu # GDMA Configuration 212 213 menu "Main XTAL Config" 214 choice XTAL_FREQ_SEL 215 prompt "Main XTAL frequency" 216 default XTAL_FREQ_40 if SOC_XTAL_SUPPORT_40M 217 help 218 This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target. 219 The selected value MUST reflect the frequency of the given hardware. 220 221 Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's 222 operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the 223 internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being 224 temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate 225 in high ambient temperatures or use high-temperature qualified chips and modules. 226 227 config XTAL_FREQ_24 228 depends on SOC_XTAL_SUPPORT_24M 229 bool "24 MHz" 230 config XTAL_FREQ_26 231 depends on SOC_XTAL_SUPPORT_26M 232 bool "26 MHz" 233 config XTAL_FREQ_32 234 depends on SOC_XTAL_SUPPORT_32M 235 bool "32 MHz" 236 config XTAL_FREQ_40 237 depends on SOC_XTAL_SUPPORT_40M 238 bool "40 MHz" 239 config XTAL_FREQ_AUTO 240 depends on SOC_XTAL_SUPPORT_AUTO_DETECT 241 bool "Autodetect" 242 endchoice 243 244 # rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported 245 # SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported 246 config XTAL_FREQ 247 int 248 default 24 if XTAL_FREQ_24 249 default 26 if XTAL_FREQ_26 250 default 32 if XTAL_FREQ_32 251 default 40 if XTAL_FREQ_40 252 default 0 if XTAL_FREQ_AUTO 253 endmenu 254 255 menu "Crypto DPA Protection" 256 depends on SOC_CRYPTO_DPA_PROTECTION_SUPPORTED 257 config ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP 258 bool "Enable crypto DPA protection at startup" 259 default y 260 help 261 This config controls the DPA (Differential Power Analysis) protection 262 knob for the crypto peripherals. DPA protection dynamically adjusts the 263 clock frequency of the crypto peripheral. DPA protection helps to make it 264 difficult to perform SCA attacks on the crypto peripherals. However, 265 there is also associated performance impact based on the security level 266 set. Please refer to the TRM for more details. 267 268 choice ESP_CRYPTO_DPA_PROTECTION_LEVEL 269 prompt "DPA protection level" 270 depends on ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP 271 default ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW 272 help 273 Configure the DPA protection security level 274 275 config ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW 276 bool "Security level low" 277 278 config ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM 279 bool "Security level medium" 280 281 config ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH 282 bool "Security level high" 283 endchoice 284 285 config ESP_CRYPTO_DPA_PROTECTION_LEVEL 286 int 287 default 1 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW 288 default 2 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM 289 default 3 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH 290 291 endmenu 292endmenu 293
