1menu "Hardware Settings"
2
3    menu "Chip revision"
4        # Insert chip-specific HW config
5        orsource "./port/$IDF_TARGET/Kconfig.hw_support"
6
7        config ESP_REV_NEW_CHIP_TEST
8            bool "Internal test mode"
9            depends on IDF_CI_BUILD
10            default n
11            help
12                For internal chip testing, a small number of new versions chips didn't
13                update the version field in eFuse, you can enable this option to force the
14                software recognize the chip version based on the rev selected in menuconfig.
15    endmenu
16
17    orsource "./port/$IDF_TARGET/Kconfig.spiram"
18
19    menu "MAC Config"
20        config ESP_MAC_ADDR_UNIVERSE_WIFI_STA
21            bool
22
23        config ESP_MAC_ADDR_UNIVERSE_WIFI_AP
24            bool
25
26        config ESP_MAC_ADDR_UNIVERSE_BT
27            bool
28
29        config ESP_MAC_ADDR_UNIVERSE_ETH
30            bool
31
32        config ESP_MAC_ADDR_UNIVERSE_IEEE802154
33            bool
34
35        config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_ONE
36            bool
37
38        config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_TWO
39            bool
40
41        config ESP_MAC_UNIVERSAL_MAC_ADDRESSES_FOUR
42            bool
43
44            # Insert chip-specific MAC config
45        orsource "./port/$IDF_TARGET/Kconfig.mac"
46
47        config ESP_MAC_IGNORE_MAC_CRC_ERROR
48            bool "Ignore MAC CRC error (not recommended)"
49            depends on IDF_TARGET_ESP32
50            default n
51            help
52                If you have an invalid MAC CRC (ESP_ERR_INVALID_CRC) problem
53                and you still want to use this chip, you can enable this option to bypass such an error.
54                This applies to both MAC_FACTORY and CUSTOM_MAC efuses.
55
56        config ESP_MAC_USE_CUSTOM_MAC_AS_BASE_MAC
57            bool "Enable using custom mac as base mac"
58            default n
59            help
60                When this configuration is enabled, the user can invoke `esp_read_mac` to obtain the desired type of
61                MAC using a custom MAC as the base MAC.
62    endmenu
63
64    menu "Sleep Config"
65        # This is here since this option affect behavior of esp_light_sleep_start
66        # regardless of power management configuration.
67        config ESP_SLEEP_POWER_DOWN_FLASH
68            bool "Power down flash in light sleep when there is no SPIRAM"
69            depends on !SPIRAM
70            default n
71            help
72                If enabled, chip will try to power down flash as part of esp_light_sleep_start(), which costs
73                more time when chip wakes up. Can only be enabled if there is no SPIRAM configured.
74
75                This option will power down flash under a strict but relatively safe condition. Also, it is possible to
76                power down flash under a relaxed condition by using esp_sleep_pd_config() to set ESP_PD_DOMAIN_VDDSDIO
77                to ESP_PD_OPTION_OFF. It should be noted that there is a risk in powering down flash, you can refer
78                `ESP-IDF Programming Guide/API Reference/System API/Sleep Modes/Power-down of Flash` for more details.
79
80        config ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND
81            bool "Pull-up Flash CS pin in light sleep"
82            depends on !APP_BUILD_TYPE_PURE_RAM_APP
83            default y
84            help
85                All IOs will be set to isolate(floating) state by default during sleep.
86                Since the power supply of SPI Flash is not lost during lightsleep, if its CS pin is recognized as
87                low level(selected state) in the floating state, there will be a large current leakage, and the
88                data in Flash may be corrupted by random signals on other SPI pins.
89                Select this option will set the CS pin of Flash to PULL-UP state during sleep, but this will
90                increase the sleep current about 10 uA.
91                If you are developing with esp32xx modules, you must select this option, but if you are developing
92                with chips, you can also pull up the CS pin of SPI Flash in the external circuit to save power
93                consumption caused by internal pull-up during sleep.
94                (!!! Don't deselect this option if you don't have external SPI Flash CS pin pullups.)
95
96        config ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND
97            bool "Pull-up PSRAM CS pin in light sleep"
98            depends on SPIRAM
99            default y
100            help
101                All IOs will be set to isolate(floating) state by default during sleep.
102                Since the power supply of PSRAM is not lost during lightsleep, if its CS pin is recognized as
103                low level(selected state) in the floating state, there will be a large current leakage, and the
104                data in PSRAM may be corrupted by random signals on other SPI pins.
105                Select this option will set the CS pin of PSRAM to PULL-UP state during sleep, but this will
106                increase the sleep current about 10 uA.
107                If you are developing with esp32xx modules, you must select this option, but if you are developing
108                with chips, you can also pull up the CS pin of PSRAM in the external circuit to save power
109                consumption caused by internal pull-up during sleep.
110                (!!! Don't deselect this option if you don't have external PSRAM CS pin pullups.)
111
112        config ESP_SLEEP_MSPI_NEED_ALL_IO_PU
113            bool "Pull-up all SPI pins in light sleep"
114            depends on (ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND || ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND)
115            default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32S3
116            help
117                To reduce leakage current, some types of SPI Flash/RAM only need to pull up the CS pin
118                during light sleep. But there are also some kinds of SPI Flash/RAM that need to pull up
119                all pins. It depends on the SPI Flash/RAM chip used.
120
121        config ESP_SLEEP_RTC_BUS_ISO_WORKAROUND
122            bool
123            default y if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3
124
125        config ESP_SLEEP_GPIO_RESET_WORKAROUND
126            bool "light sleep GPIO reset workaround"
127            default y if IDF_TARGET_ESP32C2 || IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 || \
128                IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32H2
129            select PM_SLP_DISABLE_GPIO if FREERTOS_USE_TICKLESS_IDLE
130            help
131                esp32c2, esp32c3, esp32s3, esp32c6 and esp32h2 will reset at wake-up if GPIO is received
132                a small electrostatic pulse during light sleep, with specific condition
133
134                - GPIO needs to be configured as input-mode only
135                - The pin receives a small electrostatic pulse, and reset occurs when the pulse
136                  voltage is higher than 6 V
137
138                For GPIO set to input mode only, it is not a good practice to leave it open/floating,
139                The hardware design needs to controlled it with determined supply or ground voltage
140                is necessary.
141
142                This option provides a software workaround for this issue. Configure to isolate all
143                GPIO pins in sleep state.
144
145        config ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY
146            int "Extra delay (in us) after flash powerdown sleep wakeup to wait flash ready"
147            default 2000 if IDF_TARGET_ESP32 || IDF_TARGET_ESP32S3
148            default 0
149            range 0 5000
150            help
151                When the chip exits sleep, the CPU and the flash chip are powered on at the same time.
152                CPU will run rom code (deepsleep) or ram code (lightsleep) first, and then load or execute
153                code from flash.
154
155                Some flash chips need sufficient time to pass between power on and first read operation.
156                By default, without any extra delay, this time is approximately 900us, although
157                some flash chip types need more than that.
158
159                (!!! Please adjust this value according to the Data Sheet of SPI Flash used in your project.)
160                In Flash Data Sheet, the parameters that define the Flash ready timing after power-up (minimum
161                time from Vcc(min) to CS activeare) usually named tVSL in ELECTRICAL CHARACTERISTICS chapter,
162                and the configuration value here should be:
163                ESP_SLEEP_WAIT_FLASH_READY_EXTRA_DELAY = tVSL - 900
164
165                For esp32 and esp32s3, the default extra delay is set to 2000us. When optimizing startup time
166                for applications which require it, this value may be reduced.
167
168                If you are seeing "flash read err, 1000" message printed to the console after deep sleep reset
169                on esp32, or triggered RTC_WDT/LP_WDT after lightsleep wakeup, try increasing this value.
170                (For esp32, the delay will be executed in both deep sleep and light sleep wake up flow.
171                For chips after esp32, the delay will be executed only in light sleep flow, the delay
172                controlled by the EFUSE_FLASH_TPUW in ROM will be executed in deepsleep wake up flow.)
173
174        config ESP_SLEEP_DEBUG
175            bool "esp sleep debug"
176            default n
177            help
178                Enable esp sleep debug.
179
180        config ESP_SLEEP_GPIO_ENABLE_INTERNAL_RESISTORS
181            bool "Allow to enable internal pull-up/downs for the Deep-Sleep wakeup IOs"
182            default y
183            help
184                When using rtc gpio wakeup source during deepsleep without external pull-up/downs, you may want to
185                make use of the internal ones.
186
187        config ESP_SLEEP_EVENT_CALLBACKS
188            bool "Enable registration of sleep event callbacks"
189            depends on FREERTOS_USE_TICKLESS_IDLE
190            default n
191            help
192                If enabled, it allows user to register sleep event callbacks. It is primarily designed for internal
193                developers and customers can use PM_LIGHT_SLEEP_CALLBACKS as an alternative.
194
195                NOTE: These callbacks are executed from the IDLE task context hence you cannot have any blocking calls
196                in your callbacks.
197
198                NOTE: Enabling these callbacks may change sleep duration calculations based on time spent in
199                callback and hence it is highly recommended to keep them as short as possible.
200
201        config ESP_SLEEP_CACHE_SAFE_ASSERTION
202            bool "Check the cache safety of the sleep wakeup code in sleep process"
203            default n
204            select ESP_PANIC_HANDLER_IRAM
205            help
206                Enabling it will check the cache safety of the code before the flash power is ready after
207                light sleep wakeup, and check PM_SLP_IRAM_OPT related code cache safety. This option is
208                only for code quality inspection. Enabling it will increase the time overhead of entering
209                and exiting sleep. It is not recommended to enable it in the release version.
210
211    endmenu
212
213    menu "RTC Clock Config"
214        orsource "./port/$IDF_TARGET/Kconfig.rtc"
215    endmenu
216
217    menu "Peripheral Control"
218        config PERIPH_CTRL_FUNC_IN_IRAM
219            bool "Place peripheral control functions into IRAM"
220            default n
221            help
222                Place peripheral control functions (e.g. periph_module_reset) into IRAM,
223                so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
224    endmenu
225
226    menu "ETM Configuration"
227        depends on SOC_ETM_SUPPORTED
228        config ETM_ENABLE_DEBUG_LOG
229            bool "Enable debug log"
230            default n
231            help
232                Wether to enable the debug log message for ETM core driver.
233                Note that, this option only controls the ETM related driver log, won't affect other drivers.
234    endmenu # ETM Configuration
235
236    menu "GDMA Configuration"
237        depends on SOC_GDMA_SUPPORTED
238        config GDMA_CTRL_FUNC_IN_IRAM
239            bool "Place GDMA control functions into IRAM"
240            default n
241            help
242                Place GDMA control functions (like start/stop/append/reset) into IRAM,
243                so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
244                Enabling this option can improve driver performance as well.
245
246        config GDMA_ISR_IRAM_SAFE
247            bool "GDMA ISR IRAM-Safe"
248            default n
249            help
250                This will ensure the GDMA interrupt handler is IRAM-Safe, allow to avoid flash
251                cache misses, and also be able to run whilst the cache is disabled.
252                (e.g. SPI Flash write).
253    endmenu # GDMA Configuration
254
255    menu "Main XTAL Config"
256        choice XTAL_FREQ_SEL
257            prompt "Main XTAL frequency"
258            default XTAL_FREQ_40 if SOC_XTAL_SUPPORT_40M
259            help
260                This option selects the operating frequency of the XTAL (crystal) clock used to drive the ESP target.
261                The selected value MUST reflect the frequency of the given hardware.
262
263                Note: The XTAL_FREQ_AUTO option allows the ESP target to automatically estimating XTAL clock's
264                operating frequency. However, this feature is only supported on the ESP32. The ESP32 uses the
265                internal 8MHZ as a reference when estimating. Due to the internal oscillator's frequency being
266                temperature dependent, usage of the XTAL_FREQ_AUTO is not recommended in applications that operate
267                in high ambient temperatures or use high-temperature qualified chips and modules.
268
269            config XTAL_FREQ_24
270                depends on SOC_XTAL_SUPPORT_24M
271                bool "24 MHz"
272            config XTAL_FREQ_26
273                depends on SOC_XTAL_SUPPORT_26M
274                bool "26 MHz"
275            config XTAL_FREQ_32
276                depends on SOC_XTAL_SUPPORT_32M
277                bool "32 MHz"
278            config XTAL_FREQ_40
279                depends on SOC_XTAL_SUPPORT_40M
280                bool "40 MHz"
281            config XTAL_FREQ_AUTO
282                depends on SOC_XTAL_SUPPORT_AUTO_DETECT
283                bool "Autodetect"
284        endchoice
285
286        # rtc_xtal_freq_t enum in soc/rtc.h lists the XTAL frequencies can be supported
287        # SOC_XTAL_SUPPORT_XXX in soc_caps.h lists the XTAL frequencies already supported
288        config XTAL_FREQ
289            int
290            default 24 if XTAL_FREQ_24
291            default 26 if XTAL_FREQ_26
292            default 32 if XTAL_FREQ_32
293            default 40 if XTAL_FREQ_40
294            default 0  if XTAL_FREQ_AUTO
295    endmenu
296
297    menu "Crypto DPA Protection"
298        depends on SOC_CRYPTO_DPA_PROTECTION_SUPPORTED
299        config ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
300            bool "Enable crypto DPA protection at startup"
301            default y
302            help
303                This config controls the DPA (Differential Power Analysis) protection
304                knob for the crypto peripherals. DPA protection dynamically adjusts the
305                clock frequency of the crypto peripheral. DPA protection helps to make it
306                difficult to perform SCA attacks on the crypto peripherals. However,
307                there is also associated performance impact based on the security level
308                set. Please refer to the TRM for more details.
309
310        choice ESP_CRYPTO_DPA_PROTECTION_LEVEL
311            prompt "DPA protection level"
312            depends on ESP_CRYPTO_DPA_PROTECTION_AT_STARTUP
313            default ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
314            help
315                Configure the DPA protection security level
316
317            config ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
318                bool "Security level low"
319
320            config ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM
321                bool "Security level medium"
322
323            config ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH
324                bool "Security level high"
325        endchoice
326
327        config ESP_CRYPTO_DPA_PROTECTION_LEVEL
328            int
329            default 1 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_LOW
330            default 2 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_MEDIUM
331            default 3 if ESP_CRYPTO_DPA_PROTECTION_LEVEL_HIGH
332
333    endmenu
334endmenu
335