1 2menu "ESP System Settings" 3 # Insert chip-specific cpu config 4 rsource "./port/soc/$IDF_TARGET/Kconfig.cpu" 5 6 orsource "./port/soc/$IDF_TARGET/Kconfig.cache" 7 8 orsource "./port/soc/$IDF_TARGET/Kconfig.memory" 9 10 orsource "./port/soc/$IDF_TARGET/Kconfig.tracemem" 11 12 choice ESP_SYSTEM_PANIC 13 prompt "Panic handler behaviour" 14 default ESP_SYSTEM_PANIC_PRINT_REBOOT 15 help 16 If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is 17 invoked. Configure the panic handler's action here. 18 19 config ESP_SYSTEM_PANIC_PRINT_HALT 20 bool "Print registers and halt" 21 help 22 Outputs the relevant registers over the serial port and halt the 23 processor. Needs a manual reset to restart. 24 25 config ESP_SYSTEM_PANIC_PRINT_REBOOT 26 bool "Print registers and reboot" 27 help 28 Outputs the relevant registers over the serial port and immediately 29 reset the processor. 30 31 config ESP_SYSTEM_PANIC_SILENT_REBOOT 32 bool "Silent reboot" 33 help 34 Just resets the processor without outputting anything 35 36 config ESP_SYSTEM_PANIC_GDBSTUB 37 bool "GDBStub on panic" 38 select ESP_GDBSTUB_ENABLED 39 help 40 Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem 41 of the crash. 42 43 config ESP_SYSTEM_GDBSTUB_RUNTIME 44 bool "GDBStub at runtime" 45 select ESP_GDBSTUB_ENABLED 46 depends on !IDF_TARGET_ESP32C2 47 help 48 Invoke gdbstub on the serial port, allowing for gdb to attach to it and to do a debug on runtime. 49 endchoice 50 51 config ESP_SYSTEM_PANIC_REBOOT_DELAY_SECONDS 52 int "Panic reboot delay (Seconds)" 53 default 0 54 range 0 99 55 depends on ESP_SYSTEM_PANIC_PRINT_REBOOT 56 help 57 After the panic handler executes, you can specify a number of seconds to 58 wait before the device reboots. 59 60 config ESP_SYSTEM_SINGLE_CORE_MODE 61 bool 62 default n 63 help 64 Only initialize and use the main core. 65 66 config ESP_SYSTEM_RTC_EXT_XTAL 67 # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option 68 # e.g. It will be selected on when RTC_CLK_SRC_EXT_CRYS is on 69 bool 70 default n 71 72 config ESP_SYSTEM_RTC_EXT_OSC 73 # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option 74 # e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on 75 bool 76 default n 77 78 config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 79 int "Bootstrap cycles for external 32kHz crystal" 80 depends on ESP_SYSTEM_RTC_EXT_XTAL 81 default 5 if IDF_TARGET_ESP32 82 default 0 83 range 0 32768 84 help 85 To reduce the startup time of an external RTC crystal, 86 we bootstrap it with a 32kHz square wave for a fixed number of cycles. 87 Setting 0 will disable bootstrapping (if disabled, the crystal may take 88 longer to start up or fail to oscillate under some conditions). 89 90 If this value is too high, a faulty crystal may initially start and then fail. 91 If this value is too low, an otherwise good crystal may not start. 92 93 To accurately determine if the crystal has started, 94 set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). 95 96 config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 97 bool 98 default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE 99 default y if IDF_TARGET_ESP32S2 100 default y if IDF_TARGET_ESP32C3 101 default y if IDF_TARGET_ESP32S3 102 default y if IDF_TARGET_ESP32C6 103 default n if IDF_TARGET_ESP32H2 # IDF-5667 104 depends on SOC_RTC_FAST_MEM_SUPPORTED 105 106 config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 107 bool "Enable RTC fast memory for dynamic allocations" 108 default y 109 depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 110 help 111 This config option allows to add RTC fast memory region to system heap with capability 112 similar to that of DRAM region but without DMA. This memory will be consumed first per 113 heap initialization order by early startup services and scheduler related code. Speed 114 wise RTC fast memory operates on APB clock and hence does not have much performance impact. 115 116 config ESP_SYSTEM_USE_EH_FRAME 117 bool "Generate and use eh_frame for backtracing" 118 default n 119 depends on IDF_TARGET_ARCH_RISCV 120 help 121 Generate DWARF information for each function of the project. These information will parsed and used to 122 perform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding 123 and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to 124 100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by 125 the program itself, regardless of the serial monitor used. 126 This option shall NOT be used for production. 127 128 menu "Memory protection" 129 130 config ESP_SYSTEM_PMP_IDRAM_SPLIT 131 bool "Enable IRAM/DRAM split protection" 132 depends on SOC_CPU_IDRAM_SPLIT_USING_PMP 133 default "y" 134 help 135 If enabled, the CPU watches all the memory access and raises an exception in case 136 of any memory violation. This feature automatically splits 137 the SRAM memory, using PMP, into data and instruction segments and sets Read/Execute permissions 138 for the instruction part (below given splitting address) and Read/Write permissions 139 for the data part (above the splitting address). The memory protection is effective 140 on all access through the IRAM0 and DRAM0 buses. 141 142 config ESP_SYSTEM_MEMPROT_FEATURE 143 bool "Enable memory protection" 144 depends on SOC_MEMPROT_SUPPORTED 145 default "y" 146 help 147 If enabled, the permission control module watches all the memory access and fires the panic handler 148 if a permission violation is detected. This feature automatically splits 149 the SRAM memory into data and instruction segments and sets Read/Execute permissions 150 for the instruction part (below given splitting address) and Read/Write permissions 151 for the data part (above the splitting address). The memory protection is effective 152 on all access through the IRAM0 and DRAM0 buses. 153 154 config ESP_SYSTEM_MEMPROT_FEATURE_LOCK 155 depends on ESP_SYSTEM_MEMPROT_FEATURE 156 bool "Lock memory protection settings" 157 default "y" 158 help 159 Once locked, memory protection settings cannot be changed anymore. 160 The lock is reset only on the chip startup. 161 162 endmenu # Memory protection 163 164 config ESP_SYSTEM_EVENT_QUEUE_SIZE 165 int "System event queue size" 166 default 32 167 help 168 Config system event queue size in different application. 169 170 config ESP_SYSTEM_EVENT_TASK_STACK_SIZE 171 int "Event loop task stack size" 172 default 2304 173 help 174 Config system event task stack size in different application. 175 176 config ESP_MAIN_TASK_STACK_SIZE 177 int "Main task stack size" 178 default 3584 179 help 180 Configure the "main task" stack size. This is the stack of the task 181 which calls app_main(). If app_main() returns then this task is deleted 182 and its stack memory is freed. 183 184 choice ESP_MAIN_TASK_AFFINITY 185 prompt "Main task core affinity" 186 default ESP_MAIN_TASK_AFFINITY_CPU0 187 help 188 Configure the "main task" core affinity. This is the used core of the task 189 which calls app_main(). If app_main() returns then this task is deleted. 190 191 config ESP_MAIN_TASK_AFFINITY_CPU0 192 bool "CPU0" 193 config ESP_MAIN_TASK_AFFINITY_CPU1 194 bool "CPU1" 195 depends on !FREERTOS_UNICORE 196 config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY 197 bool "No affinity" 198 199 endchoice 200 201 config ESP_MAIN_TASK_AFFINITY 202 hex 203 default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0 204 default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1 205 default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY 206 207 config ESP_MINIMAL_SHARED_STACK_SIZE 208 int "Minimal allowed size for shared stack" 209 default 2048 210 help 211 Minimal value of size, in bytes, accepted to execute a expression 212 with shared stack. 213 214 choice ESP_CONSOLE_UART 215 prompt "Channel for console output" 216 default ESP_CONSOLE_UART_DEFAULT 217 help 218 Select where to send console output (through stdout and stderr). 219 220 - Default is to use UART0 on pre-defined GPIOs. 221 - If "Custom" is selected, UART0 or UART1 can be chosen, 222 and any pins can be selected. 223 - If "None" is selected, there will be no console output on any UART, except 224 for initial output from ROM bootloader. This ROM output can be suppressed by 225 GPIO strapping or EFUSE, refer to chip datasheet for details. 226 - On chips with USB OTG peripheral, "USB CDC" option redirects output to the 227 CDC port. This option uses the CDC driver in the chip ROM. 228 This option is incompatible with TinyUSB stack. 229 - On chips with an USB serial/JTAG debug controller, selecting the option 230 for that redirects output to the CDC/ACM (serial port emulation) component 231 of that device. 232 config ESP_CONSOLE_UART_DEFAULT 233 bool "Default: UART0" 234 config ESP_CONSOLE_USB_CDC 235 bool "USB CDC" 236 # && !TINY_USB is because the ROM CDC driver is currently incompatible with TinyUSB. 237 depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB 238 config ESP_CONSOLE_USB_SERIAL_JTAG 239 bool "USB Serial/JTAG Controller" 240 select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252 241 depends on SOC_USB_SERIAL_JTAG_SUPPORTED 242 config ESP_CONSOLE_UART_CUSTOM 243 bool "Custom UART" 244 config ESP_CONSOLE_NONE 245 bool "None" 246 endchoice 247 248 choice ESP_CONSOLE_SECONDARY 249 depends on SOC_USB_SERIAL_JTAG_SUPPORTED 250 prompt "Channel for console secondary output" 251 default ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 252 help 253 This secondary option supports output through other specific port like USB_SERIAL_JTAG 254 when UART0 port as a primary is selected but not connected. This secondary output currently only supports 255 non-blocking mode without using REPL. If you want to output in blocking mode with REPL or 256 input through this secondary port, please change the primary config to this port 257 in `Channel for console output` menu. 258 config ESP_CONSOLE_SECONDARY_NONE 259 bool "No secondary console" 260 config ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 261 bool "USB_SERIAL_JTAG PORT" 262 depends on !ESP_CONSOLE_USB_SERIAL_JTAG 263 help 264 This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected. 265 The output currently only supports non-blocking mode without using the console. 266 If you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port, 267 please change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above. 268 endchoice 269 270 config ESP_CONSOLE_USB_SERIAL_JTAG_ENABLED 271 # Internal option, indicates that console USB SERIAL JTAG is used 272 bool 273 default y if ESP_CONSOLE_USB_SERIAL_JTAG || ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 274 275 config ESP_CONSOLE_UART 276 # Internal option, indicates that console UART is used (and not USB, for example) 277 bool 278 default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM 279 280 config ESP_CONSOLE_MULTIPLE_UART 281 bool 282 default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 && !IDF_TARGET_ESP32C2 && !IDF_TARGET_ESP32C6 283 284 choice ESP_CONSOLE_UART_NUM 285 prompt "UART peripheral to use for console output (0-1)" 286 depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART 287 default ESP_CONSOLE_UART_CUSTOM_NUM_0 288 help 289 This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. 290 291 If the configuration is different in the Bootloader binary compared to the app binary, UART 292 is reconfigured after the bootloader exits and the app starts. 293 294 Due to an ESP32 ROM bug, UART2 is not supported for console output 295 via esp_rom_printf. 296 297 config ESP_CONSOLE_UART_CUSTOM_NUM_0 298 bool "UART0" 299 config ESP_CONSOLE_UART_CUSTOM_NUM_1 300 bool "UART1" 301 endchoice 302 303 config ESP_CONSOLE_UART_NUM 304 int 305 default 0 if ESP_CONSOLE_UART_DEFAULT 306 default 0 if !ESP_CONSOLE_MULTIPLE_UART 307 default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 308 default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 309 default -1 if !ESP_CONSOLE_UART 310 311 config ESP_CONSOLE_UART_TX_GPIO 312 int "UART TX on GPIO#" 313 depends on ESP_CONSOLE_UART_CUSTOM 314 range 0 46 315 default 1 if IDF_TARGET_ESP32 316 default 20 if IDF_TARGET_ESP32C2 317 default 21 if IDF_TARGET_ESP32C3 318 default 16 if IDF_TARGET_ESP32C6 319 default 24 if IDF_TARGET_ESP32H2 320 default 43 321 help 322 This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including 323 boot log output and default standard output and standard error of the app). 324 325 If the configuration is different in the Bootloader binary compared to the app binary, UART 326 is reconfigured after the bootloader exits and the app starts. 327 328 config ESP_CONSOLE_UART_RX_GPIO 329 int "UART RX on GPIO#" 330 depends on ESP_CONSOLE_UART_CUSTOM 331 range 0 46 332 default 3 if IDF_TARGET_ESP32 333 default 19 if IDF_TARGET_ESP32C2 334 default 20 if IDF_TARGET_ESP32C3 335 default 17 if IDF_TARGET_ESP32C6 336 default 23 if IDF_TARGET_ESP32H2 337 default 44 338 help 339 This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including 340 default default standard input of the app). 341 342 Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. 343 344 If the configuration is different in the Bootloader binary compared to the app binary, UART 345 is reconfigured after the bootloader exits and the app starts. 346 347 348 config ESP_CONSOLE_UART_BAUDRATE 349 int 350 prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM 351 depends on ESP_CONSOLE_UART 352 default 74880 if (IDF_TARGET_ESP32C2 && XTAL_FREQ_26) 353 default 115200 354 range 1200 4000000 if !PM_ENABLE 355 range 1200 1000000 if PM_ENABLE 356 help 357 This baud rate is used by both the ESP-IDF Bootloader and the app (including 358 boot log output and default standard input/output/error of the app). 359 360 The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, 361 the UART clock source is the APB clock and all baud rates in the available range will be sufficiently 362 accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided 363 from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be 364 accurate. 365 366 If the configuration is different in the Bootloader binary compared to the app binary, UART 367 is reconfigured after the bootloader exits and the app starts. 368 369 config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE 370 int "Size of USB CDC RX buffer" 371 depends on ESP_CONSOLE_USB_CDC 372 default 64 373 range 4 16384 374 help 375 Set the size of USB CDC RX buffer. Increase the buffer size if your application 376 is often receiving data over USB CDC. 377 378 config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF 379 bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" 380 depends on ESP_CONSOLE_USB_CDC 381 default n 382 help 383 If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. 384 Disabling this option saves about 1kB or RAM. 385 386 config ESP_INT_WDT 387 bool "Interrupt watchdog" 388 default y 389 help 390 This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, 391 either because a task turned off interrupts and did not turn them on for a long time, or because an 392 interrupt handler did not return. It will try to invoke the panic handler first and failing that 393 reset the SoC. 394 395 config ESP_INT_WDT_TIMEOUT_MS 396 int "Interrupt watchdog timeout (ms)" 397 depends on ESP_INT_WDT 398 default 300 if !(SPIRAM && IDF_TARGET_ESP32) 399 default 800 if (SPIRAM && IDF_TARGET_ESP32) 400 range 10 10000 401 help 402 The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. 403 404 config ESP_INT_WDT_CHECK_CPU1 405 bool "Also watch CPU1 tick interrupt" 406 depends on ESP_INT_WDT && !FREERTOS_UNICORE 407 default y 408 help 409 Also detect if interrupts on CPU 1 are disabled for too long. 410 411 config ESP_TASK_WDT_EN 412 bool "Enable Task Watchdog Timer" 413 default y 414 select FREERTOS_ENABLE_TASK_SNAPSHOT 415 help 416 The Task Watchdog Timer can be used to make sure individual tasks are still 417 running. Enabling this option will enable the Task Watchdog Timer. It can be 418 either initialized automatically at startup or initialized after startup 419 (see Task Watchdog Timer API Reference) 420 421 config ESP_TASK_WDT_USE_ESP_TIMER 422 # Software implementation of Task Watchdog, handy for targets with only a single 423 # Timer Group, such as the ESP32-C2 424 bool 425 depends on ESP_TASK_WDT_EN 426 default y if IDF_TARGET_ESP32C2 427 default n if !IDF_TARGET_ESP32C2 428 select ESP_TIMER_SUPPORTS_ISR_DISPATCH_METHOD 429 430 config ESP_TASK_WDT_INIT 431 bool "Initialize Task Watchdog Timer on startup" 432 depends on ESP_TASK_WDT_EN 433 default y 434 help 435 Enabling this option will cause the Task Watchdog Timer to be initialized 436 automatically at startup. 437 438 config ESP_TASK_WDT_PANIC 439 bool "Invoke panic handler on Task Watchdog timeout" 440 depends on ESP_TASK_WDT_INIT 441 default n 442 help 443 If this option is enabled, the Task Watchdog Timer will be configured to 444 trigger the panic handler when it times out. This can also be configured 445 at run time (see Task Watchdog Timer API Reference) 446 447 config ESP_TASK_WDT_TIMEOUT_S 448 int "Task Watchdog timeout period (seconds)" 449 depends on ESP_TASK_WDT_INIT 450 range 1 60 451 default 5 452 help 453 Timeout period configuration for the Task Watchdog Timer in seconds. 454 This is also configurable at run time (see Task Watchdog Timer API Reference) 455 456 config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 457 bool "Watch CPU0 Idle Task" 458 depends on ESP_TASK_WDT_INIT 459 default y 460 help 461 If this option is enabled, the Task Watchdog Timer will watch the CPU0 462 Idle Task. Having the Task Watchdog watch the Idle Task allows for detection 463 of CPU starvation as the Idle Task not being called is usually a symptom of 464 CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household 465 tasks depend on the Idle Task getting some runtime every now and then. 466 467 config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 468 bool "Watch CPU1 Idle Task" 469 depends on ESP_TASK_WDT_INIT && !FREERTOS_UNICORE 470 default y 471 help 472 If this option is enabled, the Task Watchdog Timer will wach the CPU1 473 Idle Task. 474 475 config ESP_XT_WDT 476 bool "Initialize XTAL32K watchdog timer on startup" 477 depends on !IDF_TARGET_ESP32 && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL) 478 default n 479 help 480 This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure 481 is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate 482 an interrupt. 483 484 config ESP_XT_WDT_TIMEOUT 485 int "XTAL32K watchdog timeout period" 486 depends on ESP_XT_WDT 487 range 1 255 488 default 200 489 help 490 Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK. 491 492 config ESP_XT_WDT_BACKUP_CLK_ENABLE 493 bool "Automatically switch to BACKUP32K_CLK when timer expires" 494 depends on ESP_XT_WDT 495 default y 496 help 497 Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when 498 the watchdog timer expires. 499 500 config ESP_PANIC_HANDLER_IRAM 501 bool "Place panic handler code in IRAM" 502 default n 503 help 504 If this option is disabled (default), the panic handler code is placed in flash not IRAM. 505 This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will 506 automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor 507 risk, if the flash cache status is also corrupted during the crash. 508 509 If this option is enabled, the panic handler code (including required UART functions) is placed 510 in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is 511 disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception 512 is triggered. 513 514 config ESP_DEBUG_STUBS_ENABLE 515 bool "OpenOCD debug stubs" 516 default COMPILER_OPTIMIZATION_LEVEL_DEBUG 517 depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX 518 help 519 Debug stubs are used by OpenOCD to execute pre-compiled onboard code 520 which does some useful debugging stuff, e.g. GCOV data dump. 521 522 config ESP_DEBUG_OCDAWARE 523 bool "Make exception and panic handlers JTAG/OCD aware" 524 default y 525 select FREERTOS_DEBUG_OCDAWARE 526 help 527 The FreeRTOS panic and unhandled exception handers can detect a JTAG OCD debugger and 528 instead of panicking, have the debugger stop on the offending instruction. 529 530 choice ESP_SYSTEM_CHECK_INT_LEVEL 531 prompt "Interrupt level to use for Interrupt Watchdog and other system checks" 532 default ESP_SYSTEM_CHECK_INT_LEVEL_4 533 help 534 Interrupt level to use for Interrupt Watchdog and other system checks. 535 536 config ESP_SYSTEM_CHECK_INT_LEVEL_5 537 bool "Level 5 interrupt" 538 depends on IDF_TARGET_ESP32 539 help 540 Using level 5 interrupt for Interrupt Watchdog and other system checks. 541 542 config ESP_SYSTEM_CHECK_INT_LEVEL_4 543 bool "Level 4 interrupt" 544 depends on !BTDM_CTRL_HLI 545 help 546 Using level 4 interrupt for Interrupt Watchdog and other system checks. 547 endchoice 548 549 # Insert chip-specific system config 550 rsource "./port/soc/$IDF_TARGET/Kconfig.system" 551 552 config ESP_SYSTEM_BROWNOUT_INTR 553 bool 554 default n 555 help 556 This config allows to trigger an interrupt when brownout detected. Software restart will be done 557 at the end of the default callback. 558 Two occasions need to restart the chip with interrupt so far. 559 (1). For ESP32 version 1, brown-out reset function doesn't work (see ESP32 errata 3.4). 560 So that we must restart from interrupt. 561 (2). For special workflow, the chip needs do more things instead of restarting directly. This part 562 needs to be done in callback function of interrupt. 563 564endmenu # ESP System Settings 565 566menu "IPC (Inter-Processor Call)" 567 568 config ESP_IPC_TASK_STACK_SIZE 569 int "Inter-Processor Call (IPC) task stack size" 570 range 512 65536 if !APPTRACE_ENABLE 571 range 2048 65536 if APPTRACE_ENABLE 572 default 2048 if APPTRACE_ENABLE 573 default 1280 if !APPTRACE_ENABLE && IDF_TARGET_ESP32S3 574 default 1024 575 help 576 Configure the IPC tasks stack size. An IPC task runs on each core (in dual core mode), and allows for 577 cross-core function calls. See IPC documentation for more details. The default IPC stack size should be 578 enough for most common simple use cases. However, users can increase/decrease the stack size to their 579 needs. 580 581 config ESP_IPC_USES_CALLERS_PRIORITY 582 bool "IPC runs at caller's priority" 583 default y 584 depends on !FREERTOS_UNICORE 585 help 586 If this option is not enabled then the IPC task will keep behavior same as prior to that of ESP-IDF v4.0, 587 hence IPC task will run at (configMAX_PRIORITIES - 1) priority. 588 589 config ESP_IPC_ISR_ENABLE 590 bool 591 default y if !FREERTOS_UNICORE 592 help 593 The IPC ISR feature is similar to the IPC feature except that the callback function is executed in the 594 context of a High Priority Interrupt. The IPC ISR feature is itended for low latency execution of simple 595 callbacks written in assembly on another CPU. Due to being run in a High Priority Interrupt, the assembly 596 callbacks must be written with particular restrictions (see "IPC" and "High-Level Interrupt" docs for more 597 details). 598 599endmenu # "IPC (Inter-Processor Call) 600
