1 2menu "ESP System Settings" 3 4 choice ESP_SYSTEM_PANIC 5 prompt "Panic handler behaviour" 6 default ESP_SYSTEM_PANIC_PRINT_REBOOT 7 help 8 If FreeRTOS detects unexpected behaviour or an unhandled exception, the panic handler is 9 invoked. Configure the panic handler's action here. 10 11 config ESP_SYSTEM_PANIC_PRINT_HALT 12 bool "Print registers and halt" 13 help 14 Outputs the relevant registers over the serial port and halt the 15 processor. Needs a manual reset to restart. 16 17 config ESP_SYSTEM_PANIC_PRINT_REBOOT 18 bool "Print registers and reboot" 19 help 20 Outputs the relevant registers over the serial port and immediately 21 reset the processor. 22 23 config ESP_SYSTEM_PANIC_SILENT_REBOOT 24 bool "Silent reboot" 25 help 26 Just resets the processor without outputting anything 27 28 config ESP_SYSTEM_PANIC_GDBSTUB 29 bool "GDBStub on panic" 30 select ESP_GDBSTUB_ENABLED 31 help 32 Invoke gdbstub on the serial port, allowing for gdb to attach to it to do a postmortem 33 of the crash. 34 35 config ESP_SYSTEM_GDBSTUB_RUNTIME 36 bool "GDBStub at runtime" 37 select FREERTOS_UNICORE 38 select ESP_GDBSTUB_ENABLED 39 help 40 Invoke gdbstub on the serial port, allowing for gdb to attach to it and to do a debug on runtime. 41 This feature will switch system to single core mode. 42 endchoice 43 44 config ESP_SYSTEM_SINGLE_CORE_MODE 45 bool 46 default n 47 help 48 Only initialize and use the main core. 49 50 config ESP_SYSTEM_RTC_EXT_XTAL 51 # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option 52 # e.g. It will be selected on when ESP32_RTC_CLK_SRC_EXT_CRYS is on 53 bool 54 default n 55 56 config ESP_SYSTEM_RTC_EXT_OSC 57 # This is a High Layer Kconfig option, invisible, can be selected by other Kconfig option 58 # e.g. It will be selected on when ESPX_RTC_CLK_SRC_EXT_OSC is on 59 bool 60 default n 61 62 config ESP_SYSTEM_RTC_EXT_XTAL_BOOTSTRAP_CYCLES 63 int "Bootstrap cycles for external 32kHz crystal" 64 depends on ESP_SYSTEM_RTC_EXT_XTAL 65 default 5 if IDF_TARGET_ESP32 66 default 0 67 range 0 32768 68 help 69 To reduce the startup time of an external RTC crystal, 70 we bootstrap it with a 32kHz square wave for a fixed number of cycles. 71 Setting 0 will disable bootstrapping (if disabled, the crystal may take 72 longer to start up or fail to oscillate under some conditions). 73 74 If this value is too high, a faulty crystal may initially start and then fail. 75 If this value is too low, an otherwise good crystal may not start. 76 77 To accurately determine if the crystal has started, 78 set a larger "Number of cycles for RTC_SLOW_CLK calibration" (about 3000). 79 80 config ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 81 bool 82 default y if IDF_TARGET_ESP32 && FREERTOS_UNICORE 83 default y if IDF_TARGET_ESP32S2 84 default y if IDF_TARGET_ESP32C3 85 default y if IDF_TARGET_ESP32S3 86 default y if IDF_TARGET_ESP32H2 87 88 config ESP_SYSTEM_ALLOW_RTC_FAST_MEM_AS_HEAP 89 bool "Enable RTC fast memory for dynamic allocations" 90 default y 91 depends on ESP_SYSTEM_RTC_FAST_MEM_AS_HEAP_DEPCHECK 92 help 93 This config option allows to add RTC fast memory region to system heap with capability 94 similar to that of DRAM region but without DMA. This memory will be consumed first per 95 heap initialization order by early startup services and scheduler related code. Speed 96 wise RTC fast memory operates on APB clock and hence does not have much performance impact. 97 98 config ESP_SYSTEM_USE_EH_FRAME 99 bool "Generate and use eh_frame for backtracing" 100 default n 101 depends on IDF_TARGET_ARCH_RISCV 102 help 103 Generate DWARF information for each function of the project. These information will parsed and used to 104 perform backtracing when panics occur. Activating this option will activate asynchronous frame unwinding 105 and generation of both .eh_frame and .eh_frame_hdr sections, resulting in a bigger binary size (20% to 106 100% larger). The main purpose of this option is to be able to have a backtrace parsed and printed by 107 the program itself, regardless of the serial monitor used. 108 This option shall NOT be used for production. 109 110 menu "Memory protection" 111 112 config ESP_SYSTEM_MEMPROT_DEPCHECK 113 bool 114 default y if IDF_TARGET_ESP32S2 115 default y if IDF_TARGET_ESP32C3 116 default y if IDF_TARGET_ESP32H2 117 118 config ESP_SYSTEM_MEMPROT_FEATURE 119 bool "Enable memory protection" 120 depends on ESP_SYSTEM_MEMPROT_DEPCHECK 121 default "y" 122 help 123 If enabled, the permission control module watches all the memory access and fires the panic handler 124 if a permission violation is detected. This feature automatically splits 125 the SRAM memory into data and instruction segments and sets Read/Execute permissions 126 for the instruction part (below given splitting address) and Read/Write permissions 127 for the data part (above the splitting address). The memory protection is effective 128 on all access through the IRAM0 and DRAM0 buses. 129 130 config ESP_SYSTEM_MEMPROT_FEATURE_LOCK 131 depends on ESP_SYSTEM_MEMPROT_FEATURE 132 bool "Lock memory protection settings" 133 default "y" 134 help 135 Once locked, memory protection settings cannot be changed anymore. 136 The lock is reset only on the chip startup. 137 138 config ESP_SYSTEM_MEMPROT_CPU_PREFETCH_PAD_SIZE 139 # Hidden option for linker script usage 140 int 141 depends on ESP_SYSTEM_MEMPROT_DEPCHECK 142 default 16 143 144 config ESP_SYSTEM_MEMPROT_MEM_ALIGN_SIZE 145 # Hidden option for linker script usage 146 int 147 depends on ESP_SYSTEM_MEMPROT_DEPCHECK 148 default 4 if IDF_TARGET_ESP32S2 149 default 256 if IDF_TARGET_ESP32S3 150 default 512 151 152 endmenu # Memory protection 153 154 config ESP_SYSTEM_EVENT_QUEUE_SIZE 155 int "System event queue size" 156 default 32 157 help 158 Config system event queue size in different application. 159 160 config ESP_SYSTEM_EVENT_TASK_STACK_SIZE 161 int "Event loop task stack size" 162 default 2304 163 help 164 Config system event task stack size in different application. 165 166 config ESP_MAIN_TASK_STACK_SIZE 167 int "Main task stack size" 168 default 3584 169 help 170 Configure the "main task" stack size. This is the stack of the task 171 which calls app_main(). If app_main() returns then this task is deleted 172 and its stack memory is freed. 173 174 choice ESP_MAIN_TASK_AFFINITY 175 prompt "Main task core affinity" 176 default ESP_MAIN_TASK_AFFINITY_CPU0 177 help 178 Configure the "main task" core affinity. This is the used core of the task 179 which calls app_main(). If app_main() returns then this task is deleted. 180 181 config ESP_MAIN_TASK_AFFINITY_CPU0 182 bool "CPU0" 183 config ESP_MAIN_TASK_AFFINITY_CPU1 184 bool "CPU1" 185 depends on !FREERTOS_UNICORE 186 config ESP_MAIN_TASK_AFFINITY_NO_AFFINITY 187 bool "No affinity" 188 189 endchoice 190 191 config ESP_MAIN_TASK_AFFINITY 192 hex 193 default 0x0 if ESP_MAIN_TASK_AFFINITY_CPU0 194 default 0x1 if ESP_MAIN_TASK_AFFINITY_CPU1 195 default FREERTOS_NO_AFFINITY if ESP_MAIN_TASK_AFFINITY_NO_AFFINITY 196 197 config ESP_MINIMAL_SHARED_STACK_SIZE 198 int "Minimal allowed size for shared stack" 199 default 2048 200 help 201 Minimal value of size, in bytes, accepted to execute a expression 202 with shared stack. 203 204 choice ESP_CONSOLE_UART 205 prompt "Channel for console output" 206 default ESP_CONSOLE_UART_DEFAULT 207 help 208 Select where to send console output (through stdout and stderr). 209 210 - Default is to use UART0 on pre-defined GPIOs. 211 - If "Custom" is selected, UART0 or UART1 can be chosen, 212 and any pins can be selected. 213 - If "None" is selected, there will be no console output on any UART, except 214 for initial output from ROM bootloader. This ROM output can be suppressed by 215 GPIO strapping or EFUSE, refer to chip datasheet for details. 216 - On chips with USB OTG peripheral, "USB CDC" option redirects output to the 217 CDC port. This option uses the CDC driver in the chip ROM. 218 This option is incompatible with TinyUSB stack. 219 - On chips with an USB serial/JTAG debug controller, selecting the option 220 for that redirects output to the CDC/ACM (serial port emulation) component 221 of that device. 222 config ESP_CONSOLE_UART_DEFAULT 223 bool "Default: UART0" 224 config ESP_CONSOLE_USB_CDC 225 bool "USB CDC" 226 # && !TINY_USB is because the ROM CDC driver is currently incompatible with TinyUSB. 227 depends on (IDF_TARGET_ESP32S2 || IDF_TARGET_ESP32S3) && !TINY_USB 228 config ESP_CONSOLE_USB_SERIAL_JTAG 229 bool "USB Serial/JTAG Controller" 230 select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32S3 #ESPTOOL-251 231 select ESPTOOLPY_NO_STUB if IDF_TARGET_ESP32C3 #ESPTOOL-252 232 depends on IDF_TARGET_ESP32C3 || IDF_TARGET_ESP32S3 233 config ESP_CONSOLE_UART_CUSTOM 234 bool "Custom UART" 235 config ESP_CONSOLE_NONE 236 bool "None" 237 endchoice 238 239 choice ESP_CONSOLE_SECONDARY 240 depends on IDF_TARGET_ESP32S3 || IDF_TARGET_ESP32C3 241 prompt "Channel for console secondary output" 242 default ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 243 help 244 This secondary option supports output through other specific port like USB_SERIAL_JTAG 245 when UART0 port as a primary is selected but not connected. This secondary output currently only supports 246 non-blocking mode without using REPL. If you want to output in blocking mode with REPL or 247 input through this secondary port, please change the primary config to this port 248 in `Channel for console output` menu. 249 config ESP_CONSOLE_SECONDARY_NONE 250 bool "No secondary console" 251 config ESP_CONSOLE_SECONDARY_USB_SERIAL_JTAG 252 bool "USB_SERIAL_JTAG PORT" 253 depends on !ESP_CONSOLE_USB_SERIAL_JTAG 254 help 255 This option supports output through USB_SERIAL_JTAG port when the UART0 port is not connected. 256 The output currently only supports non-blocking mode without using the console. 257 If you want to output in blocking mode with REPL or input through USB_SERIAL_JTAG port, 258 please change the primary config to ESP_CONSOLE_USB_SERIAL_JTAG above. 259 endchoice 260 261 262 config ESP_CONSOLE_UART 263 # Internal option, indicates that console UART is used (and not USB, for example) 264 bool 265 default y if ESP_CONSOLE_UART_DEFAULT || ESP_CONSOLE_UART_CUSTOM 266 267 config ESP_CONSOLE_MULTIPLE_UART 268 bool 269 default y if !IDF_TARGET_ESP32C3 && !IDF_TARGET_ESP32H2 270 271 choice ESP_CONSOLE_UART_NUM 272 prompt "UART peripheral to use for console output (0-1)" 273 depends on ESP_CONSOLE_UART_CUSTOM && ESP_CONSOLE_MULTIPLE_UART 274 default ESP_CONSOLE_UART_CUSTOM_NUM_0 275 help 276 This UART peripheral is used for console output from the ESP-IDF Bootloader and the app. 277 278 If the configuration is different in the Bootloader binary compared to the app binary, UART 279 is reconfigured after the bootloader exits and the app starts. 280 281 Due to an ESP32 ROM bug, UART2 is not supported for console output 282 via esp_rom_printf. 283 284 config ESP_CONSOLE_UART_CUSTOM_NUM_0 285 bool "UART0" 286 config ESP_CONSOLE_UART_CUSTOM_NUM_1 287 bool "UART1" 288 endchoice 289 290 config ESP_CONSOLE_UART_NUM 291 int 292 default 0 if ESP_CONSOLE_UART_DEFAULT 293 default 0 if !ESP_CONSOLE_MULTIPLE_UART 294 default 0 if ESP_CONSOLE_UART_CUSTOM_NUM_0 295 default 1 if ESP_CONSOLE_UART_CUSTOM_NUM_1 296 default -1 if !ESP_CONSOLE_UART 297 298 config ESP_CONSOLE_UART_TX_GPIO 299 int "UART TX on GPIO#" 300 depends on ESP_CONSOLE_UART_CUSTOM 301 range 0 46 302 default 1 if IDF_TARGET_ESP32 303 default 21 if IDF_TARGET_ESP32C3 304 default 43 305 help 306 This GPIO is used for console UART TX output in the ESP-IDF Bootloader and the app (including 307 boot log output and default standard output and standard error of the app). 308 309 If the configuration is different in the Bootloader binary compared to the app binary, UART 310 is reconfigured after the bootloader exits and the app starts. 311 312 config ESP_CONSOLE_UART_RX_GPIO 313 int "UART RX on GPIO#" 314 depends on ESP_CONSOLE_UART_CUSTOM 315 range 0 46 316 default 3 if IDF_TARGET_ESP32 317 default 20 if IDF_TARGET_ESP32C3 318 default 44 319 help 320 This GPIO is used for UART RX input in the ESP-IDF Bootloader and the app (including 321 default default standard input of the app). 322 323 Note: The default ESP-IDF Bootloader configures this pin but doesn't read anything from the UART. 324 325 If the configuration is different in the Bootloader binary compared to the app binary, UART 326 is reconfigured after the bootloader exits and the app starts. 327 328 329 config ESP_CONSOLE_UART_BAUDRATE 330 int 331 prompt "UART console baud rate" if ESP_CONSOLE_UART_CUSTOM 332 depends on ESP_CONSOLE_UART 333 default 115200 334 range 1200 4000000 if !PM_ENABLE 335 range 1200 1000000 if PM_ENABLE 336 help 337 This baud rate is used by both the ESP-IDF Bootloader and the app (including 338 boot log output and default standard input/output/error of the app). 339 340 The app's maximum baud rate depends on the UART clock source. If Power Management is disabled, 341 the UART clock source is the APB clock and all baud rates in the available range will be sufficiently 342 accurate. If Power Management is enabled, REF_TICK clock source is used so the baud rate is divided 343 from 1MHz. Baud rates above 1Mbps are not possible and values between 500Kbps and 1Mbps may not be 344 accurate. 345 346 If the configuration is different in the Bootloader binary compared to the app binary, UART 347 is reconfigured after the bootloader exits and the app starts. 348 349 config ESP_CONSOLE_USB_CDC_RX_BUF_SIZE 350 int "Size of USB CDC RX buffer" 351 depends on ESP_CONSOLE_USB_CDC 352 default 64 353 range 4 16384 354 help 355 Set the size of USB CDC RX buffer. Increase the buffer size if your application 356 is often receiving data over USB CDC. 357 358 config ESP_CONSOLE_USB_CDC_SUPPORT_ETS_PRINTF 359 bool "Enable esp_rom_printf / ESP_EARLY_LOG via USB CDC" 360 depends on ESP_CONSOLE_USB_CDC 361 default n 362 help 363 If enabled, esp_rom_printf and ESP_EARLY_LOG output will also be sent over USB CDC. 364 Disabling this option saves about 1kB or RAM. 365 366 config ESP_INT_WDT 367 bool "Interrupt watchdog" 368 default y 369 help 370 This watchdog timer can detect if the FreeRTOS tick interrupt has not been called for a certain time, 371 either because a task turned off interrupts and did not turn them on for a long time, or because an 372 interrupt handler did not return. It will try to invoke the panic handler first and failing that 373 reset the SoC. 374 375 config ESP_INT_WDT_TIMEOUT_MS 376 int "Interrupt watchdog timeout (ms)" 377 depends on ESP_INT_WDT 378 default 300 if !ESP32_SPIRAM_SUPPORT 379 default 800 if ESP32_SPIRAM_SUPPORT 380 range 10 10000 381 help 382 The timeout of the watchdog, in miliseconds. Make this higher than the FreeRTOS tick rate. 383 384 config ESP_INT_WDT_CHECK_CPU1 385 bool "Also watch CPU1 tick interrupt" 386 depends on ESP_INT_WDT && !FREERTOS_UNICORE 387 default y 388 help 389 Also detect if interrupts on CPU 1 are disabled for too long. 390 391 config ESP_TASK_WDT 392 bool "Initialize Task Watchdog Timer on startup" 393 default y 394 help 395 The Task Watchdog Timer can be used to make sure individual tasks are still 396 running. Enabling this option will cause the Task Watchdog Timer to be 397 initialized automatically at startup. The Task Watchdog timer can be 398 initialized after startup as well (see Task Watchdog Timer API Reference) 399 400 config ESP_TASK_WDT_PANIC 401 bool "Invoke panic handler on Task Watchdog timeout" 402 depends on ESP_TASK_WDT 403 default n 404 help 405 If this option is enabled, the Task Watchdog Timer will be configured to 406 trigger the panic handler when it times out. This can also be configured 407 at run time (see Task Watchdog Timer API Reference) 408 409 config ESP_TASK_WDT_TIMEOUT_S 410 int "Task Watchdog timeout period (seconds)" 411 depends on ESP_TASK_WDT 412 range 1 60 413 default 5 414 help 415 Timeout period configuration for the Task Watchdog Timer in seconds. 416 This is also configurable at run time (see Task Watchdog Timer API Reference) 417 418 config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU0 419 bool "Watch CPU0 Idle Task" 420 depends on ESP_TASK_WDT 421 default y 422 help 423 If this option is enabled, the Task Watchdog Timer will watch the CPU0 424 Idle Task. Having the Task Watchdog watch the Idle Task allows for detection 425 of CPU starvation as the Idle Task not being called is usually a symptom of 426 CPU starvation. Starvation of the Idle Task is detrimental as FreeRTOS household 427 tasks depend on the Idle Task getting some runtime every now and then. 428 429 config ESP_TASK_WDT_CHECK_IDLE_TASK_CPU1 430 bool "Watch CPU1 Idle Task" 431 depends on ESP_TASK_WDT && !FREERTOS_UNICORE 432 default y 433 help 434 If this option is enabled, the Task Wtachdog Timer will wach the CPU1 435 Idle Task. 436 437 config ESP_XT_WDT 438 bool "Initialize XTAL32K watchdog timer on startup" 439 depends on !IDF_TARGET_ESP32 && (ESP_SYSTEM_RTC_EXT_OSC || ESP_SYSTEM_RTC_EXT_XTAL) 440 default n 441 help 442 This watchdog timer can detect oscillation failure of the XTAL32K_CLK. When such a failure 443 is detected the hardware can be set up to automatically switch to BACKUP32K_CLK and generate 444 an interrupt. 445 446 config ESP_XT_WDT_TIMEOUT 447 int "XTAL32K watchdog timeout period" 448 depends on ESP_XT_WDT 449 range 1 255 450 default 200 451 help 452 Timeout period configuration for the XTAL32K watchdog timer based on RTC_CLK. 453 454 config ESP_XT_WDT_BACKUP_CLK_ENABLE 455 bool "Automatically switch to BACKUP32K_CLK when timer expires" 456 depends on ESP_XT_WDT 457 default y 458 help 459 Enable this to automatically switch to BACKUP32K_CLK as the source of RTC_SLOW_CLK when 460 the watchdog timer expires. 461 462 config ESP_PANIC_HANDLER_IRAM 463 bool "Place panic handler code in IRAM" 464 default n 465 help 466 If this option is disabled (default), the panic handler code is placed in flash not IRAM. 467 This means that if ESP-IDF crashes while flash cache is disabled, the panic handler will 468 automatically re-enable flash cache before running GDB Stub or Core Dump. This adds some minor 469 risk, if the flash cache status is also corrupted during the crash. 470 471 If this option is enabled, the panic handler code (including required UART functions) is placed 472 in IRAM. This may be necessary to debug some complex issues with crashes while flash cache is 473 disabled (for example, when writing to SPI flash) or when flash cache is corrupted when an exception 474 is triggered. 475 476 config ESP_DEBUG_STUBS_ENABLE 477 bool "OpenOCD debug stubs" 478 default COMPILER_OPTIMIZATION_LEVEL_DEBUG 479 depends on !ESP32_TRAX && !ESP32S2_TRAX && !ESP32S3_TRAX 480 help 481 Debug stubs are used by OpenOCD to execute pre-compiled onboard code 482 which does some useful debugging stuff, e.g. GCOV data dump. 483 484 choice ESP_SYSTEM_CHECK_INT_LEVEL 485 prompt "Interrupt level to use for Interrupt Watchdog and other system checks" 486 default ESP_SYSTEM_CHECK_INT_LEVEL_4 487 help 488 Interrupt level to use for Interrupt Watchdog and other system checks. 489 490 config ESP_SYSTEM_CHECK_INT_LEVEL_5 491 bool "Level 5 interrupt" 492 depends on IDF_TARGET_ESP32 493 help 494 Using level 5 interrupt for Interrupt Watchdog and other system checks. 495 496 config ESP_SYSTEM_CHECK_INT_LEVEL_4 497 bool "Level 4 interrupt" 498 depends on !BTDM_CTRL_HLI 499 help 500 Using level 4 interrupt for Interrupt Watchdog and other system checks. 501 endchoice 502 503endmenu # ESP System Settings 504
