1# Copyright (c) 2019 Intel Corporation
2# SPDX-License-Identifier: Apache-2.0
3
4config DW_ICTL_ACE
5	bool "Designware Interrupt Controller for ACE"
6	default y
7	depends on DT_HAS_INTEL_ACE_INTC_ENABLED
8	depends on MULTI_LEVEL_INTERRUPTS
9	help
10	  Designware Interrupt Controller used by ACE.
11
12menuconfig DW_ICTL
13	bool "Designware Interrupt Controller"
14	default y
15	depends on DT_HAS_SNPS_DESIGNWARE_INTC_ENABLED
16	depends on MULTI_LEVEL_INTERRUPTS
17	help
18	  Designware Interrupt Controller can be used as a 2nd level interrupt
19	  controller which combines several sources of interrupt into one line
20	  that is then routed to the 1st level interrupt controller.
21
22
23if DW_ICTL
24
25config DW_ICTL_NAME
26	string "Name for Designware Interrupt Controller"
27	default "DW_ICTL"
28	help
29	  Give a name for the instance of Designware Interrupt Controller
30
31config DW_ISR_TBL_OFFSET
32	int "Offset in the SW ISR Table"
33	default 0
34	help
35	  This indicates the offset in the SW_ISR_TABLE beginning from where
36	  the ISRs for Designware Interrupt Controller are assigned.
37
38config DW_ICTL_INIT_PRIORITY
39	int "Init priority for DW interrupt controller"
40	default 48
41	help
42	  DesignWare Interrupt Controller initialization priority.
43
44endif # DW_ICTL
45