1# ARM architecture configuration options
2
3# Copyright (c) 2014-2015 Wind River Systems, Inc.
4# SPDX-License-Identifier: Apache-2.0
5
6menu "ARM Options"
7	depends on ARM
8
9config ARCH
10	default "arm"
11
12config CPU_CORTEX
13	bool
14	help
15	  This option signifies the use of a CPU of the Cortex family.
16
17config ARM_CUSTOM_INTERRUPT_CONTROLLER
18	bool
19	help
20	  This option indicates that the ARM CPU is connected to a custom (i.e.
21	  non-GIC or NVIC) interrupt controller.
22
23	  A number of Cortex-A and Cortex-R cores (Cortex-A5, Cortex-R4/5, ...)
24	  allow interfacing to a custom external interrupt controller and this
25	  option must be selected when such cores are connected to an interrupt
26	  controller that is not the ARM Generic Interrupt Controller (GIC) or
27	  the Cortex-M ARM Nested Vectored Interrupt Controller (NVIC).
28
29	  When this option is selected, the architecture interrupt control
30	  functions are mapped to the SoC interrupt control interface, which is
31	  implemented at the SoC level.
32
33	  N.B. Since all Cortex-M cores have a NVIC, if this option is selected it
34	  is assumed that the custom interrupt control interface implementation
35	  assumes responsibility for handling the NVIC.
36
37config ROMSTART_RELOCATION_ROM
38	bool "Relocate rom_start region"
39	default n
40	help
41	  Relocates the rom_start region containing the boot-vector data and
42	  irq vectors to the region specified by configurations:
43	  ROMSTART_REGION_ADDRESS and ROMSTART_REGION_SIZE
44
45	  This is useful for the Linux Remoteproc framework that uses the elf-loader
46	  such that it is able to load the correct boot-vector (contained in rom_start)
47	  into the correct memory location independent of the chosen zephyr,flash
48	  ROM region.
49
50	  Most SOCs include an alias for the boot-vector at address 0x00000000
51	  so a default which might be supported by the corresponding Linux rproc driver.
52	  If it is not, additionnal options allows to specify the addresses.
53
54	  In general this option should be chosen if the zephyr,flash chosen node
55	  is not placed into the boot-vector memory area.
56
57	  While this aims at generating a correct zephyr.elf file, it has the side
58	  effect of enlarging the bin file. If the zephyr.bin file is used to boot the
59	  secondary core, this option should be disabled.
60
61	  Example:
62		on IMX7D, the chosen zephyr,flash can be OCRAM/OCRAM_S/TCM/DDR memories
63		for code location. But the boot-vector must be placed into OCRAM_S for the
64		CORTEX-M to boot (alias 0, real 0x00180000/32K available).
65
66if ROMSTART_RELOCATION_ROM
67
68	config ROMSTART_REGION_ADDRESS
69		hex "Base address of the rom_start region"
70		default 0x00000000
71		help
72		  Start address of the rom_start region.
73		  This setting can be derived from a DT node reg property or specified directly.
74
75		  A default value of 0x00000000 might work in most cases as SOCs have an alias
76		  to the right memory region of the boot-vector.
77
78		  Examples:
79		  -IMX7D the boot-vector is OCRAM_S (0x00180000, aliased at 0x0).
80		  -IMX6SX the boot-vector is TCML (0x007F8000, aliased at 0x0).
81		  -IMX8MQ the boot-vector is TCML (0x007E0000, aliased at 0x0).
82		  -IMX8MN the boot-vector is ITCM (0x007E0000, aliased at 0x0).
83
84		  Example of DT definition:
85		  $(dt_nodelabel_reg_addr_hex,ocram_s_sys)
86
87	config ROMSTART_REGION_SIZE
88		hex "Size of the rom_start region"
89		default 1
90		help
91		  Size of the rom_start region in KB.
92
93		  Default is 1KB which is enough to store the boot and irq vectors.
94
95		  This setting can be derived from a DT node reg property or specified directly.
96
97		  Example for IMX7D that needs the boot-vector into OCRAM_S (0x00180000):
98		  $(dt_nodelabel_reg_size_hex,ocram_s_sys,0,K)
99
100endif
101
102config CODE_DATA_RELOCATION_SRAM
103	bool "Relocate code/data sections to SRAM"
104	depends on CPU_CORTEX_M
105	select CODE_DATA_RELOCATION
106	help
107	  When selected this will relocate .text, data and .bss sections from
108	  the specified files and places it in SRAM. The files should be specified
109	  in the CMakeList.txt file with a cmake API zephyr_code_relocate(). This
110	  config is used to create an MPU entry for the SRAM space used for code
111	  relocation.
112
113config ARM_ON_ENTER_CPU_IDLE_HOOK
114	bool
115	help
116	  Enables a hook (z_arm_on_enter_cpu_idle()) that is called when
117	  the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
118	  If needed, this hook can be used to prevent the CPU from actually
119	  entering sleep by skipping the WFE/WFI instruction.
120
121config ARM_ON_ENTER_CPU_IDLE_PREPARE_HOOK
122	bool
123	help
124	  Enables a hook (z_arm_on_enter_cpu_idle_prepare()) that is called when
125	  the CPU is made idle (by k_cpu_idle() or k_cpu_atomic_idle()).
126	  If needed, this hook can prepare data to upcoming call to
127	  z_arm_on_enter_cpu_idle(). The z_arm_on_enter_cpu_idle_prepare differs
128	  from z_arm_on_enter_cpu_idle because it is called before interrupts are
129	  disabled.
130
131config ARM_ON_EXIT_CPU_IDLE
132	bool
133	help
134	  Enables a possibility to inject SoC-specific code just after WFI/WFE
135	  instructions of the cpu idle implementation.
136
137	  Enabling this option requires that the SoC provides a soc_cpu_idle.h
138	  header file which defines SOC_ON_EXIT_CPU_IDLE macro guarded by
139	  _ASMLANGUAGE.
140
141	  The SOC_ON_EXIT_CPU_IDLE macro is expanded just after
142	  WFI/WFE instructions before any memory access is performed. The purpose
143	  of the SOC_ON_EXIT_CPU_IDLE is to perform an action that mitigate issues
144	  observed on some SoCs caused by a memory access following WFI/WFE
145	  instructions.
146
147rsource "core/Kconfig"
148rsource "core/Kconfig.vfp"
149
150# General options signifying CPU capabilities of ARM SoCs
151config CPU_HAS_ARM_MPU
152	bool
153	select CPU_HAS_MPU
154	help
155	  This option is enabled when the CPU has a Memory Protection Unit (MPU)
156	  in ARM flavor.
157
158config CPU_HAS_NXP_SYSMPU
159	bool
160	select CPU_HAS_MPU
161	help
162	  This option is enabled when the CPU has an NXP System Memory Protection
163	  Unit (SYSMPU).
164
165config CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
166	bool "Custom fixed SoC MPU region definition"
167	help
168	  If enabled, this option signifies that the SoC will
169	  define and configure its own fixed MPU regions in the
170	  SoC definition. These fixed MPU regions are currently
171	  used to set Flash and SRAM default access policies and
172	  they are programmed at boot time.
173
174config CPU_HAS_ARM_SAU
175	bool
176	select CPU_HAS_TEE
177	help
178	  MCU implements the ARM Security Attribution Unit (SAU).
179
180config CPU_HAS_NRF_IDAU
181	bool
182	select CPU_HAS_TEE
183	help
184	  MCU implements the nRF (vendor-specific) Security Attribution Unit.
185	  (IDAU: "Implementation-Defined Attribution Unit", in accordance with
186	  ARM terminology).
187
188config HAS_SWO
189	bool
190	help
191	  When enabled, indicates that SoC has an SWO output
192
193endmenu
194