1# ARM Cortex-A and Cortex-R platform configuration options
2
3# Copyright (c) 2018 Marvell
4# Copyright (c) 2018 Lexmark International, Inc.
5# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
6#
7# SPDX-License-Identifier: Apache-2.0
8
9# NOTE: We have the specific core implementations first and outside of the
10# if CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R block so that SoCs can
11# select which core they are using without having to select all the options
12# related to that core. Everything else is captured inside the if
13# CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
14# exposed if one selects a different ARM Cortex Family (Cortex-M).
15
16config CPU_CORTEX_A9
17	bool
18	select CPU_AARCH32_CORTEX_A
19	select ARMV7_A
20	help
21	  This option signifies the use of a Cortex-A9 CPU.
22
23if CPU_AARCH32_CORTEX_A
24
25config ARMV7_A
26	bool
27	select ATOMIC_OPERATIONS_BUILTIN
28	select ISA_ARM
29
30config ARMV7_EXCEPTION_STACK_SIZE
31	int "Undefined Instruction and Abort stack size (in bytes)"
32	default 256
33	help
34	  This option specifies the size of the stack used by the undefined
35	  instruction and data abort exception handlers.
36
37config ARMV7_FIQ_STACK_SIZE
38	int "FIQ stack size (in bytes)"
39	default 256
40	help
41	  This option specifies the size of the stack used by the FIQ handler.
42
43config ARMV7_SVC_STACK_SIZE
44	int "SVC stack size (in bytes)"
45	default 512
46	help
47	  This option specifies the size of the stack used by the SVC handler.
48
49config ARMV7_SYS_STACK_SIZE
50	int "SYS stack size (in bytes)"
51	default 1024
52	help
53	  This option specifies the size of the stack used by the system mode.
54
55config RUNTIME_NMI
56	default y
57
58config GEN_ISR_TABLES
59	default y
60
61config GEN_IRQ_VECTOR_TABLE
62	default n
63
64config DCACHE_LINE_SIZE
65	default 32
66
67config ICACHE_LINE_SIZE
68	default 32
69
70endif # CPU_AARCH32_CORTEX_A
71
72config CPU_CORTEX_R4
73	bool
74	select CPU_AARCH32_CORTEX_R
75	select ARMV7_R
76	select ARMV7_R_FP if CPU_HAS_FPU
77	help
78	  This option signifies the use of a Cortex-R4 CPU
79
80config CPU_CORTEX_R5
81	bool
82	select CPU_AARCH32_CORTEX_R
83	select ARMV7_R
84	select ARMV7_R_FP if CPU_HAS_FPU
85	help
86	  This option signifies the use of a Cortex-R5 CPU
87
88config CPU_CORTEX_R7
89	bool
90	select CPU_AARCH32_CORTEX_R
91	select ARMV7_R
92	select ARMV7_R_FP if CPU_HAS_FPU
93	help
94	  This option signifies the use of a Cortex-R7 CPU
95
96config CPU_CORTEX_R8
97	bool
98	select CPU_AARCH32_CORTEX_R
99	select ARMV7_R
100	select ARMV7_R_FP if CPU_HAS_FPU
101	help
102	  This option signifies the use of a Cortex-R8 CPU
103
104config CPU_CORTEX_R52
105	bool
106	select CPU_AARCH32_CORTEX_R
107	select AARCH32_ARMV8_R
108	select CPU_HAS_ICACHE
109	select CPU_HAS_DCACHE
110	select VFP_SP_D16 if !USE_SWITCH
111	help
112	  This option signifies the use of a Cortex-R52 CPU
113
114config CPU_CORTEX_R52_CACHE_SEGREGATION
115	bool "Control segregation of L1 I/D-Cache ways between Flash and AXIM"
116	depends on CPU_CORTEX_R52
117	help
118	  Control segregation of L1 I/D-Cache ways between Flash and AXIM.
119	  Updates to the cache segregation controls are only permitted before the caches
120	  have ever been enabled, following a system reset, otherwise the update is ignored.
121
122config CPU_CORTEX_R52_ICACHE_FLASH_WAY
123	int "L1 I-Cache Flash way"
124	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
125	range 0 4
126	default 0
127	help
128	  Configure L1 I-Cache ways for Flash interface. Default is reset value, all
129	  I-Cache ways are allocated for AXIM interface.
130
131config CPU_CORTEX_R52_DCACHE_FLASH_WAY
132	int "L1 D-Cache Flash way"
133	depends on CPU_CORTEX_R52_CACHE_SEGREGATION
134	range 0 4
135	default 0
136	help
137	  Configure L1 D-Cache ways for Flash interface. Default is reset value,
138	  all D-Cache ways are allocated for AXIM interface.
139
140if CPU_AARCH32_CORTEX_R
141
142config ARMV7_R
143	bool
144	select ATOMIC_OPERATIONS_BUILTIN
145	select ISA_ARM
146	select ISA_THUMB2
147	help
148	  This option signifies the use of an ARMv7-R processor
149	  implementation.
150
151	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
152	  The Armv7-R architecture implements a traditional Arm architecture with
153	  multiple modes and supports a Protected Memory System Architecture
154	  (PMSA) based on a Memory Protection Unit (MPU). It supports the Arm (32)
155	  and Thumb (T32) instruction sets.
156
157config ARMV7_R_FP
158	bool
159	depends on ARMV7_R
160	help
161	  This option signifies the use of an ARMv7-R processor
162	  implementation supporting the Floating-Point Extension.
163
164config AARCH32_ARMV8_R
165	bool
166	select ATOMIC_OPERATIONS_BUILTIN
167	select SCHED_IPI_SUPPORTED if SMP
168	select ARCH_HAS_DIRECTED_IPIS
169	help
170	  This option signifies the use of an ARMv8-R AArch32 processor
171	  implementation.
172
173	  From https://developer.arm.com/products/architecture/cpu-architecture/r-profile:
174	  The Armv8-R architecture targets at the Real-time profile. It introduces
175	  virtualization at the highest security level while retaining the
176	  Protected Memory System Architecture (PMSA) based on a Memory Protection
177	  Unit (MPU). It supports the A32 and T32 instruction sets.
178
179config ARMV7_EXCEPTION_STACK_SIZE
180	int "Undefined Instruction and Abort stack size (in bytes)"
181	default 256
182	help
183	  This option specifies the size of the stack used by the undefined
184	  instruction and data abort exception handlers.
185
186config ARMV7_FIQ_STACK_SIZE
187	int "FIQ stack size (in bytes)"
188	default 256
189	help
190	  This option specifies the size of the stack used by the FIQ handler.
191
192config ARMV7_SVC_STACK_SIZE
193	int "SVC stack size (in bytes)"
194	default 512
195	help
196	  This option specifies the size of the stack used by the SVC handler.
197
198config ARMV7_SYS_STACK_SIZE
199	int "SYS stack size (in bytes)"
200	default 1024
201	help
202	  This option specifies the size of the stack used by the system mode.
203
204config RUNTIME_NMI
205	default y
206
207config GEN_ISR_TABLES
208	default y
209
210config GEN_IRQ_VECTOR_TABLE
211	default n
212
213config DISABLE_TCM_ECC
214	bool "Disable ECC on TCM"
215	help
216	  This option disables ECC checks on Tightly Coupled Memory.
217
218config DCACHE_LINE_SIZE
219	default 64 if CPU_CORTEX_R52
220	default 32
221
222config ICACHE_LINE_SIZE
223	default 64 if CPU_CORTEX_R52
224	default 32
225
226endif # CPU_AARCH32_CORTEX_R
227
228config TEST_EXTRA_STACK_SIZE
229	default 1024 if SMP
230