1# ARM Cortex-M platform configuration options 2 3# Copyright (c) 2014-2015 Wind River Systems, Inc. 4# SPDX-License-Identifier: Apache-2.0 5 6# NOTE: We have the specific core implementations first and outside of the 7# if CPU_CORTEX_M block so that SoCs can select which core they are using 8# without having to select all the options related to that core. Everything 9# else is captured inside the if CPU_CORTEX_M block so they are not exposed 10# if one select a different ARM Cortex Family (Cortex-A or Cortex-R) 11 12config CPU_CORTEX_M0 13 bool 14 select CPU_CORTEX_M 15 select ARMV6_M_ARMV8_M_BASELINE 16 help 17 This option signifies the use of a Cortex-M0 CPU 18 19config CPU_CORTEX_M0PLUS 20 bool 21 select CPU_CORTEX_M 22 select ARMV6_M_ARMV8_M_BASELINE 23 help 24 This option signifies the use of a Cortex-M0+ CPU 25 26config CPU_CORTEX_M1 27 bool 28 select CPU_CORTEX_M 29 select ARMV6_M_ARMV8_M_BASELINE 30 help 31 This option signifies the use of a Cortex-M1 CPU 32 33config CPU_CORTEX_M3 34 bool 35 select CPU_CORTEX_M 36 select ARMV7_M_ARMV8_M_MAINLINE 37 help 38 This option signifies the use of a Cortex-M3 CPU 39 40config CPU_CORTEX_M4 41 bool 42 select CPU_CORTEX_M 43 select ARMV7_M_ARMV8_M_MAINLINE 44 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 45 help 46 This option signifies the use of a Cortex-M4 CPU 47 48config CPU_CORTEX_M23 49 bool 50 select CPU_CORTEX_M 51 select ARMV8_M_BASELINE 52 select ARMV8_M_SE if CPU_HAS_TEE 53 help 54 This option signifies the use of a Cortex-M23 CPU 55 56config CPU_CORTEX_M33 57 bool 58 select CPU_CORTEX_M 59 select ARMV8_M_MAINLINE 60 select ARMV8_M_SE if CPU_HAS_TEE 61 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 62 help 63 This option signifies the use of a Cortex-M33 CPU 64 65config CPU_CORTEX_M55 66 bool 67 select CPU_CORTEX_M 68 select ARMV8_1_M_MAINLINE 69 select ARMV8_M_SE if CPU_HAS_TEE 70 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 71 select CPU_HAS_DCACHE 72 select CPU_HAS_ICACHE 73 help 74 This option signifies the use of a Cortex-M55 CPU 75 76config CPU_CORTEX_M85 77 bool 78 select CPU_CORTEX_M 79 select ARMV8_1_M_MAINLINE 80 select ARMV8_M_SE if CPU_HAS_TEE 81 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 82 select CPU_HAS_DCACHE 83 select CPU_HAS_ICACHE 84 help 85 This option signifies the use of a Cortex-M85 CPU 86 87config CPU_CORTEX_M7 88 bool 89 select CPU_CORTEX_M 90 select ARMV7_M_ARMV8_M_MAINLINE 91 select ARMV7_M_ARMV8_M_FP if CPU_HAS_FPU 92 help 93 This option signifies the use of a Cortex-M7 CPU 94 95if CPU_CORTEX_M 96 97config CPU_CORTEX_M_HAS_SYSTICK 98 bool 99 help 100 This option is enabled when the CPU implements the SysTick timer. 101 102config DCACHE_LINE_SIZE 103 default 32 104 105config ICACHE_LINE_SIZE 106 default 32 107 108config CPU_CORTEX_M_HAS_DWT 109 bool 110 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M0PLUS && !CPU_CORTEX_M1 111 help 112 This option signifies that the CPU implements the Data Watchpoint and 113 Trace (DWT) unit specified by the ARMv7-M and above. 114 115 While ARMv6-M does define a "DWT" unit, this is significantly different 116 from the DWT specified by the ARMv7-M and above in terms of both feature 117 set and register mappings. 118 119config CPU_CORTEX_M_HAS_BASEPRI 120 bool 121 depends on ARMV7_M_ARMV8_M_MAINLINE 122 help 123 This option signifies the CPU has the BASEPRI register. 124 125 The BASEPRI register defines the minimum priority for 126 exception processing. When BASEPRI is set to a nonzero 127 value, it prevents the activation of all exceptions with 128 the same or lower priority level as the BASEPRI value. 129 Always present in CPUs that implement the ARMv7-M or 130 ARM8-M Mainline architectures. 131 132config CPU_CORTEX_M_HAS_VTOR 133 bool 134 depends on !CPU_CORTEX_M0 && !CPU_CORTEX_M1 135 help 136 This option signifies the CPU has the VTOR register. 137 The VTOR indicates the offset of the vector table base 138 address from memory address 0x00000000. Always present 139 in CPUs implementing the ARMv7-M or ARMv8-M architectures. 140 Optional in CPUs implementing ARMv6-M, ARMv8-M Baseline 141 architectures (except for Cortex-M0/M1, where it is never 142 implemented). 143 144config CPU_CORTEX_M_HAS_SPLIM 145 bool 146 depends on ARMV8_M_MAINLINE || (ARMV8_M_SE && !ARM_NONSECURE_FIRMWARE) 147 help 148 This option signifies the CPU has the MSPLIM, PSPLIM registers. 149 150 The stack pointer limit registers, MSPLIM, PSPLIM, limit the 151 extend to which the Main and Process Stack Pointers, respectively, 152 can descend. MSPLIM, PSPLIM are always present in ARMv8-M 153 MCUs that implement the ARMv8-M Main Extension (Mainline). 154 155 In an ARMv8-M Mainline implementation with the Security Extension 156 the MSPLIM, PSPLIM registers have additional Secure instances. 157 In an ARMv8-M Baseline implementation with the Security Extension 158 the MSPLIM, PSPLIM registers have only Secure instances. 159 160config CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 161 bool 162 depends on ARMV7_M_ARMV8_M_MAINLINE 163 help 164 This option signifies the CPU may trigger system faults 165 (other than HardFault) with configurable priority, and, 166 therefore, it needs to reserve a priority level for them. 167 168config CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 169 bool 170 depends on ARMV6_M_ARMV8_M_BASELINE 171 help 172 This option signifies the Cortex-M0 has some mechanisms that can map 173 the vector table to SRAM 174 175config CPU_CORTEX_M_HAS_CMSE 176 bool 177 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 178 help 179 This option signifies the Cortex-M CPU has the CMSE intrinsics. 180 181config ARMV6_M_ARMV8_M_BASELINE 182 bool 183 select ATOMIC_OPERATIONS_C if !ARMV8_M_BASELINE 184 select ISA_THUMB2 185 help 186 This option signifies the use of an ARMv6-M processor 187 implementation, or the use of an ARMv8-M processor 188 supporting the Baseline implementation. 189 190 Notes: 191 - A Processing Element (PE) without the Main Extension 192 is also referred to as a Baseline Implementation. A 193 Baseline implementation has a subset of the instructions, 194 registers, and features, of a Mainline implementation. 195 - ARMv6-M compatibility is provided by all ARMv8-M 196 implementations. 197 198config ARMV8_M_BASELINE 199 bool 200 select ARMV6_M_ARMV8_M_BASELINE 201 select CPU_CORTEX_M_HAS_CMSE 202 help 203 This option signifies the use of an ARMv8-M processor 204 implementation. 205 206 ARMv8-M Baseline includes additional features 207 not present in the ARMv6-M architecture. 208 209config ARMV7_M_ARMV8_M_MAINLINE 210 bool 211 select ATOMIC_OPERATIONS_BUILTIN 212 select ISA_THUMB2 213 select CPU_CORTEX_M_HAS_BASEPRI 214 select CPU_CORTEX_M_HAS_VTOR 215 select CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS 216 select CPU_CORTEX_M_HAS_SYSTICK 217 help 218 This option signifies the use of an ARMv7-M processor 219 implementation, or the use of a backwards-compatible 220 ARMv8-M processor implementation supporting the Main 221 Extension. 222 223 Notes: 224 - A Processing Element (PE) with the Main Extension is also 225 referred to as a Mainline Implementation. 226 - ARMv7-M compatibility requires the Main Extension. 227 228 From https://developer.arm.com/products/architecture/m-profile: 229 The Main Extension provides backwards compatibility 230 with ARMv7-M. 231 232config ARMV8_M_MAINLINE 233 bool 234 select ARMV7_M_ARMV8_M_MAINLINE 235 select CPU_CORTEX_M_HAS_SPLIM 236 select CPU_CORTEX_M_HAS_CMSE 237 help 238 This option signifies the use of an ARMv8-M processor 239 implementation, supporting the Main Extension. 240 241 ARMv8-M Main Extension includes additional features 242 not present in the ARMv7-M architecture. 243 244config ARMV8_1_M_MAINLINE 245 bool 246 select ARMV8_M_MAINLINE 247 help 248 This option signifies the use of an ARMv8.1-M processor 249 implementation, supporting the Main Extension. 250 251 ARMv8.1-M Main Extension includes additional features 252 not present in the ARMv8-M architecture. 253 254config ARMV8_M_SE 255 bool 256 depends on ARMV8_M_BASELINE || ARMV8_M_MAINLINE 257 select CPU_CORTEX_M_HAS_SPLIM if !ARM_NONSECURE_FIRMWARE 258 help 259 This option signifies the use of an ARMv8-M processor 260 implementation (Baseline or Mainline) supporting the 261 Security Extensions. 262 263config ARMV7_M_ARMV8_M_FP 264 bool 265 depends on ARMV7_M_ARMV8_M_MAINLINE && !CPU_CORTEX_M3 266 imply FPU_SHARING 267 help 268 This option signifies the use of an ARMv7-M processor 269 implementation, or the use of an ARMv8-M processor 270 implementation supporting the Floating-Point Extension. 271 272config ARMV8_M_DSP 273 bool 274 depends on ARMV8_M_MAINLINE 275 help 276 This option signifies the use of an ARMv8-M processor 277 implementation supporting the DSP Extension. 278 279config ARMV8_1_M_MVEI 280 bool 281 depends on ARMV8_1_M_MAINLINE 282 depends on ARMV8_M_DSP 283 help 284 This option signifies the use of an ARMv8.1-M processor implementation 285 supporting the M-Profile Vector Extension (MVE) integer instruction set. 286 287config ARMV8_1_M_MVEF 288 bool 289 depends on ARMV8_1_M_MVEI 290 help 291 This option signifies the use of an ARMv8.1-M processor implementation 292 supporting the M-Profile Vector Extension (MVE) floating-point 293 instruction set. 294 295config ARMV8_1_M_PMU 296 bool 297 help 298 This option is enabled when the CPU implements ARMv8-M Performance 299 Monitoring Unit (PMU). 300 301config ARMV8_M_PMU_EVENTCNT 302 int "Number of event counters in the Performance Monitoring Unit" 303 depends on ARMV8_1_M_PMU 304 range 2 8 305 help 306 The number of event counters implemented. 307 308menu "ARM Cortex-M0/M0+/M1/M3/M4/M7/M23/M33/M55 options" 309 depends on ARMV6_M_ARMV8_M_BASELINE || ARMV7_M_ARMV8_M_MAINLINE 310 311config GEN_ISR_TABLES 312 default y 313 314config ZERO_LATENCY_IRQS 315 bool "Zero-latency interrupts" 316 depends on CPU_CORTEX_M_HAS_BASEPRI 317 help 318 The kernel may reserve some of the highest interrupts priorities in 319 the system for its own use. These interrupts will not be masked 320 by interrupt locking. 321 When connecting interrupts the kernel will offset all interrupts 322 to lower priority than those reserved by the kernel. 323 Zero-latency interrupt can be used to set up an interrupt at the 324 highest interrupt priority which will not be blocked by interrupt 325 locking. 326 Since Zero-latency ISRs will run in the same priority or possibly at 327 higher priority than the rest of the kernel they cannot use any 328 kernel functionality. 329 330config ZERO_LATENCY_LEVELS 331 int "Number of interrupt priority levels reserved for zero latency" 332 depends on ZERO_LATENCY_IRQS 333 range 1 $(UINT8_MAX) 334 help 335 The amount of interrupt priority levels reserved for zero latency 336 interrupts. Increase this value to reserve more than one priority 337 level for zero latency interrupts. 338 339config DYNAMIC_DIRECT_INTERRUPTS 340 bool "Support for dynamic direct interrupts" 341 depends on DYNAMIC_INTERRUPTS 342 help 343 Direct interrupts are designed for performance-critical interrupt 344 handling and do not go through all of the common interrupt handling 345 code. This option enables the installation of interrupt service 346 routines for direct interrupts at runtime. 347 Note: this requires enabling support for dynamic interrupts in the 348 kernel. 349 350config SW_VECTOR_RELAY 351 bool "Software Vector Relay" 352 help 353 When building a bootloader firmware this option adds a 354 vector table relay handler and a vector relay table, to 355 relay interrupts based on a vector table pointer. 356 This is only required but not limited to Cortex-M Baseline CPUs 357 with no hardware vector table relocation mechanisms (e.g. VTOR). 358 359config SW_VECTOR_RELAY_CLIENT 360 bool "Software Vector Relay (client)" 361 default y if BOOTLOADER_MCUBOOT && !CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP 362 depends on !CPU_CORTEX_M_HAS_VTOR 363 help 364 Another image has enabled SW_VECTOR_RELAY, and will be forwarding 365 exceptions and HW interrupts to this image. Enable this option to make 366 sure the vector table pointer in RAM is set properly by the image upon 367 initialization. 368 369config CORTEX_M_DWT 370 bool "Data Watchpoint and Trace (DWT)" 371 depends on CPU_CORTEX_M_HAS_DWT 372 default y if TIMING_FUNCTIONS 373 help 374 Enable and use the Data Watchpoint and Trace (DWT) unit for 375 timing functions. 376 377config CORTEX_M_DEBUG_MONITOR_HOOK 378 bool "Debug monitor interrupt for debugging" 379 depends on !ARMV6_M_ARMV8_M_BASELINE 380 help 381 Enable this option to configure debug monitor exception to low priority 382 for debugging purposes. 383 384# enabled, which may increase ESF stacking requirements for 385# threads. 386config TEST_EXTRA_STACK_SIZE 387 default 512 if TEST_ARM_CORTEX_M && FPU_SHARING 388 389config TRAP_UNALIGNED_ACCESS 390 bool "Unaligned access trap" 391 depends on !ARMV6_M_ARMV8_M_BASELINE 392 help 393 If enabled, the CPU generates a UsageFault exception when executing a 394 halfword or word access. 395 396endmenu 397 398# Implement the null pointer detection using either the Data Watchpoint and 399# Trace Unit and the Debug Monitor Exception, or the Memory Protection Unit. 400 401choice NULL_POINTER_EXCEPTION_DETECTION 402 bool "Null-pointer exception" 403 # Disable this until https://github.com/zephyrproject-rtos/zephyr/issues/32984 is fixed 404 # default NULL_POINTER_EXCEPTION_DETECTION_DWT if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && CPU_CORTEX_M_HAS_DWT 405 default NULL_POINTER_EXCEPTION_DETECTION_MPU if TEST_ARM_CORTEX_M && !ARM_NONSECURE_FIRMWARE && ARM_MPU && !CPU_CORTEX_M_HAS_DWT 406 default NULL_POINTER_EXCEPTION_DETECTION_NONE 407 help 408 There are 2 implementations available, one based 409 on DWT and the other based on MPU. Use this choice 410 symbol to select one of the options. By default the 411 feature is disabled. In the test suite the feature 412 is enabled and the DWT-based solution is preferred. 413 414config NULL_POINTER_EXCEPTION_DETECTION_NONE 415 bool "No null pointer exception detection" 416 help 417 Null pointer exception detection feature is not 418 enabled. 419 420config NULL_POINTER_EXCEPTION_DETECTION_DWT 421 bool "Use DWT for null pointer exception detection" 422 depends on CPU_CORTEX_M_HAS_DWT 423 depends on !TRUSTED_EXECUTION_NONSECURE 424 select CORTEX_M_DWT 425 select CORTEX_M_NULL_POINTER_EXCEPTION 426 help 427 Null pointer dereference detection implemented 428 using the DWT unit functionality. 429 Notes: 430 - Not enabled for Non-Secure FW images, where 431 null-pointer dereferencing is likely caught as 432 a SecureFault. 433 - Requires DWT functionality in the Cortex-M SoC 434 implementation (1 comparator for ARMv7-M, 2 comparators 435 for ARMv8-M). 436 - Requires the Cortex-M core be in normal mode. 437 438config NULL_POINTER_EXCEPTION_DETECTION_MPU 439 bool "Use MPU for null pointer exception detection" 440 depends on !TRUSTED_EXECUTION_NONSECURE 441 depends on ARM_MPU 442 select CORTEX_M_NULL_POINTER_EXCEPTION 443 help 444 Null pointer dereference detection implemented 445 using MPU functionality. 446 Notes: 447 - Mutually exclusive to the DWT-based solution 448 - Not enabled for Non-Secure FW images, where 449 null-pointer dereferencing is likely caught as 450 a SecureFault. 451 - Requires MPU functionality to be present and 452 enabled. The implementation consumes 1 MPU region. 453 - In ARMv8-M, explicit null-pointer dereference 454 detection with MPU requires, additionally, that 455 the area: [0x0, 456 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE) 457 is not unmapped (covered by an MPU region already). 458 If it is unmapped null-pointer dereferencing may 459 still be indirectly detected (e.g. via a precise 460 Bus access fault), but this is not guaranteed. A 461 build-time message warns the user of this scenario. 462 463endchoice 464 465config CORTEX_M_NULL_POINTER_EXCEPTION 466 bool 467 help 468 Enable and use the null pointer exception option. 469 This is a debug feature in Cortex-M, allowing for 470 detecting null pointer dereferencing (raising a 471 CPU fault). Supporting the feature results in an 472 increased code footprint, determined by option 473 CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE. 474 475 Note: this hidden option is selected by the choice 476 symbols corresponding to the DWT-based or to the 477 MPU-based solution. 478 479if CORTEX_M_NULL_POINTER_EXCEPTION 480 481config CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE 482 hex "Size of paged unmapped to implement null pointer detection" 483 default 0x400 484 help 485 Size of the page reserved for detecting null pointer 486 dereferencing. Must be a power of two. A large value 487 offers enhanced detection performance to the cost of 488 wasting a large flash area that code may not use. 489 490endif # CORTEX_M_NULL_POINTER_EXCEPTION 491 492rsource "tz/Kconfig" 493 494endif # CPU_CORTEX_M 495
